LTC672 Tiny Micropower, Low Votage Dua Comparators FEATURES n Low Suppy Operation:.7V Minimum n Low Suppy Current: 3μA/Comparator Maximum n Propagation Deay: ns Maximum ( C to 2 C) n 3.2MHz Togge Frequency n Input Votage Range Extends Beow Ground n Interna Hysteresis: n High Output Drive: TTL and CMOS Compatibe Specifi ed at ±ma ( C to 2 C), Capacitive Load Handing to,pf n Specifi ed for C to 2 C Temperature Range n Avaiabe in Low Profi e (mm) ThinSOT and 2mm 2mm DFN Packages APPLICATIONS n Battery Powered Systems n Window Comparators n Threshod Detectors/Discriminators n Cock Regeneration n Automotive Sensing and Contros DESCRIPTION The LTC 672 is an extremey sma dua comparator designed to maximize battery ife whie providing both speed and ow votage operation in appications where board space is a premium. These comparators operate on suppies between.7v and.v, and have a maximum guaranteed propagation deay of ns whie drawing ony 3μA maximum quiescent current. Interna hysteresis desensitizes the LTC672 to input noise and makes it easy to use, even with sow moving signas. CMOS inputs aow the use of arge source impedances. The LTC672 is avaiabe in the 8-pin SOT-23 and the tiny 2mm 2mm DFN package. L, LT, LTC, LTM, Linear Technoogy and the Linear ogo are registered trademarks of Linear Technoogy Corporation. ThinSOT is a trademark of Linear Technoogy Corporation. A other trademarks are the property of their respective owners. TYPICAL APPLICATION Cock Regeneration Circuit Propagation Deay vs Input Overdrive.μF V R = REFERENCE LT66 FB C.μF k /2 LTC672 672 TA RECOVERED CLOCK (UP TO 3.2MHz) PROPAGATION DELAY (ns) 6 3 2 V = V V STEP = FALLG RISG C LOAD = pf T A = 2 C CLOCK PUT > P-P 2 3 6 7 8 PUT OVERDRIVE () 672 TAb
LTC672 ABSOLUTE MAXIMUM RATGS Suppy Votage (V to )...6V Input Votage...6V Input Current...mA Output Short-Circuit Duration (Note 2)... Indefinite Operating Temperature Range (Note 3) LTC672C... C to 8 C LTC672I... C to 8 C LTC672H... C to 2 C (Note ) Specified Temperature Range (Note ) LTC672C... C to 7 C LTC672I... C to 8 C LTC672H... C to 2 C Junction Temperature... C Storage Temperature Range...6 C to C Lead Temperature (Sodering, sec) TSOT Packages... 3 C P CONFIGURATION TOP VIEW A A A 8 2 9 A 7 3 B 6 V B B B A A A TOP VIEW V B B B DC PACKAGE 8-LEAD (2mm 2mm) PLASTIC DFN T JMAX = C, θ JA = 2 C/W EXPOSED PAD (P 9) IS, MUST BE SOLDERED TO PCB TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 T JMAX = C, θ JA = 3 C/W ORDER FORMATION Lead Free Finish TAPE AND REEL (MI) TAPE AND REEL PART MARKG* PACKAGE DESCRIPTION SPECIFIED TEMPERATURE RANGE LTC672CDC#TRMPBF LTC672CDC#TRPBF LCZJ 8-Lead (2mm 2mm) Pastic DFN C to 7 C LTC672IDC#TRMPBF LTC672IDC#TRPBF LCZJ 8-Lead (2mm 2mm) Pastic DFN C to 8 C LTC672HDC#TRMPBF LTC672HDC#TRPBF LCZJ 8-Lead (2mm 2mm) Pastic DFN C to 2 C LTC672CTS8#TRMPBF LTC672CTS8#TRPBF LTCZK 8-Lead Pastic TSOT-23 C to 7 C LTC672ITS8#TRMPBF LTC672ITS8#TRPBF LTCZK 8-Lead Pastic TSOT-23 C to 8 C LTC672HTS8#TRMPBF LTC672HTS8#TRPBF LTCZK 8-Lead Pastic TSOT-23 C to 2 C TRM = pieces. *Temperature grades are identifi ed by a abe on the shipping container. Consut LTC Marketing for parts specified with wider operating temperature ranges. Consut LTC Marketing for information on ead based finish parts. For more information on ead free part marking, go to: http://www.inear.com/eadfree/ For more information on tape and ree specifi cations, go to: http://www.inear.com/tapeandree/ 2
ELECTRICAL CHARACTERISTICS LTC672 The denotes the specifi cations which appy over the fu specifi ed temperature range, otherwise specifi cations are at T A = 2 C., V CM =.V, C = 2pF, uness otherwise noted. SYMBOL PARAMETER CONDITIONS M TYP MAX UNITS V Suppy Votage Guaranteed by PSRR.7. V I Suppy Current per Comparator 2 3 μa μa V = V 2 32 μa 2 μa V OS Input Offset Votage (Note ) LTC672C/LTC672I LTC672H V HYST Input Hysteresis Votage (Note ) LTC672C/LTC672I LTC672H 2..6.6 3. 6.3 6.2 7.2 8.2 ΔV OS /ΔT Input Offset Votage Drift (Note ) 6 μv/ C I Input Leakage Current. na LTC672C/LTC672I LTC672H na na CMRR Common Mode Rejection Ratio V CM =.V to V DD.2V 8 7 db 6 db Input Votage Range Guaranteed by CMRR. V DD.2 V PSRR Power Suppy Rejection Ratio V =.7V to.v, V CM =.V 6 6 db db V OL Output Swing Low Overdrive = 2 (Note 6) I SK = μa I SK = ma V OH Output Swing High Overdrive = 2 (Note 6) I SOURCE = μa I SOURCE = ma t PD Propagation Deay (Note 7) 2 3 32 ns ns Δt PD Differentia Propagation Deay Between Channes ns t SKEW Propagation Deay Skew Between t PDLH /t PDHL ns t r Output Rise Time ns t f Output Fa Time ns f MAX Maximum Togge Frequency 3.2 MHz I SC Short-Circuit Current V = V ±2 ma Note : Stresses beyond those isted under Absoute Maximum Ratings may cause permanent damage to the device. Exposure to any Absoute Maximum Rating condition for extended periods may affect device reiabiity and ifetime. Note 2: A heat sink may be required to keep the junction temperature beow absoute maximum. This depends on the power suppy votage and how many comparators are shorted. The θ JA specifi ed for the DC and TS packages is with minima PCB heat spreading meta. Using expanded meta area on a ayers of a board reduces this vaue. Note 3: The LTC672C and LTC672I are guaranteed functiona over the temperature range of C to 8 C. The LTC672H is guaranteed functiona over the operating temperature range of C to 2 C. Note : The LTC672C is guaranteed to meet specified performance from C to 7 C. The LTC672C is designed, characterized and expected to meet specifi ed performance from C to 8 C but is not tested or QA samped at these temperatures. The LTC672I is guaranteed to meet specifi ed performance from C to 8 C. The LTC672H is guaranteed to meet specifi ed performance from C to 2 C. Note : The LTC672 comparators incude interna hysteresis. The offset votage is defi ned as the average of the input votages (trip points) required to change the output in each direction minus V CM, whie the hysteresis votage is the difference of these trip points. Note 6: Output votage swings are measured between the output and power suppy rais. Note 7: Propagation deay is for 2 steps, and of overdrive. Overdrive is measured reative to the positive and negative trip points. 3
LTC672 TYPICAL PERFORMANCE CHARACTERISTICS SUPPLY CURRENT PER COMPARATOR (μa) 3 2 Suppy Current vs Suppy Votage 2 C 2 C C 2 3 6 SUPPLY VOLTAGE (V) SUPPLY CURRENT PER COMPARATOR (μa) 3 3 2 2 Suppy Current vs Temperature V = V 2 2 7 2 TEMPERATURE ( C) V =.7V PUT LEAKAGE CURRENT (na) 3 2 Input Leakage Current vs Input Votage C 2 C 2 C 8 C 2 3 6 PUT VOLTAGE (V) 672 G 672 G2 672 G3 PUT OFFSET CURRENT (pa) 9 8 7 6 3 2 Input Offset Current vs Input Votage 2 C 8 C 2 C C 2 3 6 PUT VOLTAGE (V) SUPPLY CURRENT PER COMPARATOR (μa) 3 3 2 2 k Suppy Current vs Togge Rate V STEP = 2 OVERDRIVE = T A = 2 C NO C LOAD V = V V =.7V k M M TOGGLE RATE (Hz) MAXIMUM TOGGLE RATE (MHz) 3 Maximum Togge Rate vs Temperature 2 V STEP = 2 OVERDRIVE = C LOAD = pf V = V V =.7V 2 2 7 2 TEMPERATURE ( C) 672 G 672 G 672 G6 Input Offset Votage vs Suppy Votage 8 Hysteresis vs Suppy Votage V Input Common Mode Limits vs Temperature PUT OFFSET VOLTAGE () 3 2 2 3 2 C C 2 C HYSTERESIS () 7 6 3 2 2 C 2 C C PUT COMMON MODE LIMITS (V) V. V. V.. 2 3 6 SUPPLY VOLTAGE (V) 2 3 6 SUPPLY VOLTAGE (V). 2 2 7 2 TEMPERATURE ( C) 672 G7 672 G8 672 G9
TYPICAL PERFORMANCE CHARACTERISTICS LTC672 PROPAGATION DELAY (ns) 2 38 36 3 32 3 28 Propagation Deay vs Suppy Votage V STEP = C LOAD = pf RISG FALLG 2 3 6 SUPPLY VOLTAGE (V) 2 C, 2 C RISG FALLG 672 G PROPAGATION DELAY (ns) 8 7 6 3 2 Propagation Deay vs Load Capacitance V STEP = OVERDRIVE = T A = 2 C V =.7V FALLG RISG, V FALLG RISG LOAD CAPACITANCE (pf) 672 TIME (ns) Output Rise and Fa Times vs Load Capacitance V STEP = OVERDRIVE = T A = 2 C t r t r t r t f t f t f V =.7V V = V LOAD CAPACITANCE (pf) 672 G2 PUT VOLTAGE (V)... Output Low Votage vs Load Current T A = 2 C V =.7V V = V PUT VOLTAGE (V -V ) (V)... Output High Votage vs Load Current T A = 2 C V =.7V V = V PUT VOLTAGE () 9 8 7 6 3 2 Output Votage vs Temperature HIGH = V V I = ±ma V =.7V V = V HIGH LOW HIGH LOW.. SK CURRENT (ma).. SOURCE CURRENT (ma) 2 2 7 2 TEMPERATURE ( C) 672 G3 672 G 672 G Propagation Deay Propagation Deay with Load MHz Sinusoid Response k V V/DIV V V/DIV 2Ω V V/DIV V /DIV V /DIV V /DIV C L = 2pF V CM = ns/div 672 G6 C L = 2pF ns/div V CM = R L = k, 2Ω 672 G7 C L = 2pF V CM = 2ns/DIV 672 G8
LTC672 P FUNCTIONS A (Pin ): Output of Comparator A. A (Pin 2): Inverting Input of Comparator A. A (Pin 3): Noninverting Input of Comparator A. (Pin ): Ground. B (Pin ): Noninverting Input of Comparator B. B (Pin 6): Inverting Input of Comparator B. B (Pin 7): Output of Comparator B. V (Pin 8): Positive Suppy Votage Exposed Pad (Pin 9, DC Package Ony): Ground. The Exposed Pad must be sodered to PCB. SIMPLIFIED SCHEMATIC V 7Ω 7Ω 672 SS 6
APPLICATIONS FORMATION The LTC672 device is a fast (ns deay), ow power, ow votage (.7V to.v suppy) genera purpose dua comparator. It provides rai-to-rai outputs abe to interface to TTL/CMOS, draws ow suppy currents (3μA/comparator), and has interna hysteresis (approximatey ). Hysteresis Each comparator has buit-in hysteresis to simpify designs, to insure stabe operation in the presence of noise at the inputs, and to reject suppy rai noise. The reference votage appied to the input is not the exact switching threshod vaue due to the buit-in hysteresis. Actua output switching typicay occurs within ±2.2 of the reference votage, pus or minus the input offset votage. Externa positive feedback circuitry can be empoyed to increase effective hysteresis if desired, as shown in Figure. This circuitry wi provide an apparent effect on both the rising and faing input threshods (the actua interna trip points remain unaffected). If an inverting confi guration with hysteresis is needed, simpy swap the V and V REF connections. Unused Inputs Any unused inputs shoud be connected in a way that fixes the output ogic state high or ow. One easy way to do this is to tie to V and to. LTC672 Input Protection Externa input protection circuitry is ony needed if currents woud otherwise exceed the absoute maximum rating. Inputs driven further negative than beow ground wi not cause damage provided the current is imited to ma. ESD protection diodes are provided to prevent damage during handing. Comparator Input The aowabe input votage ranges from beow to within.2v of the positive suppy. The input may be forced beow ground without causing an improper output, though some additiona input current wi begin to fow from the ESD input protection diode. The inputs can reach up to 6V independent of the V suppy votage without causing additiona input current or damage to the part. As ong as one input is within the aowabe input votage range, the LTC672 wi continue to function normay. Comparator Output The comparator output is a push-pu CMOS stage guaranteed to swing to within 3 of V and 2 of ground, over temperature when sourcing or sinking ma. No externa pu-up/down resistor is required. To V R R2 V REF R3 /2 LTC672 672 F R Additiona Hystersis = V R3 Trip Votages : V ( L H) = VREF R R R2 R3 V = V ( H L) REF R R V R R2 R3 R3 Exampe: Additiona Hysteresis =, V = V R= k R2 = 29k R3= M FOR VREF =. V: V ( L H) = 2. V V (H L) =. 7V Figure. Additiona Hysteresis Circuit for Noninverting Confi guration 7
LTC672 APPLICATIONS FORMATION maintain micropower operation, the output stage uses a break-before-make circuit. The break interva of this circuit turns off both the pu-up and pu-down devices for tens of nanoseconds before activating the appropriate output transistor (depends on the output transition direction). Any oad connected to the output wi charge or discharge interna capacitance during this interva. This can create a soft corner during output transitions and aso decrease the propagation deay. The Typica Performance Characteristics section shows this behavior under three oad conditions: unoaded, k to ground and 2Ω to ground. Loads to V have a simiar affect when the output is transitioning from ow to high. Power Suppies The comparator circuitry operates from a singe.7v to.v. A.μF minimum bypass capacitor is required between the V pin and. When the output is sinking at east ma, a μf bypass capacitor is recommended. Pusing the V suppy to the comparators on and off may engage the ESD protection circuitry at the V pin. If this occurs, current is pued from the V pin through the output stage. Using the recommended suppy bypass capacitors with some series resistance in the V suppy ine wi hep to prevent this action in pused suppy appications. Leve Transators The eve transators in the Typica Appications section show an adjustabe high-precision votage reference enabing the user to vary the threshod votage. Simpy adjusting the ratio of the two resistors changes the threshod votage according to the foowing equation: V THR =. R F R G TYPICAL APPLICATIONS Low to High Leve Transator.V.μF LT66 FB 2.9k k μf 2V V /2 LTC672.V V 672 TA2 8
TYPICAL APPLICATIONS LTC672 High to Low Leve Transator.8V.μF LT66 FB 2.9k k μf 6V V /2 LTC672.8V V 672 TA3 Micropower Battery Monitor with Fast Response V BATT R 99k LTC672 C.μF.μF LT79-.2 μf COMPB B (V IF V BATT < 2.V) R2 332k COMPA A (V IF V BATT < 2.8V) R3 M 672 TA 9
LTC672 PACKAGE DESCRIPTION DC Package 8-Lead Pastic DFN (2mm 2mm) (Reference LTC DWG # -8-79 Rev A).7. 2.....6. (2 SIDES) PACKAGE LE.2.. BSC.37. (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R =. TYP R =. TYP 8.. P BAR TOP MARK (SEE NOTE 6).2 REF 2.. ( SIDES).7....6. (2 SIDES).23.. BSC.37. (2 SIDES) BOTTOM VIEW EXPOSED PAD P NOTCH R =.2 OR.2 CHAMFER (DC8) DFN 6 REVØ NOTE:. DRAWG IS NOT A JEDEC PACKAGE LE 2. DRAWG NOT TO SCALE 3. ALL DIMENSIONS ARE MILLIMETERS. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT CLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED.mm ON ANY SIDE. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR P LOCATION ON THE TOP AND BOTTOM OF PACKAGE
PACKAGE DESCRIPTION TS8 Package 8-Lead Pastic TSOT-23 (Reference LTC DWG # -8-637) LTC672.2 MAX.6 REF 2.9 BSC (NOTE ).22 REF 3.8 MAX 2.62 REF. M 2.8 BSC..7 (NOTE ) P ONE ID RECOMMENDED SOLDER PAD LAY PER IPC CALCULATOR.6 BSC.22.36 8 PLCS (NOTE 3).8.9.2 BSC DATUM A. MAX...3. REF.9.2.9 BSC (NOTE 3) TS8 TSOT-23 82 NOTE:. DIMENSIONS ARE MILLIMETERS 2. DRAWG NOT TO SCALE 3. DIMENSIONS ARE CLUSIVE OF PLATG. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR. MOLD FLASH SHALL NOT EXCEED.2mm 6. JEDEC PACKAGE REFERENCE IS MO-93 Information furnished by Linear Technoogy Corporation is beieved to be accurate and reiabe. However, no responsibiity is assumed for its use. Linear Technoogy Corporation makes no representation that the interconnection of its circuits as described herein wi not infringe on existing patent rights.
LTC672 TYPICAL APPLICATION Dua Low Side Current Sense Aarm.V LTC672 V LED B k LOAD B I LOADB R SB.Ω.μF LT66 FB μf 2.9k COMP B LED A 37.k k 6.9k COMP A LOAD A I LOADA R SA.Ω 672 TA LEDA ON IF I LOADA > 2.A LEDB ON IF I LOADB >.A RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC/LTC2 LTC/LTC2 LTC82/LTC83 Dua Utraow Power Comparators with Reference Micropower Ampifi er with Comparator and Reference Dua Utraow Power Comparators with Reference.82V ±% Reference, 8μs Propagation Deay,.7μA.2V ±.8% Reference, Ampifi er Stabe with pf Load.82V ±% Reference, μs, 3.μA, Open-Drain Out LT666 Tiny Micropower Precision Series References.2% Reference, 2ppm/ C Drift, 2mA Output, 2mm 2mm DFN Package LT67-/LT67-2/ LT67-3 Dua Comparators with Reference.V to 8V Operating Range, 8μs Propagation Deay, SOT-23 Package LT673-2/LT673-3 Tiny Singe Comparator with Reference.V to 8V Operating Range, 8μs Propagation Deay, 2mm 2mm DFN Package 2 LT 69 REV A PRTED USA Linear Technoogy Corporation 63 McCarthy Bvd., Mipitas, CA 93-77 (8) 32-9 FAX: (8) 3-7 www.inear.com LEAR TECHNOLOGY CORPORATION 27