ILI2117 ILI2117 Capacitive Touch Controller Datasheet Version: V1.01 Release Date: SEP. 09,2015 ILI TECHNOLOGY CORP. 8F, No.38, Taiyuan St., Jhubei City, Hsinchu County 302, Taiwan, R.O.C Tel.886-3-5600099; Fax.886-3-5600055 http://www.ilitek.com
List of Chapters 1 DESCRIPTION... 4 2 FEATURE... 4 3 BLOCK DIAGRAM... 4 4 PIN CONFIGURATION... 5 4.1 QFN52 (6X6MM 2, 0.4MM PITCH SIZE)... 5 4.2 PINOUT DESCRIPTION... 6 5 ELECTRICAL CHARACTER... 7 5.1 ABSOLUTE MAXIMUM RATINGS... 7 5.2 DC CHARACTERISTICS... 7 5.3 ESD INFORMATION... 8 5.4 AC CHARACTERISTICS OF THE SDA AND SCL ON I 2 C INTERFACE... 8 6 PACKAGE INFORMATION... 9 6.1 QFN52 6X6X0.6MM 3... 9 7 APPLICATION... 10 7.1 REFERENCE APPLICATION CIRCUIT... 10 7.2 POWER ON RESET... 11 2015/09/09 Page 2 of 12 Version: 1.01
List of Figures Figure 3-1: ILI2117 Block Diagram... 4 Figure 4-1: ILI2117 (QFN52) Package Diagram... 5 Figure 5-1: The timing of I 2 C Interface... 8 Figure 6-1: Package Information of QFN52 6x6x0.6mm 3... 9 Figure 7-1 : Typical application circuit... 10 Figure 7-2: Recommend power on reset timing... 11 List of Tables Table 4-1: ILI2117 Pin Assignments... 6 Table 4-2: Type Define... 6 Table 5-1: Absolute Maximum Ratings... 7 Table 5-2: Power Supply... 7 Table 5-3: DC Characteristics (T opr = 25 )... 7 Table 5-4: ESD Information... 8 Table 5-5: Characteristics of the SDA and SCL bus lines... 8 Table 6-1: Package Information... 9 2015/09/09 Page 3 of 12 Version: 1.01
1 Description ILI2117 is a single chip capacitive touch controller optimized for Mobile, Tablet, Industrial application. It is a SOC with specialized 32-bit MCU and 26 driving and 14 sensing channels. ILI2117 is designed to perform the best performance and supported up to 7 application. The 10-point touch is supported and report rate is up to 100Hz. 2 Feature Channel: 40 programmable capacitive driving and sensing channel (max TX/RX = 26/14) Package: 52 pin, QFN 6x6mm 2 _0.4P Cover Lens Thickness : 0.5mm~2mm(by TP structure) Support TP Structure:GFF GFM OGS on cell Waterproof Water-spray: Robust single-touch drawing without false touch 1cc: Robust single-touch drawing without false touch Puddle: No false touch, normal touch events after wiping out water Support Smart Wake Up Support Letter : o,w,m,e,c,>,<,v,^, double click User Define High Sensitivity Support different gloves up to 3.5mm. Support Passive Stylus 2phi Tools Sensor Test Tool FPC Test Tool Tunning Tool 3 Block Diagram AFE DIGITAL FUNCTIONS INTERFACE MTP I2C High Resolution CDC Programmable for Tx/Rx CDC Control 32-bit MCU SRAM Watchdog Timers ANALOG FUNCTIONS GPIO UART Internal 48M Oscillator Regulator LVD POR Figure 3-1: ILI2117 Block Diagram 2015/09/09 Page 4 of 12 Version: 1.01
TX8 TX7 TX6 TX5 TX4 TX3 TX2 TX1 TX0 GND RX0 RX1 RX2 40 41 42 43 44 45 46 47 48 49 50 51 52 26 25 24 23 22 21 20 19 18 17 16 15 14 TX22 TX23 TX24 TX25 RSTN VDDIO SCL SDA NC TX INT GND VDD16 Capacitive Touch Controller ILI2117 4 Pin Configuration 4.1 QFN52 (6x6mm 2, 0.4mm pitch size) RX3 1 39 TX9 RX4 2 38 TX10 RX5 3 37 TX11 RX6 4 36 TX12 RX7 5 35 TX13 RX8 6 34 TX14 ILI2117 QFN52 (6x6mm) RX9 7 33 TX15 RX10 8 32 TX16 RX11 9 31 TX17 RX12 10 30 TX18 RX13 11 29 TX19 VDD 12 28 TX20 GND VGH 13 27 TX21 Figure 4-1: ILI2117 (QFN52) Package Diagram 2015/09/09 Page 5 of 12 Version: 1.01
4.2 Pinout Description Table 4-1: ILI2117 Pin Assignments Pin Out Name Type Description 1~11 RX3~RX13 I(A) Programmable Receive input channel 3~13 for CTP. 12 VDD I(P) 13 VGH O(P) 14 VDD16 O(P) Power supply input pin. Connect a decoupling capacitor (2.2uF/6.3V) between VDD and GND. Charge pump voltage output pin. Connect a decoupling capacitor (2.2uF/16V X5R) between VGH and GND. Internal regulator output pin. Connect a decoupling capacitor (2.2uF/6.3V) between VDD16 and GND. 15 GND I(P) Reference ground pin. Connect to GND. 16 INT O(D) Interrupt output pin to host. 17 TX O(D) UART data transmitter pin. 18 NC X Dummy pad. 19 SDA IO(D) A serial data pin for I 2 C interface 20 SCL I(D) A serial clock pin for I 2 C interface 21 VDDIO I(D) GPIO voltage control. Connect to VDD:VDD,Floating:1.8V. Connect a decoupling capacitor (2.2uF/6.3V) between VDDIO and GND. 22 RSTN I(D) Hardware reset pin. Active low. Connect a pull-high 10KΩ 23~48 TX25~TX0 O(A) Programmable transmit output channel 25~0 for CTP. 49 GND I(P) Reference ground pin. Connect to GND. 50~52 RX0~RX2 I(A) Programmable Receive input channel 0~2 for CTP. Table 4-2: Type Define Symbol (A) (D) (P) I O IO X CTP Analog pad Digital pad Power pad Input pad Output pad Input / Output pad Dummy pad. Capacitive touch panel (sensor) Description 2015/09/09 Page 6 of 12 Version: 1.01
5 Electrical Character 5.1 Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. Functional operation of this device at these or under any other conditions above those indicated in the operational sections of this specification are not implied and exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 5-1: Absolute Maximum Ratings Item Symbol Min Max Unit System power supply voltage VDD -0.3 4 V HV power supply voltage VGH -0.3 7.2 V Operating temperature T opr -40 85 Storage temperature T stg -55 125 5.2 DC Characteristics Table 5-2: Power Supply Item Symbol Min Typ. Max Unit System power supply voltage VDD 2.8 3.3 3.6 V Charge pump power supply voltage VDD3 2.8 3.3 3.6 V System I/O supply voltage VDDIO 1.8 3.3 3.6 V RSTN slew rate V /T slew 10 V/mS Table 5-3: DC Characteristics (T opr = 25 ) Item Symbol Min Typ. Max Unit Condition Input high voltage V IH 0.7*VDDIO VDDIO V Input low voltage V IL -0.3 0.3*VDDIO V Output high voltage V OH 2.8 3.3 3.6 1.65 1.8 1.95 Output low voltage V OL 0 0.3 V Input leakage current I I 1 μa V VDDIO=VDD VDDIO= 1.8V or Floating I 2 1.425k 4.7K 7.875k Ω Standard mode (*1) C Pull-high/low impedance R po Fast mode 1.425k 1.5k 1.575k Ω (*1) Operation mode current I Op TBD ma (*2) Standby current I Idle TBD ma (*2) Sleeping current I Sleep 100 μa *1. The pull high/low impedance was defined under C b (total capacitance load for each SDA/SCL lines) 400pF for standard mode and 300pF for fast mode. If C b smaller than 400pF/300pF, I2C circuit can chose higher impedance for saving sink power. The minimum impedance was defined under I d (sink current) of 3mA. All the above condition was defined with internal pull high impendence of 4.7k to 5.3k. *2. The power consumption depends on sensor loading condition. 2015/09/09 Page 7 of 12 Version: 1.01
5.3 ESD Information Table 5-4: ESD Information Item Symbol Min Typ. Max Unit Condition Human Body Mode (HBM) HBM ±2 KV Machine Mode MM 200 V 5.4 AC Characteristics of the SDA and SCL on I 2 C interface SDA t f t r t f t Low tsu;dat t HD;STA t SP t r t BUF SCL S t SU;STO t HD;STA t HD;DAT t HIGH t SU;STA Sr P S Figure 5-1: The timing of I 2 C Interface Symbol Table 5-5: Characteristics of the SDA and SCL bus lines Parameter 100KHz 400KHz Min Max Unit Min Max Unit f SCL SCL clock frequency 0 100 khz 0 400 KHz t HD;STA Hold time (repeated) START condition. After this period, the first clock pulse is generated 4.0 µs 0.6 µs t LOW LOW period of the SCL clock 4.7 µs 1.3 µs t HIGH HIGH period of the SCL clock 4.0 µs 0.6 µs t SU;STA Set-up time for a repeated START condition 4.7 µs 0.6 µs t HD;DAT Data hold time 0 3.45 µs 0 0.9 µs t SU;DAT Data set-up time 250 ns 100 ns t r Rise time of both SDA and SCL signals 1000 ns 300 ns t f Fall time of both SDA and SCL signals 300 ns 300 ns t SU;STO Set-up time for STOP condition 4.0 µs 0.6 µs t BUF Bus free time between a STOP and START condition 4.7 µs 1.3 µs 2015/09/09 Page 8 of 12 Version: 1.01
6 Package Information 6.1 QFN52 6x6x0.6mm 3 (Unit: mm) Figure 6-1: Package Information of QFN52 6x6x0.6mm 3 Table 6-1: Package Information Symbol Min Normal Max Unit A 0.50 0.55 0.60 mm A1 0.00 0.02 0.05 mm A3 0.150 REF. mm b 0.15 0.20 0.25 mm D 6.00 BSC mm D1 4.45 4.50 4.55 mm E 6.00 BSC mm E1 4.45 4.50 4.55 mm e 0.40 BSC mm L 0.35 0.40 0.45 mm K 0.20 mm 2015/09/09 Page 9 of 12 Version: 1.01
7 Application 7.1 Reference Application Circuit VDD 2.2uF 6.3V 2.2uF 16V 2.2uF 6.3V VDD VGH VDD16 GND GND 12 13 14 15 49 1 2 RX3 RX4 INT 16 TX 17 18 10 11 RX12 RX13 SDA 19 VDD SCL 20 VDDIO 21 ILI2117 QFN52 23 24 TX25 TX24 VDDIO Level Detection VDD: VDD ; Floating: 1.8V 2.2uF 6.3V VDD 10K RSTN 22 47 48 TX1 TX0 0.1uF 6.3V 50 51 52 RX0 RX1 RX2 GND Figure 7-1 : Typical application circuit Note: 1. SCL and SDA pins have internal pull high 4.7K ohm resistor. 2015/09/09 Page 10 of 12 Version: 1.01
7.2 Power On Reset To avoid the IC operate in the wrong power condition. We recommend RSTN keep low during VDD power on. At the same time RSTN has minimum slew rate requirement for sure that the interface power detection function works well. VDD <50ms VDDIO >100ms RSTN Slew rate >10V/ms If touch INT Touch Initial >10ms Host : Output high If no output High, ignored INT Level Host : Input INT keep High Level Figure 7-2: Recommend power on reset timing 2015/09/09 Page 11 of 12 Version: 1.01
Document Revision History Version Data Author Description 1.00 2015/02/07 Hank Chen New Create 1.01 2015/09/09 Hank Chen Modify Description, Package Information 2015/09/09 Page 12 of 12 Version: 1.01