UNIT II: Clocked Synchronous Sequential Circuits CpE 411 Advanced Logic Circuits Design 1
Unit Outline Analysis of Sequential Circuits State Tables State Diagrams Flip-flop Excitation Tables Basic Design Procedure State Assignment Problem Design with Unused States CpE 411 Advanced Logic Circuits Design 2
Flip-flop Characteristic Tables (c) D Flip-flop D Q(t+1) State 0 0 Reset 1 1 Set (b) SR Flip-flop S R Q(t+1) State 0 0 Q(t) No change 0 1 0 Reset 1 0 1 Set 1 1? Undefined (d) T Flip-flop T Q(t+1) State 0 Q(t) No change 1 Q'(t) Complement CpE 411 Advanced Logic Circuits Design 3
Recall... Inputs Combinational Circuit Next State Outputs Storage Element Present State Block Diagram of a Sequential Circuit CpE 411 Advanced Logic Circuits Design 4
Recall... Inputs Combinational Circuit Next State Outputs Present State Flip-flops Clock pulses CpE 411 Advanced Logic Circuits Design 5
Analysis of Clocked Sequential Example 1 Circuits A sequential circuit with two D flip-flops, A and B; two inputs, x and y; and output, z, is specified by the following next-state and output equations: A(t+1) = x'y + xa B(t+1) = x'b + xa z = B (a) Draw the logic diagram of the circuit. (b) Derive the state table. (c) Derive the state diagram. CpE 411 Advanced Logic Circuits Design 6
Solution: (a) Logic Diagram CpE 411 Advanced Logic Circuits Design 7
Solution: (b) State Table Present State Inputs Next State Output A(t) B(t) x y A(t+1) B(t+1) z 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 0 0 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 CpE 411 Advanced Logic Circuits Design 8
Solution: (c) State Diagram CpE 411 Advanced Logic Circuits Design 9
Activity: Individual or By Pair A sequential circuit has three D flip-flops, A, B, and C, and one input, x. It is described by the following flip-flop input functions: DA = (BC + B C)x + (BC + B C )x DB = A DC = B (a) Derive the state table for the circuit. (b) Draw two state diagrams: one for x = 0 and the other for x = 1. CpE 411 Advanced Logic Circuits Design 10
Flip-flops other than the D f/f Example 2 A sequential circuit has two JK flip-flops, one input x, and one output y. The logic diagram of the circuit is shown below. Derive the state table and the state diagram of the circuit. CpE 411 Advanced Logic Circuits Design 11
Logic Diagram CpE 411 Advanced Logic Circuits Design 12
Solution The first thing to do, when a logic diagram is given, is to obtain the flip-flop input and output functions. These are the ff.: JA = B KA = B JB = (Ax + A x) = A xnor x KB = (Ax + A x) = A xnor x y = ((A'x + Ax') + B') + ((A'x + Ax')' + B) = A xor x xor B To plot the next-state values in the state table, use the characteristic table of the JK flip-flop. CpE 411 Advanced Logic Circuits Design 13
Solution: (a) State Table Present State Input Next State Output Flip-flop Inputs A(t) B(t) x A(t+1) B(t+1) y JA KA JB KB 0 0 0 0 1 0 0 1 1 1 0 0 1 0 0 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 1 1 1 1 0 1 1 0 1 0 0 0 1 1 1 1 0 1 1 0 1 1 CpE 411 Advanced Logic Circuits Design 14
Solution: (b) State Diagram CpE 411 Advanced Logic Circuits Design 15
Activity: Individual or By Pair A sequential circuit has two JK flip-flops, A and B; two inputs, x and y; and one output, z. The flip-flop input functions and the circuit output function are as follows: JA = Bx + B y KA = B xy JB = A x KB = A + xy z = Axy + Bx y (a) Draw the logic diagram of the circuit. (b) Tabulate the state table. (c) Derive the next-state equations for A and B. CpE 411 Advanced Logic Circuits Design 16
Designing using Flip-flops Characteristic tables will not be sufficient anymore Use excitation tables CpE 411 Advanced Logic Circuits Design 17
Flip-flop Excitation Tables CpE 411 Advanced Logic Circuits Design 18
Design Procedure The word description of the circuit behavior is stated. From the given information about the circuit, obtain the state table. The number of states may be reduced by state-reduction methods if the sequential circuit can be characterized by input-output relationships independent of the number of states. Assign binary values to each state if the state table obtained in step 2 or 3 contains letter symbols. CpE 411 Advanced Logic Circuits Design 19
Design Procedure Determine the number of flip-flops needed and assign a letter symbol to each. Choose the type of flip-flop to be used. From the state table, derive the circuit excitation and output tables. Using the map or any other simplification method, derive the circuit output functions and the flip-flop input functions. Draw the logic diagram. CpE 411 Advanced Logic Circuits Design 20
Example: State Diagram CpE 411 Advanced Logic Circuits Design 21
Solution: (a) State Table CpE 411 Advanced Logic Circuits Design 22
Solution: (b) State Excitation Table CpE 411 Advanced Logic Circuits Design 23
Solution: (c) K-maps CpE 411 Advanced Logic Circuits Design 24
Solution: (d) Logic Diagram CpE 411 Advanced Logic Circuits Design 25
Example: Word Problem Design a sequential circuit with two JK flip-flops, A and B, and two inputs, E and x. If E = 0, the circuit remains in the same state regardless of the value of x. When E = 1 and x = 1, the circuit goes through the state transitions from 00 to 01 to 10 to 11 back to 00, and repeats. When E = 1 and x = 0, the circuit goes through the state transitions from 00 to 11 to 10 to 01 back to 00, and repeats. CpE 411 Advanced Logic Circuits Design 26
State Reduction Example: CpE 411 Advanced Logic Circuits Design 27
Reduced State Table CpE 411 Advanced Logic Circuits Design 28
State Assignment CpE 411 Advanced Logic Circuits Design 29
Reduced state table with binary assignment 1 CpE 411 Advanced Logic Circuits Design 30
Example Reduce the number of states in the following state table and tabulate the reduced state table. CpE 411 Advanced Logic Circuits Design 31
Example: Sequence Recognizer Design a circuit that recognizes the occurrence of a particular sequence of bits, regardless of where it occurs in a longer sequence. It has to have one input X, output Z, and direct resets on its flip-flops to initialize the state of the circuit to all zeros. The circuit is to recognize the occurrence of the sequence of bits 1101 on X by making Z equal to 1 when the previous inputs of the circuit were 110 and the current input is a 1. Otherwise, Z is 0. CpE 411 Advanced Logic Circuits Design 32
Design with D Flip-flops Design a clocked sequential circuit that operates according to the state table shown. CpE 411 Advanced Logic Circuits Design 33
Flip-flop Input and Output Equations CpE 411 Advanced Logic Circuits Design 34
Logic Diagram CpE 411 Advanced Logic Circuits Design 35
Design with Unused States CpE 411 Advanced Logic Circuits Design 36
Maps for Flip-flop Inputs CpE 411 Advanced Logic Circuits Design 37
Maps for Flip-flop Inputs and Output CpE 411 Advanced Logic Circuits Design 38
Logic Diagram with SR Flip-flops CpE 411 Advanced Logic Circuits Design 39
State Diagram CpE 411 Advanced Logic Circuits Design 40
Activity: Individual or By Pair Design the sequential circuit specified by the state diagram below using RS flip-flops. CpE 411 Advanced Logic Circuits Design 41
Design of Counters CpE 411 Advanced Logic Circuits Design 42
Maps for 3-bit binary counter CpE 411 Advanced Logic Circuits Design 43
Logic diagram of a 3-bit binary counter CpE 411 Advanced Logic Circuits Design 44
Counter w/ Nonbinary Sequence CpE 411 Advanced Logic Circuits Design 45
State diagram and logic diagram of counter CpE 411 Advanced Logic Circuits Design 46
Example: Nonbinary sequenced counter Design a counter with the following repeated binary sequence: 0, 1, 3, 5, 7. Use T flip-flops. Treat the unused states as don t-care conditions. Analyze the final circuit to ensure that it is self-correcting. If your design produces a nonself-correcting counter, you must modify the circuit to make it self-correcting. CpE 411 Advanced Logic Circuits Design 47
Activity: Individual or By Pair Design a counter with the following repeated binary sequence: 0, 1, 2, 4, 6. Use D flip-flops. If unused states should occur, make the counter reset to 0 on the next clock pulse. CpE 411 Advanced Logic Circuits Design 48
End of Unit II CpE 411 Advanced Logic Circuits Design 49