Si79DN P-Channl -V (D-S) MOSFET PRODUCT SUMMARY V DS (V) R DS(on) (Ω) I D (A) Q g (Typ.) -.5 at V GS = - V -.8.6 nc. at V GS = - 6.V -.6 PowrPAK -8 FEATURES Halogn-fr According to IEC 69-- Availabl TrnchFET Powr MOSFET Low Thrmal Rsistanc PowrPAK Packag with Small Siz and Low.7 mm Profil % UIS and R g Tstd APPLICATIONS Activ Clamp in Intrmdiat DC/DC Powr Supplis D 8 D 7 D 6 D 5 S S. mm. mm Bottom Viw S G Ordring Information: Si79DN-T-E (Lad (Pb)-fr) Si79DN-T-GE (Lad (Pb)-fr and Halogn-fr) G S D P-Channl MOSFET ABSOLUTE MAXIMUM RATINGS T A = 5 C, unlss othrwis notd Paramtr Symbol Limit Unit Drain-Sourc Voltag V DS - V Gat-Sourc Voltag V GS ± T C = 5 C -.8 T Continuous Drain Currnt (T J = 5 C) C = 7 C -. I D T A = 5 C -. a, b T A = 7 C -.95 a, b A Pulsd Drain Currnt I DM - 5 T Continuous Sourc-Drain Diod Currnt C = 5 C - 5 I S T A = 5 C -. a, b Avalanch Currnt I AS 5 L =. mh Singl-Puls Avalanch Enrgy E AS.5 mj T C = 5 C 5 T Maximum Powr Dissipation C = 7 C P D W T A = 5 C.7 a, b T A = 7 C. a, b Oprating Junction and Storag Tmpratur Rang T J, T stg - 5 to 5 C Soldring Rcommndations (Pak Tmpratur) c, d 6 Nots: a. Surfac Mountd on " x " FR board. b. t = s. c. S Soldr Profil (/ppg?757). Th PowrPAK -8 is a ladlss packag. Th nd of th lad trminal is xposd coppr (not platd) as a rsult of th singulation procss in manufacturing. A soldr fillt at th xposd coppr tip cannot b guarantd and is not rquird to nsur adquat bottom sid soldr intrconnction. d. Rwork Conditions: manual soldring with a soldring iron is not rcommndd for ladlss componnts.. T C = 5 C. Documnt Numbr: 75 S-85-Rv. B, 9-Dc-8
Si79DN THERMAL RESISTANCE RATINGS Paramtr Symbol Typical Maximum Unit Maximum Junction-to-Ambint a, b t s R thja 8 5 Maximum Junction-to-Cas (Drain) Stady Stat R thjc.9.8 C/W Nots: a. Surfac Mountd on " x " FR board. b. Maximum undr Stady Stat conditions is 8 C/W. SPECIFICATIONS T J = 5 C, unlss othrwis notd Paramtr Symbol Tst Conditions Min. Typ. Max. Unit Static Drain-Sourc Brakdown Voltag V DS V GS = V, I D = - 5 µa - V V DS Tmpratur Cofficint ΔV DS /T J - 5 I D = - 5 µa V GS(th) Tmpratur Cofficint ΔV GS(th) /T J - 5.5 mv/ C Gat-Sourc Thrshold Voltag V GS(th) V DS = V GS, I D = - 5 µa - - V Gat-Sourc Lakag I GSS V DS = V, V GS = ± V ± na V DS = - V, V GS = V - Zro Gat Voltag Drain Currnt I DSS V DS = - V, V GS = V, T J = 55 C - µa On-Stat Drain Currnt a I D(on) V DS - V, V GS = - V - A Drain-Sourc On-Stat Rsistanc a V R GS = - V, I D = - A.86.5 DS(on) V GS = - 6 V, I D = - A.88. Ω Forward Transconductanc a g fs V DS = - 5 V, I D = - A S Dynamic b Input Capacitanc C iss 666 Output Capacitanc C oss V DS = - 5 V, V GS = V, f = MHz 6 pf Rvrs Transfr Capacitanc C rss 5 V Total Gat Charg Q DS = - V, V GS = - V, I D = - A 6. 5 g.6 6 nc Gat-Sourc Charg Q gs V DS = - V, V GS = - 6 V, I D = - A.5 Gat-Drain Charg Q gd.9 Gat Rsistanc R g f = MHz 5. 8 Ω Turn-On Dlay Tim t d(on) 6 5 Ris Tim t r V DD = - V, R L = Ω 6 5 Turn-Off DlayTim t d(off) I D - A, V GEN = - 6 V, R g = Ω 5 Fall Tim t f 6 5 Turn-On Dlay Tim t d(on) 9 5 ns Ris Tim t r V DD = - V, R L = Ω 8 Turn-Off DlayTim t d(off) I D - A, V GEN = - V, R g = Ω 7 Fall Tim t f Drain-Sourc Body Diod Charactristics Continuous Sourc-Drain Diod Currnt I S T C = 5 C - 5 Puls Diod Forward Currnt a I SM - 5 A Body Diod Voltag V SD I S = - A -.8 -. V Body Diod Rvrs Rcovry Tim t rr 66 9 ns Body Diod Rvrs Rcovry Charg Q rr 5 7 nc I F = - A, di/dt = A/µs, T J = 5 C Rvrs Rcovry Fall Tim t a 8 ns Rvrs Rcovry Ris Tim t b 8 Nots: a. Puls tst; puls width µs, duty cycl %. b. Guarantd by dsign, not subjct to production tsting. Strsss byond thos listd undr Absolut Maximum Ratings may caus prmannt damag to th dvic. Ths ar strss ratings only, and functional opration of th dvic at ths or any othr conditions byond thos indicatd in th oprational sctions of th spcifications is not implid. Exposur to absolut maximum rating conditions for xtndd priods may affct dvic rliability. Documnt Numbr: 75 S-85-Rv. B, 9-Dc-8
( i t i Si79DN TYPICAL CHARACTERISTICS 5 C, unlss othrwis notd 6 n C u r r n t ( A ) I D - Dr a 5 V GS = thru 5 V V 6 8 V DS - Drain-to-Sourc Voltag (V) Output Charactristics. R D S o n ) - O n - R s s a n c (Ω)...96.88 V GS = 6 V V GS = V.8....6.8 6. I D - Drain Currnt (A) On-Rsistanc vs. Drain Currnt ) V ( g a ( t t l t i t i.5 n C u r r n t ( A ) I D - D r a..9.6. T C = 5 C T C = 5 C T C = - 55 C. 6 8 V GS - Gat-to-Sourc Voltag (V) Transfr Charactristics a n c ( p F ) C - C a p a c 8 6 C oss C iss C rss 6 8 V DS - Drain-to-Sourc Voltag (V) Capacitanc 8 I D = A V DS = 5 V.. I D = A o V c r u o S - o - a G - V G S 6 V DS = V V DS = 5 V R D S o n ) - O n-rsistanc (Normalizd).6..8 V GS = V V GS = 6 V.. 6.8..6 7. Q g - Total Gat Charg (nc) Gat Charg. - 5-5 5 5 75 5 5 T J - Junction Tmpratur ( C) On-Rsistanc vs. Junction Tmpratur Documnt Numbr: 75 S-85-Rv. B, 9-Dc-8
Si79DN TYPICAL CHARACTERISTICS 5 C, unlss othrwis notd 5 I S - Sourc Currnt (A).. T J = 5 C T J = 5 C..6.9..5 V SD - Sourc-to-Drain Voltag (V) Sourc-Drain Diod Forward Voltag R D S(on ) - Drain-to-Sourc On-Rsistanc (Ω) T A = 5 C T A = 5 C 6 8 V GS - Gat-to-Sourc Voltag (V) On-Rsistanc vs. Gat-to-Sourc Voltag.8.6. I D = 5 µa 8 V G S (t h ) ( V ).. I D = 5 ma P o w r ( W ) 6 -. -. - 5-5 5 5 75 5 5 T J - Tmpratur ( C) Thrshold Voltag... Tim (s) Singl Puls Powr, Junction-to-Ambint Limitd by R DS(on) * (A) Drain Currnt I D -... T A = 5 C Singl Puls ms ms ms s s. V DS - Drain-to-Sourc V oltag (V) * V GS > minimum V GS at which R DS (on) is spcifid DC Saf Oprating Ara, Junction-to-Ambint Documnt Numbr: 75 S-85-Rv. B, 9-Dc-8
Si79DN TYPICAL CHARACTERISTICS 5 C, unlss othrwis notd 5 I D - Drain Currnt (A ) 5 5 75 5 5 T C - Cas Tmpratur ( C) Currnt Drating*..6 ) ( W r w o P 6 ) ( W r. w o P.8 8. 5 5 75 5 5. 5 5 75 5 5 T C - Cas Tmpratur ( C) Powr, Junction-to-Cas T C - Cas Tmpratur ( C) Powr, Junction-to-Ambint * Th powr dissipation P D is basd on T J(max) = 5 C, using junction-to-cas thrmal rsistanc, and is mor usful in sttling th uppr dissipation limit for cass whr additional hatsinking is usd. It is usd to dtrmin th currnt rating, whn this rating falls blow th packag limit. Documnt Numbr: 75 S-85-Rv. B, 9-Dc-8 5
f f t i i t t i l i f f i t Si79DN TYPICAL CHARACTERISTICS 5 C, unlss othrwis notd Duty Cycl =.5 n l i s n r a n T c a d v p c m l I d E m a r N o r m a T z h.. Nots:..5 P DM. t t t. Duty Cycl, D = t. Pr Unit Bas = R thja = 65 C/W. T JM - T A = P DM Z (t) thja Singl Puls. Surfac Mountd. - - - - Squar Wav Puls Duration (s) Normalizd Thrmal Transint Impdanc, Junction-to-Ambint Duty Cycl =.5 n s n r a n T c a d v p c m l I d E m a r N o r m a T z h....5. Singl Puls. - - - - Squar Wav Puls Duration (s) Normalizd Thrmal Transint Impdanc, Junction-to-Foot maintains worldwid manufacturing capability. Products may b manufacturd at on of svral qualifid locations. Rliability data for Silicon Tchnology and Packag Rliability rprsnt a composit of all qualifid locations. For rlatd documnts such as packag/tap drawings, part marking, and rliability data, s /ppg?75. 6 Documnt Numbr: 75 S-85-Rv. B, 9-Dc-8
θ PowrPAK -8, (Singl / Dual) Packag Information W D H E E K L 8 M Z D D D D5 5 b θ θ θ L A E Backsid viw of singl pad c A H E E K L E E Nots. Inch will govrn Dimnsions xclusiv of mold gat burrs. Dimnsions xclusiv of mold flash and cutting burrs Dtail Z H D D(x) D D D K D5 b E Backsid viw of dual pad DIM. MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. MAX. A.97...8.. A. -.5. -. b....9..6 c..8..9.. D....6.. D.95.5.5.6.. D.98...78.8.88 D.8 -.89.9 -.5 D.7 typ..85 typ D5. typ..9 typ E....6.. E.95.5.5.6.. E.7.6.7.58.6.68 E.75.85.98.69.7.78 E. typ.. typ..65 BSC.6 BSC K.86 typ.. typ. K.5 - -. - - H...5..6. L...56..7. L.6....5.8 - - W.5.5.6.6.. M.5 typ..5 typ. ECN: S6-667-Rv. M, 9-Jan-7 DWG: 588 Rvison: 9-Jan-7 Documnt Numbr: 7656 For tchnical qustions, contact: pmostchsupport@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT /doc?9
AN8 PowrPAK Mounting and Thrmal Considrations Johnson Zhao MOSFETs for switching applications ar now availabl with di on rsistancs around mω and with th capability to handl 85 A. Whil ths di capabilitis rprsnt a major advanc ovr what was availabl just a fw yars ago, it is important for powr MOSFET packaging tchnology to kp pac. It should b obvious that dgradation of a high prformanc di by th packag is undsirabl. PowrPAK is a nw packag tchnology that addrsss ths issus. Th PowrPAK -8 provids ultra-low thrmal impdanc in a small packag that is idal for spac-constraind applications. In this application not, th PowrPAK -8 s construction is dscribd. Following this, mounting information is prsntd. Finally, thrmal and lctrical prformanc is discussd. THE PowrPAK PACKAGE Th PowrPAK -8 packag (Figur ) is a drivativ of PowrPAK SO-8. It utilizs th sam packaging tchnology, maximizing th di ara. Th bottom of th di attach pad is xposd to provid a dirct, low rsistanc thrmal path to th substrat th dvic is mountd on. Th PowrPAK -8 thus translats th bnfits of th PowrPAK SO-8 into a smallr packag, with th sam lvl of thrmal prformanc. (Plas rfr to application not PowrPAK SO-8 Mounting and Thrmal Considrations. ) Th PowrPAK -8 has a footprint ara comparabl to TSOP-6. It is ovr % smallr than standard TSSOP-8. Its di capacity is mor than twic th siz of th standard TSOP-6 s. It has thrmal prformanc an ordr of magnitud bttr than th SO-8, and tims bttr than TSSOP-8. Its thrmal prformanc is bttr than all currnt SMT packags in th markt. It will tak th advantag of any PC board hat sink capability. Bringing th junction tmpratur down also incrass th di fficincy by around % compard with TSSOP-8. For applications whr biggr packags ar typically rquird solly for thrmal considration, th PowrPAK -8 is a good option. Both th singl and dual PowrPAK -8 utiliz th sam pin-outs as th singl and dual PowrPAK SO-8. Th low.5 mm PowrPAK hight profil maks both vrsions an xcllnt choic for applications with spac constraints. PowrPAK SINGLE MOUNTING To tak th advantag of th singl PowrPAK -8 s thrmal prformanc s Application Not 86, Rcommndd Minimum Pad Pattrns With Outlin Drawing Accss for MOSFETs. Click on th PowrPAK -8 singl in th indx of this documnt. In this figur, th drain land pattrn is givn to mak full contact to th drain pad on th PowrPAK packag. This land pattrn can b xtndd to th lft, right, and top of th drawn pattrn. This xtnsion will srv to incras th hat dissipation by dcrasing th thrmal rsistanc from th foot of th PowrPAK to th PC board and thrfor to th ambint. Not that incrasing th drain land ara byond a crtain point will yild littl dcras in foot-to-board and foot-toambint thrmal rsistanc. Undr spcific conditions of board configuration, coppr wight, and layr stack, xprimnts hav found that adding coppr byond an ara of about. to.5 in of will yild littl improvmnt in thrmal prformanc. Figur. PowrPAK Dvics Documnt Numbr 768 -Mar-6
AN8 PowrPAK DUAL To tak th advantag of th dual PowrPAK -8 s thrmal prformanc, th minimum rcommndd land pattrn can b found in Application Not 86, Rcommndd Minimum Pad Pattrns With Outlin Drawing Accss for MOSFETs. Click on th PowrPAK -8 dual in th indx of this documnt. Th gap btwn th two drain pads is mils. This matchs th spacing of th two drain pads on th PowrPAK -8 dual packag. This land pattrn can b xtndd to th lft, right, and top of th drawn pattrn. This xtnsion will srv to incras th hat dissipation by dcrasing th thrmal rsistanc from th foot of th PowrPAK to th PC board and thrfor to th ambint. Not that incrasing th drain land ara byond a crtain point will yild littl dcras in foot-to-board and foot-toambint thrmal rsistanc. Undr spcific conditions of board configuration, coppr wight, and layr stack, xprimnts hav found that adding coppr byond an ara of about. to.5 in of will yild littl improvmnt in thrmal prformanc. REFLOW SOLDERING surfac-mount packags mt soldr rflow rliability rquirmnts. Dvics ar subjctd to soldr rflow as a prconditioning tst and ar thn rliability-tstd using tmpratur cycl, bias humidity, HAST, or prssur pot. Th soldr rflow tmpratur profil usd, and th tmpraturs and tim duration, ar shown in Figurs and. For th lad (Pb)-fr soldr profil, s http:/// doc?757. Ramp-Up Rat + 6 C /Scond Maximum Tmpratur at 55 ± 5 C Sconds Maximum Tmpratur Abov 8 C 7-8 Sconds Maximum Tmpratur + 5/- C Tim at Maximum Tmpratur - Sconds Ramp-Down Rat + 6 C/Scond Maximum Figur. Soldr Rflow Tmpratur Profil - C s (max) C/s (max) C/s (max) - 7 C 8 C C/s (max) 6 s (min) Pr-Hating Zon 5 s (max) Rflow Zon Maximum pak tmpratur at C is allowd. Figur. Soldr Rflow Tmpraturs and Tim Durations Documnt Numbr 768 -Mar-6
AN8 TABLE : EQIVALENT STEADY STATE PERFORMANCE Packag SO-8 TSSOP-8 TSOP-8 PPAK PPAK SO-8 Configuration Singl Dual Singl Dual Singl Dual Singl Dual Singl Dual Thrmal Rsiatanc R thjc (C/W) 5 8 9. 5.5.8 5.5 PowrPAK Standard SO-8 Standard TSSOP-8 TSOP-6 9.8 C 85 C 9 C 5 C. C/W C/W 5 C/W C/W PC Board at 5 C Figur. Tmpratur of Dvics on a PC Board THERMAL PERFORMANCE Introduction A basic masur of a dvic s thrmal prformanc is th junction-to-cas thrmal rsistanc, Rθjc, or th junction to- foot thrmal rsistanc, Rθjf. This paramtr is masurd for th dvic mountd to an infinit hat sink and is thrfor a charactrization of th dvic only, in othr words, indpndnt of th proprtis of th objct to which th dvic is mountd. Tabl shows a comparison of th PowrPAK -8, PowrPAK SO-8, standard TSSOP-8 and SO-8 quivalnt stady stat prformanc. By minimizing th junction-to-foot thrmal rsistanc, th MOSFET di tmpratur is vry clos to th tmpratur of th PC board. Considr four dvics mountd on a PC board with a board tmpratur of 5 C (Figur ). Suppos ach dvic is dissipating W. Using th junction-to-foot thrmal rsistanc charactristics of th PowrPAK -8 and th othr SMT packags, di tmpraturs ar dtrmind to b 9.8 C for th PowrPAK -8, 85 C for th standard SO-8, 9 C for standard TSSOP-8, and 5 C for TSOP-6. This is a.8 C ris abov th board tmpratur for th Powr- PAK -8, and ovr C for othr SMT packags. A.8 C ris has minimal ffct on r DS(ON) whras a ris of ovr C will caus an incras in r DS(ON) as high as %. Sprading Coppr Dsignrs add additional coppr, sprading coppr, to th drain pad to aid in conducting hat from a dvic. It is hlpful to hav som information about th thrmal prformanc for a givn ara of sprading coppr. Figur 5 and Figur 6 show th thrmal rsistanc of a PowrPAK -8 singl and dual dvics mountd on a -in. x -in., four-layr FR- PC boards. Th two intrnal layrs and th backsid layr ar solid coppr. Th intrnal layrs wr chosn as solid coppr to modl th larg powr and ground plans common in many applications. Th top layr was cut back to a smallr ara and at ach stp junction-to-ambint thrmal rsistanc masurmnts wr takn. Th rsults indicat that an ara abov. to. squar inchs of sprading coppr givs no additional thrmal prformanc improvmnt. A subsqunt xprimnt was run whr th coppr on th back-sid was rducd, first to 5 % in strips to mimic circuit tracs, and thn totally rmovd. No significant ffct was obsrvd. Documnt Numbr 768 -Mar-6
AN8 5 95 Sprading Coppr (sq. in.) Sprading Coppr (sq. in.) 85 R t hj A ( C/W) 75 65 % 55 5 % % 5..5.5.75..5.5.75. Figur 5. Sprading Coppr - Si7DN R thj A ( C/W) 9 8 7 6 5 5 % % %..5.5.75..5.5.75. Figur 6. Sprading Coppr - Junction-to-Ambint Prformanc CONCLUSIONS As a drivativ of th PowrPAK SO-8, th PowrPAK -8 uss th sam packaging tchnology and has bn shown to hav th sam lvl of thrmal prformanc whil having a footprint that is mor than % smallr than th standard TSSOP-8. Rcommndd PowrPAK -8 land pattrns ar providd to aid in PC board layout for dsigns using this nw packag. Th PowrPAK -8 combins small siz with attractiv thrmal charactristics. By minimizing th thrmal ris abov th board tmpratur, PowrPAK simplifis thrmal dsign considrations, allows th dvic to run coolr, kps r DS(ON) low, and prmits th dvic to handl mor currnt than a sam- or largr-siz MOS- FET di in th standard TSSOP-8 or SO-8 packags. Documnt Numbr 768 -Mar-6
Application Not 86 RECOMMENDED MINIMUM PADS FOR PowrPAK -8 Singl.5 (.86).9 (.99).68 (.75). (.55).6 (.5).88 (.5).9 (.9).6 (.66).5 (.65). (.76) Rcommndd Minimum Pads Dimnsions in Inchs/(mm) Rturn to Indx Rturn to Indx APPLICATION NOTE Documnt Numbr: 7597 Rvision: -Jan-8 7
Lgal Disclaimr Notic Vishay Disclaimr ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intrtchnology, Inc., its affiliats, agnts, and mploys, and all prsons acting on its or thir bhalf (collctivly, Vishay ), disclaim any and all liability for any rrors, inaccuracis or incompltnss containd in any datasht or in any othr disclosur rlating to any product. Vishay maks no warranty, rprsntation or guarant rgarding th suitability of th products for any particular purpos or th continuing production of any product. To th maximum xtnt prmittd by applicabl law, Vishay disclaims (i) any and all liability arising out of th application or us of any product, (ii) any and all liability, including without limitation spcial, consquntial or incidntal damags, and (iii) any and all implid warrantis, including warrantis of fitnss for particular purpos, non-infringmnt and mrchantability. Statmnts rgarding th suitability of products for crtain typs of applications ar basd on Vishay s knowldg of typical rquirmnts that ar oftn placd on Vishay products in gnric applications. Such statmnts ar not binding statmnts about th suitability of products for a particular application. It is th customr s rsponsibility to validat that a particular product with th proprtis dscribd in th product spcification is suitabl for us in a particular application. Paramtrs providd in datashts and / or spcifications may vary in diffrnt applications and prformanc may vary ovr tim. All oprating paramtrs, including typical paramtrs, must b validatd for ach customr application by th customr s tchnical xprts. Product spcifications do not xpand or othrwis modify Vishay s trms and conditions of purchas, including but not limitd to th warranty xprssd thrin. Excpt as xprssly indicatd in writing, Vishay products ar not dsignd for us in mdical, lif-saving, or lif-sustaining applications or for any othr application in which th failur of th Vishay product could rsult in prsonal injury or dath. Customrs using or slling Vishay products not xprssly indicatd for us in such applications do so at thir own risk. Plas contact authorizd Vishay prsonnl to obtain writtn trms and conditions rgarding products dsignd for such applications. No licns, xprss or implid, by stoppl or othrwis, to any intllctual proprty rights is grantd by this documnt or by any conduct of Vishay. Product nams and markings notd hrin may b tradmarks of thir rspctiv ownrs. 7 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Rvision: 8-Fb-7 Documnt Numbr: 9