Foveon FX17-78-F13D-07 14.1 Mp, 7.8 µm Pixel Size CIS from Sigma DP1 Compact Digital Camera 0.18 µm Dongbu Process Imager Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
Imager Process Review Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2008 Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR-0804-804 12560JMRK Revision 1.0 Published: June 16, 2008 Revision 2.0 Published: July 15, 2008
Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Camera Teardown and Image Sensor Package and Die 2.2 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Dielectrics 3.3 Metallization 3.4 Vias and Contacts 3.5 Transistors and Poly 3.6 Isolation 3.7 Wells and Substrate 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis 4.4 Color Filters and Microlenses 5 Critical Dimensions 5.1 Critical Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks
Overview 1-1 1 Overview 1.1 List of Figures 2 Device Overview 2.1.1 Sigma DP1 Digital Camera Front View 2.1.2 Sigma DP1 Digital Camera Back View 2.1.3 Sigma DP1 Digital Camera Top View 2.1.4 Sigma DP1 Digital Camera Bottom View 2.1.5 Sigma DP1 Main Board and LCD Monitor 2.1.6 Sigma DP1 Main Board Front View 2.1.7 Sigma DP1 Main Board Back View 2.1.8 Sigma DP1 Camera Teardown Showing CIS on PCB 2.1.9 Sigma DP1 CIS Module on PCB Top 2.1.10 Sigma DP1 CIS Module on PCB Bottom 2.1.11 Sigma DP1 CIS Package Bottom View 2.1.12 CIS on PCB X-Ray 2.1.13 CIS Die Photograph Color Filter and Microlenses Intact 2.1.14 Photograph Color Filter and Microlenses Removed 2.1.15 CIS Die Markings No. 1 2.1.16 CIS Die Markings No. 2 2.1.17 CIS Die Markings No. 3 & 4 Mask Level Mark 1 2.1.18 CIS Die Markings No. 5 Mask Mark 2 2.1.19 CIS Die Markings No. 6 Mask Mark 3 2.1.20 CIS Die Markings No. 7 Test Pad Mark 1 2.1.21 CIS Die Markings No. 8 Test Pad Mark 2 2.1.22 CIS Die Markings No. 9 Test Pad Mark 3 2.1.23 CIS Die Markings No. 10 Test Pad Mark 4 2.1.24 Foveon13VD Metal 2 Die Photograph 2.1.25 Section Map 2.2.1 Die Corner A 2.2.2 Die Corner B 2.2.3 Die Corner C 2.2.4 Die Corner D 2.2.5 Active Pixel Array Top Left Corner 2.2.6 Active Pixel Array Top Right Corner 2.2.7 Array Bottom Right Corner 2.2.8 Active Pixel Array Bottom Left Corner 2.2.9 Minimum Pitch Bond Pads 2.2.10 Detail of Bond Pad
Overview 1-2 3 Process Analysis 3.1.1 General View of the Foveon13VD Periphery 3.1.2 General View of the Foveon13VD Pixel Array 3.1.3 Die Edge Overview 3.1.4 Die Edge Detailed View 3.1.5 Die Seal 3.1.6 Ball Bond and Bond Pad 3.1.7 Left Edge of Bond Pad 3.1.8 Right Edge of Bond Pad 3.2.1 Passivation Periphery 3.2.2 IMD 3 3.2.3 IMD 2 3.2.4 IMD 1 3.2.5 PMD Periphery 3.3.1 Minimum Pitch Metal 4 3.3.2 Minimum Pitch Metal 3 3.3.3 Minimum Pitch Metal 2 3.3.4 Metal 3 Thickness TEM 3.3.5 Metal 3 Cap Layers in Detail 3.3.6 Metal 2 Thickness 3.3.7 Minimum Pitch Metal 1 3.3.8 Metal 1 Thickness 3.3.9 Metal 1 Cap Layers in Detail 3.4.1 Minimum Pitch Via 3s 3.4.2 Minimum Pitch Via 2s through Via 1s 3.4.3 Minimum Pitch Contacts to N + Diffusion 3.4.4 Contacts to Diffusion TEM 3.4.5 Contact to Poly TEM 3.5.1 Peripheral MOS Transistor Glass Etch 3.5.2 Minimum Observed Gate Length Peripheral NMOS Transistor 3.5.3 Minimum Observed Gate Length Peripheral PMOS Transistor 3.5.4 Minimum Gate Length Pixel NMOS Transistor 3.5.5 Minimum Width Poly Line 3.6.1 Minimum Width STI TEM 3.6.2 Poly Over STI 3.7.1 Pixel Triple-Cathode Structure 3.7.2 SCM Profile of Triple-Cathode Photodiode Pixel 3.7.3 SRP of Pixel Array 3.7.4 SIMS Profile of Pixel Diffusions 3.7.5 Deep Buried Peripheral N-Well (N-Well 3) 3.7.6 Shallow Peripheral N-Well 3.7.7 SRP of Peripheral N-Well 3 and P-Well 3.7.8 SRP of Peripheral P-Well and P-Epi 3.7.9 Pixel To Peripheral Wells Transition SCM 3.7.10 Peripheral Wells SCM
Overview 1-3 4 Pixel Analysis 4.1.1 13T Pixel Schematic 4.2.1 Pixel Array Corner Optical 4.2.2 Microlenses Plan View (SEM) 4.2.3 Microlenses Tilt View (SEM) 4.2.4 Pixel Array at Metal 3 4.2.5 Pixel Array at Metal 2 4.2.6 Pixel Array at Metal 1 4.2.7 Pixel Array at Poly Overview 4.2.8 Pixel Array at Poly Detailed View 4.2.9 Pixel Array at Diffusion 4.2.10 Pixel Array at Diffusion T4 and T5 Transistor Width 4.2.11 Pixel Array at Diffusion T9 and T10 Transistor Width 4.2.12 Pixel Array at Diffusion T12 and T13 Transistor Width 4.2.13 SCM of Blue Photocathode 4.2.14 SCM of Green Photocathode 4.2.15 SCM of Red Photocathode 4.3.1 Pixel at Poly Showing Cross-Sectional Planes Plan View 4.3.2 Transistor T1 and Pixel Overview (A) 4.3.3 Detail of Transistor T1 (A) 4.3.4 SCM of P-Pinning Layer and Buried N-Photocathodes (A) 4.3.5 Pixel Transistors T2, T3, T4, T5, T6, and T7 Overview (B) 4.3.6 Detail of T2 and T3 Transistors (B) 4.3.7 T3 (or T2) Transistor Width (C) 4.3.8 Detail of T4 and T5 Transistors TEM (B) 4.3.9 Detail of T6 and T7 Transistors and FD TEM (B) 4.3.10 Transfer Transistor T6 Gate TEM (B) 4.3.11 Reset Transistor T7 Gate TEM (B) 4.3.12 Transfer Gate (T6), Gate Oxide Thickness TEM (A) 4.3.13 Silicon Nitride PMD 1 (Used as AR Over Pixel) Layer (A) 4.3.14 Pixel Transistor Gate Width TEM (D) 4.3.15 Pixel Transistors T8, T9, T10, T11, T12, and T13 Overview (E) 4.3.16 Detail of Transfer T8 and Reset T9 Transistors (E) 4.3.17 Detail of Transfer T11 and Reset T10 Transistors (E) 4.3.18 Detail of Source Follower T12 and Row Select T13 Transistors (E) 4.4.1 General Structure of Pixel and Pixels Near Array Center Angle of Acceptance (F) 4.4.2 Microlens Radius of Curvature (F) 4.4.3 Pixel at Bottom Array Edge (F) Parallel to Column Out 4.4.4 Pixel at Right Array Edge and Active Pixels to Dark Pixels Transition (G)
Overview 1-4 4.4.5 Dark Pixels to Periphery Transition (H) 4.4.6 Microlens Array Edge Parallel to Column Out 4.4.7 Edge of Organic Spacer Parallel to Column Out 4.4.8 Edge of Green Color Filter Parallel to Column Out 4.4.9 Organic Lens TEM (Parallel to Row Select) 4.4.10 Green Color Filter TEM (Parallel to Row Select) 1.2 List of Tables 1 Overview 1.4.1 Device Identification 1.5.1 Foveon13VD CIS Device Summary 1.6.1 Foveon13VD CIS Process Summary 2 Device Overview 2.1.1 Sigma DP1 Camera Identification 2.1.2 Functional Block Sizes 2.2.1 CIS Die and Bond Pad Dimensions 3 Process Analysis 3.2.1 Dielectric Thicknesses 3.3.1 Metallization Vertical Dimensions 3.3.2 Minimum Metallization Horizontal Dimensions 3.4.1 Via and Contact Dimensions 3.5.1 Transistor and Polycide Horizontal Dimensions 3.5.2 Transistor and Polycide Vertical Dimensions 3.6.1 STI Observed Critical Dimensions 3.7.1 Well Depths 4 Pixel Analysis 4.1.1 Pixel Array Horizontal Dimensions 4.1.2 Pixel Array Vertical Dimensions 4.3.1 Pixel Transistor Dimensions 5 Critical Dimensions 5.1.1 CIS Die and Bond Pad Dimensions 5.1.2 Dielectric Thicknesses 5.1.3 Metallization Vertical Dimensions 5.1.4 Minimum Metallization Horizontal Dimensions 5.1.5 Via and Contact Dimensions 5.1.6 Transistor and Polycide Horizontal Dimensions 5.1.7 Transistor and Polycide Vertical Dimensions 5.1.8 STI Observed Critical Dimensions 5.1.9 Well Depths 5.1.10 Pixel Array Horizontal Dimensions 5.1.11 Pixel Array Vertical Dimensions 5.1.12 Pixel Transistor Dimensions
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