Samsung S5K3L1YX03 12.1 Mp, 1/3.2 Inch Optical Format 1.12 µm Pixel Pitch Back Illuminated (BSI) CMOS Image Sensor Circuit Analysis of Pixel Array, Row Drivers, Column Readouts, Ramp Generator, DPLL, MIPI Interface, and Other Analog Circuits 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com
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Overview Introduction Brief Design Overview Component Descriptions Device Summary Figures To view, please click on the appropriate bookmark in the panel on the left. 0.1.1 Package Photograph 0.1.2 Die Markings 0.2.1 Die Photograph CMOS Image Sensor with Microlens and Filter Layer Intact 0.2.2 Die Photograph Top Metal Layer 0.2.3 Die Photograph Polysilicon 0.2.4 Die Architecture Schematics 1.0.0 Top Level Diagram 2.0.0 Pixel Array 2.1.0 Pixel Cell 3.0.0 Row Drivers 3.1.0 Row Driver 1 3.1.1 Row Select Driver A 3.1.2 Output Driver 1 3.1.3 Register Cell 3.1.4 Reset Driver 2 3.1.5 Output Drive 2 3.1.6 Reset Driver 1A 3.1.7 Transfer 2 Driver 3.1.7.1 Driver Cell 1 3.1.8 Transfer 1 Driver 3.1.9 Row Logic 3 3.1.10 Row Logic 2 3.1.11 Row Logic 1 3.2.0 Row Driver 2 3.2.1 Row Select Driver B 3.2.2 Reset Driver 1B
4.0.0 Column Readouts 4.1.0 Column Logic Top 4.1.1 Column Logic 1 4.2.0 Column Readout 3 4.2.1 Comparator 1 4.2.2 Databus Driver 3 4.2.3 Output Pull-Down Cell 4.2.4 Driver 4.2.5 Counter 4.2.6 Column Selection 4.3.0 Column Readout 4 4.3.1 Data Bus Driver 4 4.4.0 Column Readout 1 4.4.1 Data Bus Driver 1 4.5.0 Column Readout 2 4.5.1 Data Bus Driver 2 5.0.0 Ramp Generator and Voltage Generators 5.1.0 UNUSED_21 5.1.1 S_DIFBUF_60L4_20L4S1 5.2.0 Current Bias 5.3.0 Bandgap Reference 5.4.0 Voltage Doublers Pumps 5.4.1 Programmable IBias 1 5.4.2 S_INV_26L4_10L4 5.4.3 S_INV_26L4_10L4S1 5.4.4 Current-Starved Oscillator 2 5.4.5 S_BUF_26L4_10L4D6 5.4.6 Voltage Doubler Pump 1 5.4.7 Current-Starved Oscillator 1 5.4.8 S_BUF2F_26L4_10L4D16 5.4.9 Phase Generator 5.4.10 Voltage Doubler Pump 3 5.4.11 VPUMP Clock 5.4.12 Voltage Doubler Pump 4 5.4.13 Voltage Doubler Pump 2 5.4.14 Voltage Pump Control 1 5.4.15 COMP_9 5.4.16 VREF Gen
5.4.17 Programmable IBias 2 5.5.0 Voltage Level Shifter 5.6.0 Voltage Select 5.6.1 S_TRIGATE_100L4_100L4D20 5.7.0 Control Logic 1 5.8.0 Ramp Generator 5.8.1 Control Logics 5.8.2 UNUSED_3 5.8.3 UNUSED_4 5.8.4 UNUSED_6 5.8.5 UNUSED_7 5.8.6 NAND Gates 5.8.7 Buffers 5.8.8 Buffer Circuit 5.8.9 Decoder 5.8.10 Control Circuit 5.8.11 Clock Buffers 5.8.12 NANDs 5.8.13 NOR Gates 5.8.14 Shift Registers 5.8.15 Registers 5.8.16 Registers 5.8.17 Buffers 5.8.18 Clock Control Circuits 5.8.19 Decoder 1 5.8.20 Registers 1 5.8.21 Registers 2 5.8.22 UNUSED_5 5.8.23 MUXs 5.8.24 Decoder 2 5.8.25 AND 5.8.26 NAND 5.8.27 Buffers 5.8.28 NOR 5.8.29 Clock Circuit 5.8.30 Clock Buffers 5.8.31 UNUSED_17 5.8.32 Programmable Current Sinks 5.8.33 Programmable Current Sink 3 5.8.34 Programmable Current Sink 4
5.8.35 Programmable Current Sink 5 5.8.36 Programmable Current Sink 1 5.8.37 Programmable Current Sink 2 5.8.38 Current Sink Decoder 2 5.8.39 Current Sink Buffers 5.8.40 Programmable Current Sink 6 5.8.41 Current Sink Decoder 1 5.8.42 Voltage Reference Generator 5.8.43 Buffers 5.8.44 Amplifier 1 5.8.45 Amplifier 2 5.8.46 Voltage Bias 5.8.47 Voltage Gen 5.8.48 PCASC_X85 5.8.49 PCASC_X42 5.8.50 PCASC_X22 5.8.51 Full Adder 5.8.52 Adder Cell 1 5.8.53 Ramp Counter 5.8.54 S_DFCF_6_4 5.8.55 Control Circuit 5.8.56 ORs 5.8.57 UNUSED_15 5.8.58 Resistor Pull-Down Cell 5.8.59 Programmable RES Pull-Down 1 5.8.60 Programmable RES Pull-Down 2 5.8.61 Reference Gen 5.8.62 Ramp Generator Control 1 5.8.63 Ramp Control 1 5.8.64 Inverter 5.8.65 PCASC_X5 5.8.66 Full Adder 5.8.67 Inverters 5.8.68 Ramp Pulse Generator 5.8.69 Registers 5.8.70 Counter 5.9.0 Pixel Voltage Generator 5.9.1 Voltage Divider 2 5.9.2 Cascode Amplifier 5.9.3 Voltage Bias Generator
5.9.4 Level Shift 2 5.9.5 Level Shift 1 5.10.0 Voltage Generators 5.10.1 Voltage Divider 5.10.2 Amplifier 4 5.10.3 Voltage Reference 2 5.10.4 Amplifier 2 5.10.5 Amplifier 1 5.10.6 Voltage Reference 3 5.10.7 Amplifier 3 5.10.8 S_NOR2_25L4_10L4 5.10.9 S_INV_25L4_10L4 5.10.10 Voltage Reference 1 5.10.11 Amplifier 6 5.10.12 Control Logic 5.10.13 Amplifier 5 5.11.0 Voltage Regulator 5.11.1 UNUSED_8 5.11.2 UNUSED_13 5.11.3 VREG Current Control 5.11.4 Voltage Regulator Control 5.11.5 UNUSED_11 5.11.6 S_DIFBUF_18L4_7L4 5.11.7 VDDD_DET_1 5.11.8 Voltage Detector 5.11.9 STARTUP_COMP 5.11.10 S_INV_40L5_20L5 5.11.11 S_INV_40L10_20L10 5.12.0 Programmable Current Bias 5.12.1 Voltage Reference 5.12.2 Decoder 5.12.3 PMOS_X8 5.12.4 PCASC_X20 5.12.5 PCASC_X4_2 5.12.6 PCASC_X2_2 5.12.7 PCASC_X5_2 5.12.8 PCASC_X10_2 5.12.9 PCASC_X8_2 5.12.10 PCASC_X16_2 5.12.11 Inverters
5.12.12 Control Logic 5.12.13 Comparators 5.12.14 AMP_27 5.13.0 Voltage Generator 5.13.1 Amplifier 1 5.13.2 Amplifier 2 5.13.3 Voltage Divider 5.14.0 Voltage Selector 5.14.1 Cascode Amplifier 5.14.2 Level Shifters 6.0.0 DPLL and Pulse Generators 6.1.0 DPLL 6.1.1 Amplifier 6.1.2 Current Bias 2 6.1.3 Buffers 6.1.4 Bandgap 6.1.5 Differential Amplifier 3 6.1.6 Differential Amplifier 1 6.1.7 Differential Amplifier 2 6.1.8 S_DIFBUFF_33L5_10L5 6.1.9 Phase Frequency Detector 1 6.1.10 Counter 2 6.1.11 Logic Control 6.1.12 Logic A 6.1.13 UNUSED_12 6.1.14 Clock Buffers 2 6.1.15 Divider 6.1.16 Counter 1 6.1.17 Clock Buffers 6.1.18 Control Logic 2 6.1.19 PFD2 and Counter 6.1.20 Phase Frequency Detector 2 6.1.21 Latch 1 6.1.22 Phase Frequency Selector 6.1.23 Select Control 6.1.24 VCO 6.1.25 UNUSED_9 6.1.26 Current Bias Generator 6.1.27 COMP_6
6.1.28 VCO Cell 6.1.29 Low Pass Filer 6.1.30 Buffer 1 6.1.31 Charge Pump 6.1.32 Charge Pump Amp 6.2.0 Clock Pulse-Phase-Frequency Generator 6.2.1 Divider A 6.2.2 Pulse Generator 2 6.2.3 Decoder 1 6.2.4 Clock Divider 5 6.2.5 Clock Divider 6 6.2.6 Clock Divider 7 6.2.7 Clock Divider 8 6.2.8 Pulse Generator 3 6.2.9 Clock Divider 1 6.2.10 Clock Divider 9 6.2.11 Clock Divider 10 6.2.12 S_DFTF_12X2_8 6.2.13 Decoder 2 6.2.14 Pulse Generator 4 6.2.15 Clock Divider 4 6.2.16 Clock Divider 11 6.2.17 Decoder 3 6.2.18 Clock Pulse 1 6.2.19 CLK Control 1 6.2.20 Clock Divider 2 6.2.21 Clock Divider 3 6.2.22 Pulse Generator 6 6.2.23 CLK Pulse 2 6.2.24 Clock Divider 13 6.2.25 Pulse Generator 5 6.2.26 Clock Divider 12 6.2.27 Decoder 4 6.2.28 Pulse Generator 1 7.0.0 MIPI Interface 7.1.0 Buffer Amplifier 7.1.1 Unused 5 7.2.0 TRX TOP Control 1 7.2.1 TRX Bias
7.2.2 S_TRIGATE_25X4_15L2X2 7.2.3 S_TRIGATE_25X4_15L2X2S1 7.2.4 S_TRIGATE_40_40D4 7.2.5 S_TRIGATE_40_40D2 7.2.6 Unused 3 7.2.7 VREF Generators 7.2.8 Bias Controls 1 7.2.9 Bias Controls 2 7.2.10 TRX TOP CTRL 1 7.3.0 TX 1 7.3.1 TX Amplifier 1 7.3.2 TX Driver 3 7.3.3 TX Logic 4 7.3.4 TX Current Bias Generator 7.3.5 TX Counter 1 7.3.6 Registers 2 7.3.7 Registers 1 7.3.8 TX Logic 3 7.3.9 TX Logic 1 7.3.10 TX Driver 1 7.3.11 S_TRIGATE_60L1X4_60L1X2 7.3.12 S_TRIGATE_50L4_50L4D2 7.3.13 S_TRIGATE_50X4_50X2 7.3.14 S_TRIGATE_50L2_50L2D2 7.3.15 Driver Control 1 7.3.16 Load Resistor 7.3.17 TX Driver 2 7.3.18 TX Logic 2 7.4.0 TX2 7.5.0 RX Select Circuit 7.5.1 Decoder 7.6.0 TX 3 7.6.1 Registers 3 7.6.2 Registers 2 7.6.3 Registers 4 7.6.4 Registers 7 7.6.5 TX Logic 3 7.6.6 Registers 5 7.6.7 TX Counter 2 7.6.8 Registers 6
7.6.9 TX Logic 5 7.6.10 TX Logic 4 7.6.11 TX Logic 6 7.7.0 RX 1 7.7.1 RX Data Selector 1 7.7.2 Comparator 1 7.7.3 BUF_DLY4_1 7.7.4 INV_DLY5 7.7.5 BUF_DLY8_1 7.7.6 RX Data Selector 2 7.7.7 COMP_2 7.7.8 RX Logic 1 7.7.9 INV_DLY13 7.7.10 ESD1 7.7.11 Register 3 7.7.12 Registers 6 7.7.13 Register 2 7.7.14 Decoder 1 7.7.15 Registers 7 7.7.16 Registers 5 7.7.17 RX Control Logic 3 7.7.18 RX Data Logic Path 7.7.19 RX Control Logic 1 7.7.20 Register 1 7.7.21 Registers 8 7.7.22 RX Control Logic 4 7.7.23 RX Control Logic 2 7.7.24 Registers 4 7.8.0 RX 2 7.8.1 Registers 9 7.9.0 TRX TOP Control 2 7.9.1 Logic Control C 7.9.2 Current Bias C 7.9.3 Buffer C 7.10.0 RX 3 7.10.1 Delay Logic 7.10.2 VBIAS Signal Path 7.10.3 Programmable Resistors 7.10.4 RX Signal Path 1 7.10.5 Logic 1
7.10.6 Counter 1 7.10.7 Signal Path 7.10.8 Comparator 2 7.10.9 S_INV_15X2_10 7.10.10 Registers 12 7.10.11 Unused 7.10.12 Registers 10 7.10.13 RX Control 11 7.10.14 Registers 11 7.10.15 RX Control 6 7.10.16 RX Control 7 7.10.17 Logic A 7.10.18 Logic B 7.10.19 RX Control 8 7.10.20 RX Control 12 7.10.21 RX Control 5 7.10.22 RX Control 9 7.10.23 RX Comparator 7.10.24 Differential Amp 1 7.10.25 Differential Amp 3 7.10.26 Differential Amp 2 7.10.27 Differential Amp 4 7.10.28 Amplifier Bias 7.10.29 S_TRIGATE_30L3_30L3D6 7.10.30 S_TRIGATE_25_25D2 7.10.31 RX Control 10 7.10.32 VREF 7.10.33 S_TRIGATE_5_5D2 7.11.0 RX 4 7.11.1 Signal Path 3 7.11.2 Signal Path 2 7.11.3 Comparator 2 7.11.4 Programmable Current Bias 7.11.5 COMP_4 7.11.6 RX Signal Path 7.11.7 RX Comparators 2 7.11.8 Differential Amp 3 7.11.9 Differential Amp 1 7.11.10 Differential Amp 2 7.11.11 Amplifier Bias
7.11.12 RX Signal Path 3 7.11.12 UNUSED_19 7.11.13 Signal Path 4 7.11.14 Programmable Resistors 7.11.15 RX Control 13 7.11.16 UNUSED_18 7.11.17 Delay Cell 2 7.12.0 TX 4 7.12.1 COMP_3S1 7.12.2 TX Logic 9 7.12.3 TX COUNTER 3 7.12.4 TX Logic 7 7.12.5 Decoder A 7.12.6 UNUSED_14 7.12.7 Registers 9 7.12.8 Registers 8 7.12.9 REGS_2BX2_1 7.12.10 TX Logic 8 7.13.0 TRX TOP Control and Bias 7.13.1 RX Voltage Bias 7.13.2 S_TRIGATE_25X4_15L2X2S2 7.13.3 S_TRIGATE_25X4_15L2X2S3 7.13.4 Unused 2 7.13.5 Bias Control 7.14.0 Bandgap 7.14.1 Bandgap Amplifier 7.15.0 AMP_2S1 7.16.0 RX TOP Current Bias 8.0.0 Voltage Detector Cell Library 9.0.0 Pads About Chipworks
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