Fault Tolerant Control of DC-Link Voltage Sensor for Three-Phase AC/DC/AC PWM Converters

Journal of Powr Elctronics, Vol. 4, No. 4, pp. 695-73, July 24 695 JPE 4-4-9 http://dx.doi.org/.63/jpe.24.4.4.695 ISSN(Print): 598-292 / ISSN(Onlin): 293-478 Fault Tolrant Control of DC-Link Voltag Snsor for Thr-Phas AC/DC/AC PWM Conrtrs Soo-Chol Kim, Thanh Hai Nguyn, Dong-Choon L, Kyo-Bum L, and Jang-Mok Kim Dawoo Shipbuilding and Marin Enginring Co., Ltd., Soul, Kora Dpartmnt of Elctrical Enginring, Yungnam Unirsity, Gyongsan, Kora Dpartmnt of Elctrical and Computr Enginring, Ajou Unirsity, Suwon, Kora Dpartmnt of Elctrical Enginring, Pusan National Unirsity, Pusan, Kora Abstract In this papr, a fault dtction schm for DC-link oltag snsor and its fault tolrant control stratgy for thr-phas AC/DC/AC PWM conrtrs ar proposd, whr th Lunbrgr obsrr is applid to stimat th DC-link oltag. Th Lunbrgr obsrr is basd on a conrtr modl, which is drid from th oltag quations of a grid-sid conrtr and th powr balanc on a DC link. A fault of th oltag snsor is dtctd by comparing th masurd alu of th DC-link oltag with th stimatd on. Whn a snsor fault is dtctd, a fault tolrant control stratgy is prformd, whr th stimatd DC-link oltag is usd for th fdback control. Th stimation rror from th obsrr is about.5 V, which is sufficintly accurat for fdback control. In addition, it is shown that th obsrr prformanc is robust to paramtr ariations of th conrtr. Th alidity of th proposd mthod has bn rifid by simulation and xprimntal rsults. Ky words: DC-link oltag, Estimation, Fault tolrant control, Lunbrgr obsrr, PWM conrtr I. INTRODUCTION AC/DC/AC PWM conrtrs ar widly usd in arious industrial aras such as lctric machin dris, UPSs (unintrruptibl powr supply), UPQCs (unifid powr quality conditionr) and grid-connctd rnwabl nrgy systms []- [3]. A rsarch sury has rportd that th failur rats of ths conrtr ar 3%, 26%, 2% and 3% du to thir capacitors, printd circuit boards, smiconductors, and soldring, rspctily [4], [5]. Thrfor, th rliability and prformanc of PWM conrtrs has bn paid a grat dal of attntion. Rcntly, fault dtction and tolrant control tchniqus for powr conrtrs ha attractd a lot of intrst du to thir highr rliability and lowr maintnanc. Thrfor, som studis on th fault dtction and tolrant control of th PWM conrtrs, which ar mainly on th opnor short-circuits of switching dics and DC-link capacitors, ha bn introducd [6]-[2]. Howr, th fault dtction of Manuscript rcid Jan. 5, 24; accptd Apr. 7, 24 Rcommndd for publication by Associat Editor S-Kyo Chung. Corrsponding Author: l@yu.ac.kr Tl: +82-53-8-2582, Fax: +82-53-8-4767, Yungnam Uni. Dawoo Shipbuilding and Marin Enginring Co., Ltd., Kora Dpt. of Elctrical Eng., Yungnam Unirsity, Kora Dpt. of Elctrical and Computr Eng., Ajou Unirsity, Kora Dpt. of Elctrical Eng., Pusan National Unirsity, Kora 24 KIPE th snsor and its tolrant control schm ha not bn studid ry much. A study on DC-link oltag snsorlss control has bn rportd [3], which focuss on cost rduction rathr than prparation for failurs. Thrfor, rsarch on th fault diagnosis and tolrant control of DC oltag snsor is ndd. Th control of a PWM-VSC (oltag-sourc conrtr) rquirs information on th DC-link oltag, and th grid oltags and currnts, whr th control prformanc dpnds a grat dal on accurat masurmnts by oltag and currnt snsors. In th cas of a malfunction of a DC oltag snsor, th DC-link oltag cannot b controlld at a dsird alu, which may damag or trip th systm. In addition, if th masurd alu of th DC-link oltag contains a rippl componnt, th input currnt of th PWM conrtr is also distortd by th action of th DC-link oltag controllr [4]. Rcntly, sral studis ha bn prsntd to stimat DC-link oltag. At first, DC-link oltag monitoring was studid for grid-connctd wind turbin conrtrs [4], whr a combination of th PI (proportional-intgral) control and th prdicti algorithm is mployd to compnsat for masurmnt rrors of th DC-link oltag. This mthod rquirs a high sampling frquncy (qual to four tims th switching frquncy) with a complicatd timing synchronization for th sampling and prdiction of currnts and oltags. Anothr mthod has bn introducd, which

696 Journal of Powr Elctronics, Vol. 4, No. 4, July 24 as bs cs i a i b i c Rs a b c p in, c + C p out, c2 p cap dib b = Rsib + + b dt (2) dic c = Rsic + + c dt (3) d q - pˆout Fig.. Thr-phas AC/DC/AC PWM conrtr. stimats th DC-link and sourc oltags simultanously using a switching tabl and a driati of th boost inductor currnt [5]. In this schm, th stimation prformanc is snsiti to masurmnt nois. Furthrmor, if th switching tim is not chosn appropriatly for th initial stimation at start-up, th wrong stimation may caus an orcurrnt. In anothr mthod, th DC-link oltag and grid currnts ar stimatd by a sliding mod obsrr [6]. A disadantag of this mthod is that an undsirabl chattring phnomnon is initabl on th stimation ariabls. In addition, xprimntal rification of th actual systm has not bn proidd. In this papr, fault dtction for th DC-link oltag snsor and its tolrant control schm ar proposd for thr-phas AC/DC/AC PWM conrtrs, whr th Lunbrgr obsrr is mployd to stimat th DC-link oltag. For this stimation schm, th PWM conrtr is modld as a nonlinar systm which rsults from including th powr balanc btwn th input and th output. At first, th nonlinarity of th PWM conrtr modl is linarizd by using a small signal analysis [7]-[9]. Thn, th Lunbrgr obsrr is applid to stimat th DC-link oltag, sinc it is known to gi good prformanc with a fast rsponss and high rliability. Th stimation rror is lss than 3% in th transint stats of th load chang or ariations of th systm paramtrs. Th fault condition of th DC oltag snsor is discrnd by comparing th masurd alu with th stimatd on. Thn, th DC-link oltag is still controlld wll during th snsor fault by fding th stimatd on back. Th alidity of th proposd stimation and control mthod is rifid by simulation and xprimntal rsults. II. NONLINEAR MODELING OF AC/DC PWM CONVERTERS Fig. shows th thr-phas AC/DC/AC PWM conrtrs for th AC motor dris. A. Voltag Equations Th oltag quations in a thr-phas AC/DC PWM conrtr ar xprssd as: dia a = Rsia + + a () dt whr a, b and c ar th input phas oltags, i a, i b and i c ar th input currnts, and a, b and c ar th input oltags of th conrtr. In addition, R s and L s ar th rsistancs and inductancs in th AC sid, rspctily. Th sourc oltag can b rwrittn in th d-q synchronous rfrnc fram as []: d s d s d sw q d = R i + L pi - L i + (4) q s q s q sw d q = R i + L pi + L i + (5) whr th suprscript rprsnts a quantity in th synchronous rfrnc fram and p dnots a diffrntial oprator. In (4) and (5), th conrtr input oltags, dq, can b xprssd as: d dd q = (6) q whr is th DC-link oltag, and = d (7) d and q ar th duty ratios transformd into th d-q fram from th a-b-c fram [7], [8]. B. Powr Balanc in th DC-Link Th powr flow at th DC-link sid of th back-to-back conrtr is shown in Fig., and is xprssd as: pcap = pin - pout (8) whr p cap is th capacitor powr, p in is th input powr flowing into th DC-link from th AC sourc with th conrtr loss nglctd, and p out is th output powr dlird from th DClink to th load. Th input powr can b xprssd with th sourc oltag and currnt in th synchronous rfrnc fram as: ( ) 3 pin = aia + bib + cic = did + qiq. (9) 2 Th output powr is gin by: p = i () out 2 whr c2 is th output currnt of th DC-link sid. Th capacitor powr is xprssd as []: 2 d cap d p = C V C 2 dt» dt () whr C is th DC-link capacitanc, and V is th DC-link oltag at th oprating point. In ordr to kp th DC-link oltag constant, th ariation of th capacitor powr is rquird to b zro.

Fault Tolrant Control of DC-Link Voltag Snsor for 697 C. Nonlinar Modling of th AC/DC PWM Conrtr By rarranging quations (4) to (), th nonlinar modl of th thr-phas AC/DC PWM conrtr is dscribd as [2]: x& = f ( x) + g u (2) y = h x whr: ( ) é ù Rs w - i d + iq - dd L s Rs f ( x) = -wid - - dq, æ ö di d qiq.5 + ç ë è C C ø û ( ) é h x = i i ù ë û. d q é ù d q g u =, Pout - C ë û III. ESTIMATION OF DC-LINK VOLTAGE BY THE A. Lunbrgr Obsrr LUENBERGER OBSERVER Th Lunbrgr obsrr is a kind of stat obsrr which stimats th intrnal stat of linar systms. Th stat quations for th Lunbrgr obsrr ar xprssd as [2]- [24]: xˆ & ( t) = Axˆ ( t) + Bu( t) + L( y( t) - yˆ ( t) ) (3) yˆ t = Cxˆ t ( ) ( ) whr ^ indicats th stimatd alus, x(t) is th stat ctor, u(t) is th input ctor, y(t) is th output ctor, A, B and C ar th systm paramtr matrics, and L is th obsrr gain matrix. Th obsrr rror dynamic is xprssd as: x &% t = A - LC x % t (4) ( ) ( ) ( ) whr: x% ( t) = x( t) - xˆ ( t). Fig. 2 shows a block diagram of th Lunbrgr obsrr. In ordr to nsur that th stimation rror approachs zro asymptotically from any of th initial stats, th obsrr pols should b placd on th lft-half plan, which is st by th gain matrix L. In this study, th obsrr pols ar placd in ordr to ha on ral and two complx roots, as p and α ± jβ, rspctily [25]. B. Linarization of th Nonlinar Systm of an AC/DC PWM Conrtr First, th nonlinar systm in (2) is linarizd by smallsignal analysis. Thn, th linar systm is obtaind as [8], [9]: whr: ( t) = ( t) + ( t) ( t) = Cx( t) x& Ax Bu y (5) u( s) I s I s x ( s) y( s) xˆ( s) Fig. 2. Block diagram of Lunbrgr obsrr. T = ë d q û x ( t) éi i ù, ( ) T yˆ( s) u t = éd q dd dq P ù ë out û, y ( t) = éid i ù ë q û, (6) é Rs D ù do - w - R D s qo A = w - - L, s.5e.5e do qo ë CVo CVo û é ù C = (7) ë û é V ù o - Vo B = - L. (8) s.5i.5i do qo - ë CVo CVo CVo û In (5) and (6), th uppr-cas ariabls ( d, q, d, q, d, q, I I E E D D V ) rfr to th oprating points in th stady stat, whras th lowr-cas ariabls d q d q d q ( i, i,,, d, d, ) rprsnt th prturbations around thir oprating points. C. Dtrmination of th Lunbrgr Obsrr Gains In ordr to obtain stabl stimation for all of th rangs of th DC-link oltag and th ariations of th systm paramtrs (L s, C ), th obsrr gain matrix should b slctd so that th ral parts of all ignalus of (A-LC) ar ngati. In this cas th obsrr gain matrix L is xprssd as: él L2 ù L = L2 L 22. (9) ë L3 L32 û T

698 Journal of Powr Elctronics, Vol. 4, No. 4, July 24 ff d = d + sw q ff q = q - sw d V L i V L i Fig. 3. Control block diagram of th AC/DC PWM conrtr. To dtrmin th ignalus of matrix (A-LC), th charactristic is xprssd as: whr dt( l - ( A - LC )) = (2) LO I l LO is th obsrr pol matrix as: l él ù LO = l2, ë l 3 û é ù I =. (2) ë û In this study, th obsrr pol locations ar slctd by trial and rror as -5, and -5, ± j3,. Thn, from (7) and (9)-(2), th gain matrix L is calculatd as: él L2 ù é4,5 4 ù L = L2 L 22 5 9,97 = -. ë L3 L32 û ë -43-23,79û IV. FAULT DETECTION OF THE DC-LINK VOLTAGE SENSOR AND TOLERANT CONTROL A. Fault Dtction of th DC-Link Voltag Snsor With th stimation of th DC-link oltag, th PWM conrtr can b controlld with a snsorlss control algorithm, which rducs th whol systm cost. Rgardlss of th cost rduction, th dgr of rdundancy for rliabl opration of th systm cannot b scurd with only th snsorlss control algorithm. For this dgr of rdundancy, th oltags and currnts nd to b both masurd and stimatd. Thn, th conrtr can continu oprating whn a snsor fault occurs. Th snsor fails whn it snds out a wrong signal with a significant rror. Th oltag is normally masurd through hall snsors, analog scaling circuits consisting of an amplifir and a low-pass filtr, and A/D (analog to digital) conrtrs. Snsor failurs somtims occur du to a malfunction of th powr supply of th snsors, and circuit board faults du to humidity, high tmpratur, tc [2], [4]. This study focuss on th fault dtction of DC-link oltag snsors and tolrant control by a snsorlss control algorithm whn th failur of a snsor occurs. Th faults of DC-link oltag snsors ar dtctd by a comparison of th masurd DC-link oltag and th stimatd on. If thr is a significant diffrnc btwn th two alus, it is discrnd that th snsor is faulty. Whn a snsor fault is dtctd, th fault flag, F f, is st to, whil it is zro undr normal conditions. Th oltag stimation rror, r(t), is calculatd as: Thn: - ˆ r ( t) = %. (22) ( ) ( ) if r t < V, thn F = th or if r t ³ V, thn F = th f f (23) whr V th is a thrshold alu. In this study, V th is chosn as %. B. Control of AC/DC PWM Conrtrs For thr-phas AC/DC/AC PWM conrtrs, th DC-link oltag is controlld by th sourc-sid conrtr, whr th control structur is cascadd by an outr oltag control loop and innr d-q currnt control loops as shown in Fig. 3 []. For DC-link oltag control without any orshoot in th transint stats, an IP (intgral-proportional) rgulator is prfrrd, whr th anti-windup tchniqu is also mployd [26], [27]. Th dq-axis componnts of th sourc currnts ar rgulatd by PI (proportional-intgral) controllrs, whr th crosscoupling trms and th sourc oltag as a disturbanc ar compnsatd in a fd-forward typ, as shown in Fig. 3.

Fault Tolrant Control of DC-Link Voltag Snsor for 699 2.5A/di (a) ˆ (b) -2 5 - ( Sliding ) ( Sliding ) 5A/di ˆ ˆ 375 (c) 36 35 (d) ˆ ( Sliding ) _ rr ( Sliding ) 5V/di 5V/di - T/di = 2 ms Fig. 5. Estimation prformanc using sliding mod obsrr in th cas of abrupt load changs. (a) d-axis currnts. (b) q-axis currnts. (c) DC-link oltags. (d) DC-link oltag stimation rror. Fig. 4. Flow chart of fault tolrant control of oltag snsor. TABLE I PARAMETERS OF SOURCE-SIDE CONVERTER ( Lunbrgr ) Sourc oltag Input rsistor Boost inductor DC-link capacitor DC-link oltag 22 V/ 6 Hz. Ω 3.5 mh,65 μf 36 V ( Lunbrgr ) Whn a snsor fault is dtctd, a fault tolrant control schm is actiatd. In this cas, th masurd DC-link oltag is rplacd by th stimatd on for th fdback control, as shown in Fig. 3. Fig. 4 shows a flowchart of th snsor fault dtction and tolrant control algorithm. ˆ ( Lunbrgr ) _ rr ( Lunbrgr ) V. SIMULATION RESULTS Simulations using PSIM wr carrid out to rify th alidity of th proposd mthod, whr an induction machin dri is usd as a load for th AC/DC/AC PWM conrtr. Th systm paramtrs for th sourc-sid conrtr ar listd in Tabl I. Th switching frquncy of th conrtrs is 5 khz. Th sampling tim is µs. In th simulation, th controllr gains wr chosn so that th bandwidths of th currnt and oltag controllrs ar 398 Hz and 32 Hz, rspctily. First, th stimation prformanc with th sliding mod obsrr [6], for th AC/DC/AC PWM conrtr undr stpwis load ariations was instigatd, as shown in Fig. 5. Th load profil applid to th AC/DC PWM conrtr is no load 3 kw - 2 kw no load. Fig. 5(a) shows th d-axis currnts, whr th stimatd currnt conrgs to th actual Fig. 6. Estimation prformanc of Lunbrgr obsrr in th cas of abrupt load changs. (a) d-axis currnts. (b) q-axis currnts. (c) DC-link oltags. (d) DC-link oltag stimation rror. on. Howr, th rippl componnt of th stimatd currnt is high. Th sam phnomna for th q-axis currnt and th DC-link oltag ar shown in Fig. 5(b) and (c), rspctily. Fig. 5(d) shows th stimation rror of th DC-link oltag, which is about 3 V. Nxt, th prformanc of th Lunbrgr obsrr, undr th sam conditions as thos usd in th cas of Fig. 5, is illustratd in Fig. 6, whr th obsrr gains dsignd in sction III ar usd. Fig. 6(a) shows th d-axis currnt, whr th stimatd currnt is narly th sam as th masurd on. In addition, th

7 Journal of Powr Elctronics, Vol. 4, No. 4, July 24 (a) (b) - 8 6 ( Lunbrgr ) ( Lunbrgr ).5A/di 2A/di ( Lunbrgr ) ( Lunbrgr ) (c) (d) 4 364 36 356 4 ˆ ( Lunbrgr ) _ rr ( Lunbrgr ) 2V/di 2V/di ˆ ( Lunbrgr ) _ rr ( Lunbrgr ) -4 6 () 4mH 2 2.4 (f).8mf.2 C T/di = 2 ms L s mh/di.3mf/di Fig. 7. Estimation prformanc of Lunbrgr obsrr in th cas of paramtr ariations. (a) d-axis currnts. (b) q-axis currnts. (c) DC-link oltags. (d) DC-link oltag stimation rror. () Variation of input filtr inductanc and DC-link capacitanc. q-axis currnt is stimatd wll, n undr transint conditions, as shown in Fig. 6(b). Fig. 6(c) shows th stimatd and masurd DC-link oltags, which ar ry clos. Th stimation rror is about.5 V, which is shown in Fig. 6(d). Ths rsults show that th stimation prformanc is xcllnt n whn th load is changd. Fig. 7 shows th stimation prformanc of th Lunbrgr obsrr undr paramtr ariations, whr th paramtr alus ar assumd to b changd in th controllr rathr than in th actual systm. An incras of 4% in th input inductanc or an incras of 2% in th DC-link capacitanc ha bn considrd, and ar shown in Fig. 7() and (f), rspctily. Fig. 7(a) and (b) show th d- and q-axis componnts of th sourc currnts, rspctily. It can b sn that th stimatd currnts follow th masurd currnts wll. Th masurd and stimatd DC-link oltags ar shown in Fig. 7(c), and th stimation rror is shown in Fig. 7(d). Ths rsults illustrat that th stimation rror is lss than 2 V n undr paramtr ariations. Th control prformanc of th conrtr without th DC-link oltag snsor is shown in Fig. 8, wr th stimatd alu of th DC-link oltag is usd as th fdback control. Th d- and q-axis sourc currnts follow thir rfrncs wll, and ar Fig. 8. Prformanc of DC-link oltag control without DC-link oltag snsor in th cas of abrupt load changs. (a) d-axis currnts. (b) q-axis currnts. (c) DC-link oltags. (d) DC-link oltag stimation rror. (a) (b) (c) (d) ().4 -.4 5-5 36-4kW -4kW ( Lunbrgr ) F f P out T/di = 2 ms ( Lunbrgr ) Snsor fault condition ˆ ( Lunbrgr ).2A/di 5A/di V/di 2kW/di Fig. 9. Control prformanc of th fault tolrant control undr th snsor failur of th DC-link oltag. (a) d-axis currnts. (b) q- axis currnts. (c) DC-link oltags. (d) Output powr. () Fault flag. shown in Fig. 8(a) and (b), rspctily. Fig. 8(c) shows th DC-link oltag, which is wll kpt at its rfrnc of 36 V. Th stimation rror is shown in Fig. 8(d), whr th maximum rror in th transint stat is lss than.5 V. Fig. 9 shows th prformanc of th fault tolrant control undr load ariations whn a fault of th DC-link oltag snsor

Fault Tolrant Control of DC-Link Voltag Snsor for 7 Fig.. Exprimntal stup. occurs. For this instigation, it is assumd that th snsor fault occurs for an intral of 2 ms, which is shown in Fig. 9(). It can b sn in Fig. 9(c) that th snsd DC-link oltag is rducd to zro at th fault. Howr, with th fault tolrant control, th DC-link oltag is controlld wll at its rfrnc, as shown in Fig. 9(c). Fig. 9(a) and (b) show th d- and q-axis currnt componnts, whr th control prformancs ar good n undr snsor fault and load ariation conditions. Fig. 9(d) shows th output powr of th conrtr. VI. EXPERIMENTAL RESULTS To rify th fasibility of th proposd mthod in practical applications, xprimntal tsts wr carrid out in th laboratory for a thr-phas AC/DC/AC PWM conrtr, which fds an induction motor dri. Fig. shows th layout of th xprimntal stup. Th paramtrs of th sourc-sid conrtr ar th sam as thos of th simulation as shown in Tabl. A DSP chip (TMS32VC33) is usd as th main procssor, and th switching frquncy of th conrtrs is 5 khz. Th xprimntal conditions ar th sam as thos of th simulation. Fig. shows th stimation prformanc of th Lunbrgr obsrr whn changing th conrtr paramtrs in th controllr. Fig. (a) and (b) show an incras of 4% in both th input inductanc and th DC-link capacitanc. It can b sn in Fig. (c) that th DC-link oltag is stimatd wll, sinc th stimation rror is about 7 V n in th cas of paramtr ariations. Fig. (d) and () show th stimatd and masurd alus of th d- and q-axis componnts of th sourc currnts, rspctily. Fig. 2 shows th control prformanc of th fault tolrant control for th PWM conrtr undr a snsor failur of th DC-link oltag. Th fault flag shown in Fig. 2(a) illustrats that th DC-link oltag snsor fault occurrd at 4 s, whil th snsd DC-link oltag is zro during th fault, as shown in Fig. ( a) 3.5m ( b) 65u ( c) ( d ) ( ) 4 36 32 4-4 6-6 ˆ L s Paramtr Chang C ˆ ˆ Paramtr Chang Fig.. Estimation prformanc of Lunbrgr obsrr in th cas of paramtr ariations. (a) Variation of input filtr inductanc. (b) Variation of DC-link capacitanc. (c) DC-link oltags. (d) d-axis currnts. () q-axis currnts. ( a) ( b) ( d ) ( ) 63 36-9 4 ( c) -4 6-6 2k -2k Flag fault ˆ ˆ ˆ P out Snsor Fault Fig. 2. Control prformanc of th fault tolrant control undr th snsor failur of th DC-link oltag (xp.). (a) Fault flag. (b) DC-link oltags. (c) d-axis currnts. (d) q-axis currnts. () Output powr. 2(b). Howr, th DC-link oltag is wll kpt at its rfrnc of 36 V with th fault tolrant control. Fig. 2(c) and (d) show th d- and q-axis currnt componnts, whr th control prformancs ar good n undr snsor fault and load ariation conditions. Fig. 2() shows th output powr of th conrtr.

72 Journal of Powr Elctronics, Vol. 4, No. 4, July 24 VII. CONCLUSIONS In this papr, a fault dtction and tolrant control schm for th DC-link oltag snsors in thr-phas AC/DC/AC PWM conrtrs has bn proposd, whr th Lunbrgr obsrr is usd to stimat th DC-link oltag. Th linar Lunbrgr obsrr systm has bn built from a nonlinar modl of th PWM conrtr, whr th stimation rror is about.5 V in th transint condition. With th proposd algorithm, th systm rliability is improd, which can aoid tripping th systm whn snsor faults occur. Th ffctinss of th proposd mthod has bn rifid by simulation and xprimntal rsults. Thy show that th stimation schm works wll undr ariations of th paramtrs in th PWM conrtr such as th input inductanc and th DC-link capacitanc. ACKNOWLEDGEMENT This work has bn supportd by KESRI (Kora Elctrical Enginring and Scinc Rsarch Institut) (29T65), which was fundd by MKE (Ministry of Knowldg Economy). REFERENCES [] S.-K. Sul, Control of Elctric Machin Dri Systms, Wily-IEEE Prss, 2. [2] Q. N. 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Fault Tolrant Control of DC-Link Voltag Snsor for 73 Soo-Chol Kim was born in 985. H rcid his B.S. and M.S. dgrs in Elctrical Enginring from Yungnam Unirsity, Gyongsan, Kora, in 2 and 23, rspctily. H is prsntly with Dawoo Shipbuilding and Marin Enginring Co., Ltd., Soul, Kora. His currnt rsarch intrsts includ AC machin dris, th control of powr conrtrs, and lctric propulsion systms. Thanh Hai Nguyn was born in Dong Thap, Vitnam. H rcid his B.S. dgr in Enginring from th Ho Chi Minh City Unirsity of Tchnology, Ho Chi Minh City, Vitnam, in 23, and his M.S. and Ph.D. dgrs in Elctrical Enginring from Yungnam Unirsity, Gyongbuk, Kora, in 2 and 23, rspctily. H is prsntly working as a Rsarch Profssor at Yungnam Unirsity. H was an Assistant Lcturr in th Collg of Tchnology, Can Tho Unirsity, Can Tho, Vitnam, from May 23 to Fbruary 28. His currnt rsarch intrsts includ powr conrtrs, machin dris, HVDC transmission systms, and wind powr gnration. Dong-Choon L rcid his B.S., M.S., and Ph.D. dgrs in Elctrical Enginring from Soul National Unirsity, Soul, Kora, in 985, 987, and 993, rspctily. H was a Rsarch Enginr with Dawoo Hay Industry, Kora, from 987 to 988. Sinc 994, h has bn a faculty mmbr in th Dpartmnt of Elctrical Enginring, Yungnam Unirsity, Gyongbuk, Kora. As a Visiting Scholar, h joind th Powr Quality Laboratory, Txas A&M Unirsity, Collg Station, TX, USA, in 998, th Elctrical Dri Cntr, Unirsity of Nottingham, Nottingham, U.K., in 2, th Wisconsin Elctric Machins and Powr Elctronic Consortium, Unirsity of Wisconsin, Madison, Wisconsin, USA, in 24, and th FREEDM Systms Cntr, North Carolina Stat Unirsity, Raligh, North Carolina, USA, from Sptmbr 2 to August 22. His currnt rsarch intrsts includ ac machin dris, th control of powr conrtrs, wind powr gnration, and powr quality. Profssor L is currntly a Publication Editor for th Journal of Powr Elctronics of th Koran Institut of Powr Elctronics. Kyo-Bum L rcid th B.S. and M.S. dgrs in lctrical and lctronic nginring from th Ajou Unirsity, Kora, in 997 and 999, rspctily. H rcid th Ph.D. dgr in lctrical nginring from th Kora Unirsity, Kora in 23. From 23 to 26, h was with th Institut of Enrgy Tchnology, Aalborg Unirsity, Aalborg, Dnmark. From 26 to 27, h was with th Diision of Elctronics and Information Enginring, Chonbuk National Unirsity, Jonju, Kora. In 27 h joind th School of Elctrical and Computr Enginring, Ajou Unirsity, Suwon, Kora. H is an associatd ditor of th IEEE Transactions on Powr Elctronics and th Journal of Powr Elctronics. His rsarch intrsts includ lctric machin dris, lctric hicls, and rnwabl powr gnrations. Jang-Mok Kim was born in Busan, Kora, in August 96. H rcid his B.S. dgr from Pusan National Unirsity (PNU), Pusan, Kora, in 988, and his M.S. and Ph.D. dgrs from th Dpartmnt of Elctrical Enginring, Soul National Unirsity, Soul, Kora, in 99 and 996, rspctily. From 997 to 2, h was a Snior Rsarch Enginr with th Kora Elctrical Powr Rsarch Institut (KEPRI). Sinc 2, h has bn with th School of Elctrical Enginring, Pusan National Unirsity (PNU), whr h is prsntly a Faculty Mmbr. In addition, h is a Rsarch Mmbr of th Rsarch Institut of Computr Information and Communication at PNU. His currnt rsarch intrsts includ th control of lctric machins, lctric hicl propulsion, and powr quality.