AN 761: Board Management Controller

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Contents Contents... 3 Design Example Description... 3 Supported Features...4 Requirements... 4 Hardware Requirements...4 Software Requirements...6 Design Example Walkthrough... 9 Hardware Setup Instructions... 9 Running the Design Example... 17 Supported Commands... 17 Customizing the Design Example...19 Concept... 21 Design in the Intel MAX 10 Device...21 Software Implementation... 24 Document Revision History for...27 2

This application note provides details on how to design and implement the board management controller using the Intel MAX 10 FPGA development kit and the Enpirion ED810X + FDMF5820 kit. Design Example Description This design example shows how to use an Intel MAX 10 device as a board management controller for the power-up sequencing of a typical system using the PMBus interface. Figure 1. Board Management Controller Implementation using the Intel MAX 10 FPGA Development Kit PC USB Port USB to UART Intel MAX 10 Development Kit Power Module via PMBus System Fan Intel MAX 10 FPGA Button LEDs The Intel MAX 10 design example uses the following hardware blocks: Internal analog-to-digital converter (ADC) and temperature sensor diode (TSD) User flash memory (UFM) Nios II soft processor Phase-locked loop (PLL) Related Information Board Management Controller Design Example Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

Supported Features Requirements The design example supports the following features: Control the power-up and power-down sequencing of any FPGA using the PMBusbased power modules. Monitor power rails of external power modules. Data log voltages or temperature conditions that exceed the defined-threshold values. These values are stored in the Intel MAX 10 UFM. You can configure the threshold values. Control the DC Fan Speed based on the temperature reported by the TSD. Related Information Intel MAX 10 FPGA Development Kit User Guide AN 692: Power Sequencing Considerations for Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 Devices Hardware Requirements System Requirements This design example targets the Intel MAX 10 FPGA development kit and ED810X +FDMF5820 kit. To enable the Power Management BUS (PMBus) communication, the Intel MAX 10 development kit must be connected to the ED810X+FDMF5820 evaluation kit. Related Information Board Management Controller Design Example External Hardware Requirement The Intel MAX 10 FPGA Development Board does not integrate a DC fan or PMBusbased power module. You need to connect these components through an external hardware. Intel recommends using the Intel Enpirion Power SoC in this design example. 4

Figure 2. Intel Enpirion Power Module Connections 1-kΩ pull-up resistor 3.3 V CONTROL is optional. In this design example, although CONTROL pins exist, they are not implemented. SCL SDA SALRT CONTROL ED810X and FDMF5820 Kit You can control the speed of the DC fan by varying the duty cycle of the pulse width modulation (PWM). Figure 3. External DC Fan Connections Fan 1N4003 9-12 V From FPGA Pin 100 K 2N7000 Power Module Grouping This design example uses three power modules. Each power module powers different power rails for the Intel Arria 10 device. Table 1. Power Module Grouping Group Nominal Value (V) Power Rails on Intel Arria 10 Device 1 0.9 V CC, V CCP, V CCR_GXB, V CCERAM 2 1.8 V CCPT, V CCH_GXB, V CCA_PLL 3 1.8 V CCPGM, V CCIO Each power group has different threshold and ramp voltage limits. The preset values are defined in the program in main.h. You can update the threshold and ramp voltage via UART using the THRESHOLD or RAMP command. 5

Pin Assignments and Description Table 2. Intel MAX 10 Pin Assignments Pin Pin Direction Location I/O Standard Description clk_in Input M9 2.5V Clock input for the whole system. reset Input L22 1.5V Reset the whole design. uart_rx Input Y19 2.5V Receive UART signal to the PC (host). uart_tx Output W18 2.5V Send UART signal from the PC (host). pmbus_alert[0] Input E8 3.3-V LVTTL Alert line for the PMBus. pmbus_alert[1] Input D5 3.3-V LVTTL Alert line for the PMBus. pmbus_alert[2] Input B5 3.3-V LVTTL Alert line for the PMBus. pmbus_scl Output C7 3.3-V LVTTL Clock output to the PMBus devices. pmbus_sda Bidirectional C8 3.3-V LVTTL Bidirectional data line for the PMBus. pmbus_control[0] Output A2 3.3-V LVTTL Control line for the PMBus. pmbus_control[1] Output A3 3.3-V LVTTL Control line for the PMBus. pmbus_control[2] Output B4 3.3-V LVTTL Control line for the PMBus. system_led[0] Output T20 1.5V System indicator for Group 1 power. system_led[1] Output U22 1.5V System indicator for Group 2 power. system_led[2] Output U21 1.5V System indicator for Group 3 power. system_led[3] Output AA21 1.5V System indicator for the UFM storage status. pwm_fan Output B7 3.3-V LVTTL PWM output signal for the DC fan. button_user Input M21 1.5V User button to perform manual power up. Software Requirements This design example requires the following software: Intel Quartus Prime version 15.1.2 Tera Term 6

Other Software The communication with the Nios II processor is established through the UART interface. You can use off-the-shelf terminal software such as Tera Term as a user console. When you set up the Tera Term software, select CR+LF to enable the New-line Transmit option. This ensure the command sent through the terminal is recognized by the controller. You also need to turn on the Local echo option to track the command entered. Figure 4. Setting Up the Tera Term Software Alternatively, you can use the example GUI that is provided with this design example for live data monitoring and display the ADC readout in a graphical format. 7

Figure 5. Board Control Management GUI The board management controller GUI is developed using TCL. You need to install a TCL interpreter to use the GUI. You can download the installer from the ActiveTCL Downloads. After installing the TCL interpreter, double click the BoardControl.tcl to open the GUI. Table 3. Functionality of Command Buttons Command Button/ Entry Detect COM PORT Connect COM PORT Select Channel Radio Button Upper Threshold or Lower Threshold Description Displays which COM PORT is connected to the PC. Double click the COM PORT to specify which COM PORT to connect. Click the Connect COM PORT to connect the selected COM PORT. Specifies which ADC channel that you want to stream the data and displays the data in graphical format. Specifies the threshold to be displayed on the graph as red lines. This does not alter the threshold limit for the controller. If TSD is selected at the Select Channel Radio Button, the upper threshold cannot be more than 100 C while the lower threshold cannot be less than 40 C. For other selection, the upper threshold cannot be more than 2.5V while the lower threshold cannot be less than 0V. continued... 8

Command Button/ Entry Start Stop Log File Name Clear Terminal Output Description Starts streaming the data for the channel selected in the Select Channel Radio Button. The value is displayed and plotted as a graph while the value is transmitted via the UART interface. Stops data streaming. You can select other channel in the Select Channel Radio Button and update the threshold value. Enter the file name and click Save Datalog if you want to save the output shown in the Interactive Terminal to a file. Clears the output in the Interactive Terminal. Related Information Tera Term Software ActiveTcl Community Edition Design Example Walkthrough Hardware Setup Instructions Intel MAX 10 Development Kit Figure 6. Intel MAX 10 Development Kit Connect to PC for JTAG Configuration Connect to PC for UART Communication User ADC Ports (up to 16 Channels) PM Bus Port and PWM Port 12 V, 2 A AC Adapter (Comes with Kit) LEDs Indicate Group Power Up Design Example Reset Button Manual Power Up/Down Button To run the GUI or the Tera Term software, you need to connect the UART (J11) to PC. You can manually start the power-up or power-down sequence by using the power-up or power-down button (USER_PB1). In this design example, only three ADC channels are used. You can customize the design if you require more ADC channels for your design. For this board, the maximum analog signal input is up to 2.5V. 9

Custom Fan Board This is a customized board consisting of other functions. You can design your own fan board using the design based on the External DC Fan Connections figure. Figure 7. Custom Fan Board PWM Input 9-12 V Fan Connection (Red and Black Wire Only) Ground Related Information External Hardware Requirement on page 4 10

ED810X+FDMF5820 Kit Figure 8. ED810X+FDMF5820 Kit VOUT Connection to MAX 10 ADC Port 12 V VIN 1-KΩ Pull-Up Resistor Resistor Configuration for PM Bus Address PM Bus J2.2 SCL J2.4 SDA J2.6 SMBALERT J2.8 CONTROL Figure 9. ED810X+FDMF5820 Jumper Jumper 11

ED810X+FDMF5820 Kit Setup Instructions To set up the ED810X+FDMF5820 kit, follow these steps: 1. Connect all the jumpers as shown in the ED810X+FDMF5820 Jumper figure. 2. Solder 1-kΩ resistors on SDA, SCL, and SMBALERT lines. You are only required to perform this step on the first ED810X+FDMF5820 kit connected in a daisy-chain connection. 3. Solder R22 and R23 with the correct resistor value to set the PMBus address for each power module. 4. Connect the jumper to J7 as shown in the ED810X+FDMF5820 Jumper figure. 5. To set the desired voltage, refer to the FDMF5820 Kit User Guide. This design example uses the following PMBus address for the power modules. Table 4. PMBus Address for Each Power Module To configure the PMBus address to other values, refer to the device datasheet. Group Nominal Value (V) R22(kΩ) R23(kΩ) PMBus Address (HEX) 1 0.9 Short 3.3 0x20 2 1.8 Short 5.6 0x30 3 1.8 Short Short 0x40 Related Information FDMF5820DC - Smart Power Stage (SPS) Module with Integrated Temperature Monitor Connection Diagram for the Board Management Controller Figure 10. Fan Board to the Intel MAX 10 Development Kit Connections Fan 1N4003 A 9-12 V From FPGA Pin 100 K 2N7000 12

Figure 11. Fan Board Power Connections Custom Fan Board Setup Instructions To set up the custom fan board, follow these steps: 1. Connect J4.4 on the Intel MAX 10 Development Kit to point A on the custom fan board. Point A connects to the gate of 2N7000. 2. Connect J4.5 on the Intel MAX 10 Development Kit to GND on the custom fan board. 3. For the 12-V DC-fan connection, connect the red and black lines. You must add a supply line to the fan. ED810X+FDMF5820 Kit and Intel MAX 10 Development Kit Setup Instructions Table 5. Intel MAX 10 Development Kit and ED810X+FDMF5820 Kit PMBus Lines Connections Intel MAX 10 Development Kit ED810X+FDMF5820 Kit Description J4.1 J2.2 Connect the SCL (yellow) to the first ED810X+FDMF5820 Kit. J4.2 J2.4 Connect the SDA (white) to the first ED810X+FDMF5820 Kit. J5.1 J2.6 Connect the SALRT (brown) to the first ED810X+FDMF5820 Kit. J5.2 J2.6 Connect SALRT (red) to the second ED810X+FDMF5820 Kit. J5.3 J2.6 Connect SALRT (grey) to the third ED810X+FDMF5820 Kit. J4.5 J2.1 Connect to GND. J4.11 J2.2 J5.5 J2.3 13

Figure 12. PMBus Connection on the ED810X+FDMF5820 Kit Figure 13. PMBus Connection from the Intel MAX 10 Development Kit to the First ED810X+FDMF5820 Kit 14

Table 6. ED810X+FDMF5820 Kit Daisy-Chain Connections First ED810X+FDMF5820 Kit Second ED810X+FDMF5820 Kit Third ED810X+FDMF5820 Kit J2.2 J2.2 J2.2 J2.4 J2.4 J2.4 Figure 14. ED810X+FDMF5820 Kit Connection for VOUT Table 7. VOUT to J20 Header Connections VOUT Intel MAX 10 Development Kit VOUT for the first ED810X+FDMF5820 Kit J20.1 VOUT for the second ED810X+FDMF5820 Kit J20.3 VOUT for the third ED810X+FDMF5820 Kit J20.5 To set up the PMBus connections between the Intel MAX 10 Development Kit and the ED810X+FDMF5820 Kit, follow these steps: 1. Connect the PMBus lines between the Intel MAX 10 Development Kit and the ED810X+FDMF5820 Kit. 2. Connect the PMBus on each of the ED810X+FDMF5820 Kit in a daisy chain. For more information, refer to the ED810X+FDMF5820 Kit Daisy-Chain Connections table. 15

a. Connect SCL and SDA lines from the first ED810X+FDMF5820 Kit to the second ED810X+FDMF5820 Kit. b. Repeat this step for the second and third ED810X+FDMF5820 Kit in the daisy chain. 3. Connect the VOUT on the ED810X+FDMF5820 Kit to the Intel MAX 10 Development Kit (J20 header) to monitor the voltage level of the power module using the Intel MAX 10 ADC. For more information, refer to the ED810X +FDMF5820 Kit Connection for VOUT figure and VOUT to J20 Header Connections table. Caution: Figure 15. The analog channel of the Intel MAX 10 development kit supports up to 2.5V only. Do not provide voltage higher than 2.5V to the analog channel. Intel MAX 10 Development Kit Connection for the ADC Input Port You can modify the design example if you are using more than three power modules in your design. There are up to 16 ADC channels available. After you have the complete hardware connection for the design example, you can program the bmc.pdf to the Intel MAX 10 device to test the functionality of the design example. If you need to customize the design example, follow the steps listed in the Customizing Design Example section. 16

Figure 16. Design Example Complete Hardware Connections First Board PM Bus Ports ADC Input Ports Second Board +12 V DC Fan Third Board +12 V for Custom Fan Board (to Benchtop Power Supply) +12 V to Power Up (Benchtop Power Supply) Running the Design Example To run the design example, follow these steps: 1. Connect all the required hardware. For more information, refer to the Hardware Setup Instruction section. 2. Download and install the Board Management Controller design example from the design store. For more information, refer to the Importing Design Template section. 3. Program the Intel MAX 10 device on the Development Kit with bmc.pof located in the project folder. 4. Open Tera Term or BoardControl.tcl to send command to the Nios II processor. For more information, refer to the Other Software section. Related Information Hardware Setup Instructions on page 9 Customizing the Design Example on page 19 Other Software on page 7 Board Management Controller Design Example Supported Commands Table 8. Controller Supported Commands All commands are case sensitive. Command ADC Description Reads the ADC channel voltage or temperature. continued... 17

Command Description Example: ADC ALL reads all ADC channels. ADC 00 reads ADC Channel 0. ADC 01 reads ADC Channel 1. ADC TSD reads temperature. POWER SEQ READ UFM ERASE UFM CHECK SPACE THRESHOLD RAMP TEMP SHOW LIMIT RESET FAN Turns on the power groups. Example: POWER 1 ON turns on the power for Group 1. POWER 1 OFF turns off the power for Group 1. POWER 2 ON turns on the power for Group 2. Powers on or off all power groups based on the predefined sequence. Example: SEQ ON turns on the power from Group 1 to Group 3 in sequence. SEQ OFF turns off the power from Group 3 to Group 1 in sequence. Reads all the data stored in the UFM. Erases all the data stored in the UFM. Checks the available space left in the UFM. Updates the upper or lower threshold value for each channel. Data is logged into the UFM when the value detected on each channel is beyond the threshold value. Example: THRESHOLD 1 H 1.2 sets the upper threshold for Channel 1 to 1.2V. THRESHOLD 1 L 0.95 sets the lower threshold for Channel 1 to 0.95V. THRESHOLD 15 H 1.6 sets the upper threshold for Channel 15 to 1.6V. Updates the threshold value for the ramp-up or ramp-down voltage. During the power-up operation, the controller checks if the voltages on a power group have reached the threshold value (High) before turning on the next power group. During the power-down operation, the controller checks if the voltages on a power group is below the threshold value (Low) before turning off the power module group. Example: RAMP H 1 0.8 sets the high threshold value to 0.8V for Group 1. RAMP L 1 0.05 sets the low threshold value to 0.05V for Group 1. Updates the lower or upper threshold value for the TSD. Data is logged into the UFM when the temperature detected by the TSD is beyond the threshold value. This does not impact the fan speed. Example: TEMP H 80 sets the high threshold value to 80 C. TEMP L 20 sets the low threshold value to 20 C. Shows all limits set in the board management controller. Resets all limits to the default values defined in main.h. Changes the DC fan speed by changing the duty cycle of the PWM. Example: FAN 1 changes the fan speed to 1, where the duty cycle is 33.33%. FAN 3 changes the fan speed to 3, where the duty cycle is 100%. LOG UFM Enables or disables data log to the UFM. Example: LOG UFM ON enables data log to the UFM. LOG UFM OFF disables data log to the UFM. continued... 18

Command SHOW TIMER UPDATE TIMER HELP Description Displays the interval to check the ADC or TSD. Updates the interval to check the ADC or TSD. Example: UPDATE TIMER 5 updates the interval to five minutes. The controller checks the ADC or TSD on the interval of every five minutes. Displays the summary of all the supported commands on the terminal. Customizing the Design Example To customize the design example to meet your requirements, follow the steps listed in the Importing Design Template and Importing Software Code for the Nios II Processor sections. Importing Design Template To import design template, follow these steps: 1. Download the design example from Intel Cloud. 2. Launch the Intel Quartus Prime software. Click the File menu and select New Project Wizard. 3. Specify the working directory for your design. Type BMC as the project name. Click Next. 4. Select Project template in the Project Type page. Click Next. 5. On the Design Templates page, click Install the design templates. 6. In the Design Template Installation window, browse to the working directory where the bmc.par file is located. The default destination directory is the location you have specified in Step 3. Next, click OK to install the design template. 7. After the installation completes, you will receive a message to prompt you that the design template installation was successful. Click OK. 8. On the Design Templates page, select Board Management Controller in the list of available design templates. Click Next. 9. On the Summary page, click Finish to complete the Intel Quartus Prime project creation. 10. On the Tool menu, select Platform Designer. 11. In the Open window, select nios.qsys file. Click Open. 12. If you encounter error messages on the nios.i2c_opencores_0 and nios.pwm_0, you need to include the <design_folder>/platform/ip folder in the IP search path. 13. On the Tools menu, select Options to update the IP search path. 14. In the Options window, click Add and browse to the <design_folder>/platform/ip folder. Click Finish. 15. You can customize the Platform Designer system to meet your design requirements. Save the changes and generate the HDL. 19

Importing Software Code for the Nios II Processor To import the software code for the design example, follow these steps: 1. Unzip the bmc_software.zip in the <project_folder>\software folder. 2. Launch the Nios II Software Build Tools for Eclipse. 3. Specify the workspace for the project. 4. In the Project Explorer tab, select Import. 5. On the Import window, select Import Nios II Software Build Tools Project. Click Next. 6. On the Import Software Build Tools Project window, click Browse to select the <design_folder>/software/bmc folder in the Project location. Type bmc as the Project name. Click Finish. 7. On the Importing a custom Software Build Tools project window, click Browse to select the <design_folder>/software/bmc_bsp folder in the Project location. Type bmc_bsp as the Project name. Click Finish. 8. In the Project Explorer tab, select the bmc_bsp project. Right-click and select Nios II and Generate BSP. 9. You can edit the C codes in the bmc folder to meet your design requirements. Save the changes. 10. On the Project menu, select Build All to compile the changes made on the C codes. 20

Concept Design in the Intel MAX 10 Device Figure 17. Platform Designer System Block Diagram 1-Minute Timer On-Chip RAM PM Bus, SCL, SDA, Control, Alert Platform Designer System ADC Channel 0-15 Phase-Locked Loop (PLL) Nios II Processor Pulse Width Modulation (PWM) UART (RS-232) On-Chip Flash (UFM) LED I/O Table 9. Intel MAX 10 Design Components Block Description Nios II Processor PLL Timer On-Chip RAM The soft processor manages the operation of the design. The Nios II E core is used in this design example. Synthesizes the clocks required in this design example. PLL output counter C0 to synthesize 80-MHz clock for the whole system. This design example uses a 1-minute timer. By default, the system checks for voltages and temperature at every 5- minutes interval. If the voltage or temperature exceeds the preset limits, the Nios II processor will data log the value to the UFM. You can change the timer interval value (TIMER_MINUTE) in main.h. You can also change the timer minute using the UPDATE_TIMER command. Storage for the program memory. TSD The TSD measures the temperature on the Intel MAX 10 device. The presets are defined in main.h. You can also preset on-the-fly using the TEMP command when connected to a PC through the UART. The fan speed is based on the threshold temperature in the system. PWM This is a custom Platform Designer component. The duty cycle of the PWM is used to control the fan speed. continued... 21

Block Description For more information about this custom component, refer to the PWM Registers and Setting table. System fan Temperature < low threshold the PWM duty cycle is 33%. Low threshold < temperature < upper threshold the PWM duty cycle is 66.55%. Temperature > upper threshold the PWM duty cycle is 100%. The default value for the low threshold is 20 C and the high threshold is 50 C. You can set the threshold value using the TEMP command. TEMP L trigger point for the low threshold. TEMP H trigger point for the high threshold. You can change the duty cycle and the PWM frequency in fan.c. When the board is powered on, the fan runs at 33.33% duty cycle. After each timer interrupts, the program reads the TSD temperature and tune the fan to operate at a different speed. You can change the fan speed to 1, 2, or 3 using the FAN command. ADC You can send command to read the voltage and temperature of each channel. There are up to 16 analog inputs that are muxed to the Intel MAX 10 ADC. This enables the Intel MAX 10 device to monitor multiple voltage rails in the system. continued... 22

Block Description UFM PMBus UART Storage for data logs failing channel, failing voltage, or failing temperature. Data is stored based on their failing condition. Two types of data are stored in UFM1. For a failing voltage 0x000AYXXX is logged into the UFM. For a failing temperature 0x00050XXX is logged into the UFM. Where Y is the failing channel or group, XXX is the 12-bit output data produced by the ADC or TSD block. LED3 is turned on when UFM1 is full. No new data log will be written into UFM1 when it is full. When UFM1 is full, you need to read all the UFM1 data to the PC. You can save the readout to a file on the PC for analysis if required. After that, you need to erase the UFM before new data can be logged into the UFM again. You can also perform some basic functions by using Erase UFM1, Read UFM1, and Check UFM1 Space commands. The PMBus is built using the OpenCores IP and is used to control the external power module. The PMBus is a standard protocol used in power management applications. It is built on top of the I2C with additional ALERT and CONTROL lines. In this design example, the SCL, SDA, and ALERT pins must be pulled to high using a 1-kΩ resistor to run at 400 khz. This design example supports the following commands: OPERATION ON turns on the power module OPERATION OFF turns off the power module CONFIG ON configures the power module operation by the PMBus only You can add new commands in power.c and power.h. Interactive terminal. The list of supported commands in this design example is listed in the Supported Commands table. You can add your command by modifying main.c. Table 10. PWM Registers and Settings The duty cycle of the PWM is pulse divided by period. Register Name Size (Bits) Address (Binary) Setting R/W Period 32 0 Specify the PWM period, in clock cycles. Pulse 32 1 Specify the duration of the high pulse of the PWM, in clock cycles. R/W R/W 23

Software Implementation Figure 18. Board Management Controller Software Flow Start Initialize Variable Check Process Group 1 Group 1 Voltage Initialize Peripheral Initialize Interrupt Check Group 2 Process Group 2 Voltage Check Group 3 Process Group 3 Voltage Check Temperature Process Temperature and Control Fan Check Steam Process Stream of Data Check Command User Command Decode and Process 24

The following is the flow of the design example: During system start up Initialize system variable Initialize peripheral (ADC, power module, system fan, UFM, timer, and watchdog timer) ADC Reset to stop the ADC sample Power module Set the I2C frequency to 400 KHz Enable the On/Off control of the power module through PMBus Turn off all power module Turn off the LED indicator on the development kit System fan Set the fan speed to medium (50% duty cycle) UFM Read the last UFM address data is 0xE0000000 If true, the UFM content is not erased If false, the UFM content will be erased When the UFM is clear, it will be showing the full LED indicator Timer Enable timer for the voltage and temperature monitor Watchdog timer The watchdog timer resets the board management controller if it is not responding after 10 seconds during power up or power down Initialize system interrupt Enable interrupt for the PMBus ALRT line Enable interrupt for the button action Enable interrupt for the timer Enable interrupt for the UART receive 25

After the completion of all initialization Board management controller turn on the power supplies by power group Preset voltage for each group: Group 1 at 0.9 V Group 2 at 1.0 V Group 3 at 1.2 V Power-up sequence based on the Intel Stratix 10 FPGA Group 1 to Group 2 to Group 3 Power-down sequence based on the Intel Stratix 10 FPGA Group 3 to Group 2 to Group 1 Four waiting input: Wait for the press button Once press button, check if the flag for all power modules is turn on or turn off If turn off, proceed to power up the power modules using the powerup sequence If turn on, proceed to shut down the power modules using the powerdown sequence Wait for the timer to trigger voltage and temperature measurement Upon reaching the five seconds interval, the board management controller triggers the ADC to check the temperature of the Group 1, Group 2, and Group 3 voltage regulators and the Intel MAX 10 FPGA Voltage Review all three modules to ensure there is no voltage supply that violates the preset voltage Any violation of the preset voltage will have data log into the UFM Temperature Any violation of the preset temperature will have data log into the UFM High temperature preset 50 C Low temperature preset 20 C System fan Fan with PWM duty cycle of 100% if high temperature is detected (50 C) Fan with PWM duty cycle of 30% if low temperature is detected (20 C) By default, fan with PWM duty cycle of 50% Wait for the user input from the USB Preset commands in the firmware read voltage, set timer, read UFM, delete UFM, and preset threshold voltage Each command has an integrated function Watchdog timer check 26

Document Revision History for AN 761: Board Management Controller Document Version Changes 2018.06.27 Rebranded as Intel. Updated the power-up and power-down sequencing feature in the Supported Features section. Updated the Software Implementation section to include more details on the design example flow. Updated the Board Management Controller Implementation using the Intel MAX 10 FPGA Development Kit figure. Updated the Design Example Pin Assignments table to include the pin directions. Revamped the document structure. Date Version Changes May 2016 2016.05.02 Initial release. 27