1 Mixed-Signal-Electronics PD Dr.-Ing. Stephan Henzler
2 Chapter 6 Nyquist Rate Analog-to-Digital Converters
3 Analog-to-Digital Converter Families Architecture Variant Speed Precision Counting Operation single/dual slope integration low high Weighted Operation successive approximation algorithmic converter w/wo redundancy, callibration medium medium Flash Operation direct flash multi-stage flash interpolating flash folding flash high low to medium Oversampling -modulation, i.e. noise shaping discrete time continuous time low to medium high Time based emerging tbd. tbd. Sampling frequency can be further increased by pipelining time interleaving, i.e. parallelization
Stephan Henzler Advanced Integrated Circuit Design 2011/12 4 General ADC Model Linear model often very useful limitations as quantization noise is de-correlated from signal Input signal must change sufficiently fast sufficiently strong
5 Dual-Slope Analog-to-Digital Converter
6 Dual-Slope Analog-to-Digital Converter
7 Iterative Analog-to-Digital Converters Tracking ADC Successive Approximation ADC Algorithmic ADC Pipeline ADC
Stephan Henzler Advanced Integrated Circuit Design 2011/12 8 Tracking ADCs
9 Converter with Successive Approximation What would you ask if you had N questions to find out the approximate value of the input voltage? 1. Is it positive or negative? NEGATIVE 2. Is it in the upper or lower negative region? 3. UPPER
10 Converter with Successive Approximation This is a binary search technique: Partition the interval where the input voltage is located in two sub-intervals and check whether the voltage lies in the upper or lower part
11 Converter with Successive Approximation
12 Converter with Successive Approximation (cont) ADC is mainly a DAC and a comparator (These are the critical building blocks) Conversion principle: Make DAC voltage equal to input voltage, minimize error Depending on the voltage comparison the bits in the SAR register are iteratively set or reset
13 Modified SAR Algorithm Also based on binary search technique Comparison against zero More suited for implementation, e.g. charge redistribution
14 Modified SAR Algorithm
Charge Redistribution SAR Converter Phase I: Input Tracking Stephan Henzler Mixed-Signal-Electronics 2011/12 15
Charge Redistribution SAR Converter Phase II: Hold Stephan Henzler Mixed-Signal-Electronics 2011/12 16
Charge Redistribution SAR Converter Phase III: SAR Evaluation Stephan Henzler Mixed-Signal-Electronics 2011/12 17
Charge Redistribution SAR Converter Phase III: SAR Evaluation Stephan Henzler Mixed-Signal-Electronics 2011/12 18
19 Add-On Material Hybrid SAR Converters Search can be done with different references Same idea as for DACs monotonous resistor string for MSBs binary weighted cap array for LSBs 1. Charge caps to -vin 2. Binary search in resistive network: vx = -vin + vres 3. Interpolate in between two subsequent taps of resistor string by charge redistribution
Stephan Henzler Advanced Integrated Circuit Design 2011/12 20 More Details on SAR and Algorithmic ADC Architectural Considerations on SAR Pipelined SAR Redundant SAR Remember: The goal is to make this error voltage equal to zero
Stephan Henzler Advanced Integrated Circuit Design 2011/12 21 Detailed SAR Architecture Let s look at the DAC in detail Thermometer Coding Each DAC has same error contribution Remainder: Aaron Buchwald, Pipelined A/D Converters: The Basics, ISSCC 2008
Stephan Henzler Advanced Integrated Circuit Design 2011/12 22 Binary Weighted SAR Binary weighting is desirable to reduce number of sub-dacs Remainder: Error contribution due to DAC mismatch scales with binary weigting of reference
Stephan Henzler Advanced Integrated Circuit Design 2011/12 23 Binary Weighted SAR
Stephan Henzler Advanced Integrated Circuit Design 2011/12 24 Weighted SAR with Distributed Gain Binary weighting can be achieved also by using equal DACs with a single reference voltage but with gain / scaling elements Due to scaling MSB DAC is most critical Linear transformation enables distributed gain
25 Algorithmic Analog-to-Digital Converter Comparator threshold constant Voltage increment/decrement constant remainder is doubled in each iteration step accurate x2 circuit required
26 Algorithmic Analog-to-Digital Converter
27 Robertson Diagram
28 Illustration in Robertson Diagram 2. 3. 4. 1. 5.
29 Lecturer Page Version Algorithmic Analog-to-Digital Converter ADC DAC Long conversion time N cycles per inout sample
30 Add-On Material Voltage Doubling in Algorithmic Converter V 2 V 1 Sample remainder V err together with opamp offset voltage Amplifier configured as voltage follower C2 charged to amplifier offset voltage
31 Add-On Material Voltage Doubling in Algorithmic Converter V 2 V 1 Disconnect input, discharge C 1 Transfer charge of C 1 to C 2
32 Add-On Material Voltage Doubling in Algorithmic Converter V 2 V 1 Disconnect C2, charge Q2 unchanged Sample input again
Add-On Material Voltage Doubling in Algorithmic Converter V 2 V 1 Combine charge on C1, offset compensated, Four clock cycles required! Stephan Henzler Mixed-Signal-Electronics 2011/12 33
Stephan Henzler Advanced Integrated Circuit Design 2011/12 34 Weighted SAR with Distributed Gain Algorithmic converter in unfolded implementation Long conversion time N x TADC + N x TDAC Speed-up by insertion of ADC and S&H in each stage pipelining: high throughput at the price of latency
Stephan Henzler Advanced Integrated Circuit Design 2011/12 35 Pipelined ADC 1 Going for pipelined-adc means cut the feed-back loop add a sample-and hold at the output of each stage to store the remainder, i.e. the stage quantization error add a comparator, i.e. coarse ADC at input of each stage
36 Pipelined ADC 2