Lec Sequential CMOS Logic Circuits
Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative behavior of sequential circuits is due to either a direct or an indirect feedback connection between the output and input
Critical Components of Sequential Circuits Basic Regenerative Circuits Categories of Basic Regenerative Circuits. Bistable Circuits: Two stable states or operation modes, each of them can be attained under certain input and output conditions. The most widely used and the most important class which is used for the basic latch, flip-flop circuits, registers, and memory elements.. Monostable Circuits: One stable state or operation mode 3. Astable Circuits: No stable operating point or state which the circuit can preserve for a certain time period. The output oscillates without settling into a stable operating mode. Sequential Circuits Bistable Monostable Astable 3
Behavior of Bistable Elements (/7) Two Identical Cross-Coupled Inverter Circuit Voltage Transfer Curves» The output voltage of inverter () is equal to the input voltage of inverter (), and the output voltage of inverter () is equal to the input voltage of inverter ().» A and B are stable points: If the circuit is initially operating at one of them, it will preserve this state. The gain is smaller than unity. V i =V o A stable C unstable V i V o B stable V i =V o V o V i Energy 4
Behavior of Bistable Elements (/7)» C is an unstable point: The voltage gains of both inverters are larger than unity. A small voltage perturbation at this operating point will be amplified the operating point will move to one of the stable operating points, A or B. Energy Levels:» The potential energy is at its minimum at A and B, since the voltage gains of both inverters are equal to zero.» The potential energy is at its maximum at C, since the voltage gains of both inverters are maximum. (all four transistors are in saturation modes) V DD V DD V o V i V i V o V OH V th V OL V o V o t 5
Behavior of Bistable Elements (3/7) Analysis of the Output Voltages Let the initially operating point is at v o =v o =V th, and assume that the gate capacitance (C g ) of each inverter is much larger than the drain capacitance (C d ). The drain current of each inverter is equal to the gate current of the other inverter. i g = i d = g m v g i g = i d = g m v g g m is the small-signal transconductance of the inverter. The gate voltages can be expressed by gate charges, q and q v g = q / C g (Eq. B) v g = q / C g Also the small-signal gate currents can be expressed as i g = C g dv g /dt i g = C g dv g /dt (Eq. A) (Eq. C) i g i d v g vg i d i g 6
7 Behavior of Bistable Elements (4/7) Analysis of the Output Voltages Combine Eq. A and C, we have Replace the gate voltages by Eq. B, we obtain The above equations can be simplified to dt dq q C g dt dq q C g g m g m v g vg i g i d i d i g ; g C q q C g dt q d dt q d g C q C g m g g m m g g m dt dv C v g dt dv C v g g g g m g g g m
8 Behavior of Bistable Elements (5/7) Analysis of the Output Voltages Therefore, where q () = C g v g () Replace the gate charge pf both inverters with the corresponding out-put voltages variables, we have For large values of t, the above equations can be approximated as e e t t q q q q t q () () ' ' e e e e t o o t o o o t o o t o o o v v v v t v v v v v t v () () () () ' ' ' ' e e t o o o t o o o v v t v v v t v () () ' ' for t for t
Behavior of Bistable Elements (6/7) Analysis of the Output Voltages Depending on the polarity of the initial small perturbations dv o () and dv o (), the v o and v o will diverge from their initial values of V th to either V OL and V OH. The polarity of dv o must always be opposite to that of dv o, because of the charge-conservation principle. Therefore, v o and v o always diverge into opposite directions. VOH vo Vth unstable VOL vo VOL Vth VOH Phase-plane Representation 9 v o : V th V OH or V OL v o : V th V OL or V OH
Behavior of Bistable Elements (7/7) Analysis of the Output Voltages As a bistable circuit settles from unstable operating point to its stable point, a signal travels around INV loop n times. vo vo Loop v o (t)/v o ()e t/ If during interval t = T, the signal travels around the loop n times A n e T/ V OH V th V OL loop loop loop n A A v o e t/ v o A n t T
Naming Conventions A latch is level sensitive A register is edge-triggered There are many different naming conventions For instance, many books call edge-triggered elements flip-flops Digital Integrated Circuits nd
Latch versus Register Latch stores data when clock is low Register stores data when clock rises D D Clk Clk Clk Clk D D Digital Integrated Circuits nd
Latches 3 Digital Integrated Circuits nd
SR Latch Circuit The two cross-coupled inverters can perform a simple memory function of holding its state. However, the two-inverter circuit alone has no provision for allowing its state to be changed externally from one stable operating point to other. In order to allow such a change of state, we need to add simple switches which can be used to force or trigger the circuit from one operating point to the other. S R S R NOR-based SR Latch Schematic Diagram of SR Latch 4
SR Latch Circuit (Cont.) The below circuit shows the simple CMOS SR latch which consists of two triggering inputs, S (set) and R (reset). The SR Latch consists of two CMOS NOR gates. One of the input terminals of each NOR gate is used to cross-couple to the output of the other NOR gate. The second input enables triggering of the circuit. V DD V DD M 6 M 8 basic cross coupled inverter M 5 M 7 S M M M 3 M 4 R 5
SR Latch Circuit Truth Table Set: S=, R= n+ =, n+ =. The SR latch will be set regardless of its previous state. Reset: S=, R= n+ =, n+ =. The SR latch will be reset regardless of its previous state. Hold: S=, R= n+ = n, n+ = n. The previous states will be held. Not Allow: S=, R= n+ =, n+ = active high S R n+ n+ Operation n n Hold Set Reset Not Allowed Truth Table of NOR-based (active high inputs) SR latch 6
SR Latch Circuit Operation Modes of the Transistors S R n+ n+ Operation NMOS PMOS V OH V OL V OH V OL M, M on; M 3, M 4 off M 7, M 8 on; M 5, M 6 off V OL V OH V OL V OH M, M off; M 3, M 4 on M 7, M 8 off; M 5, M 6 on V OL V OL V OH V OL M, M 4 off; M, on M 6, M 8 on; M 7, on V OL V OL V OL V OH M, M 4 off; M 3, on M 6, M 8 on; M 5, on V DD V DD M 6 M 8 basic cross coupled inverter S M M 5 M 7 M M 3 M 4 R 7
SR Latch Circuit Transient Analysis For transient analysis, we have to consider an event which results in a state change, reset set, or set reset In either case, we note that both of the output nodes undergo simultaneous voltage transitions. One is from logic-low to logichigh, and the other is from logic-high to logic-low. The exact transient analysis need to solve two coupled differential equations. For simplicity, we can assume that the two events take place in sequence rather than simultaneously. (overestimation) Switching Time Calculation The total lumped capacitance at each output node can be approximated as C = C gb, +C gb,5 +C db,3 +C db,4 +C db,7 +C sb,7 +C db,8 C = C gb,3 +C gb,7 +C db, +C db, +C db,5 +C sb,5 +C db,6 8
SR Latch Circuit Transient Analysis (Cont.) Assuming that the latch is initially reset and that a set operation is being performed, the rise time associated with node can be estimated as rise, (SR-latch) = rise, (NOR)+ fall, (NOR) V DD V DD S M M C M 3 M 4 C M on rise, (NOR) R 9
SR Latch Circuit NAND-based (active low signals) V DD V DD basic cross coupled inverter S R active low S R n+ n+ Operation Not Allowed Set Reset n n Hold
Clocked Latch and Flip-Flop Circuits The previous SR latch circuits are asynchronous sequential circuits. The synchronization can be introduced through clock, which the outputs will respond to the input levels only during the active period of a clock pulse. Clocked SR Latch S SR Latch R When =, S, R have no influence of, Hold Set State: =, S=, R= n+ =, n+ = Reset State: =, S=, R= n+ =, n+ = Not Allowed: =, S=, R= Active High
AOI-based Implementation of Clocked NOR-based SR Latch The AOI-based implementation need a very small transistor count, compared with the circuit consisting of two AND and two NOR gates» NOR-based: transistors» AOI-based: transistors V DD V DD NOR SR Latch S M M M 3 M 4 R M
Operation of Clocked SR Latch Operation S R n+ n+ Hold X X n n Set Reset Not Allow S R Glitch Glitch Free When Glitch ON S (or R) occurs during =, is set (or reset). Level Sensitive: When =, any changes in S, R will effect. 3
Clocked NAND-based SR Latch S R When =, S and R have no influence of and Hold Operation S R n+ n+ Hold X X n n Set Reset Not Allow 4
OAI-based Implementation of Clocked NAND-based SR Latch The OAI-based implementation need a very small transistor count, compared with the circuit consisting of two OR and two NAND gates V DD V DD NAND SR Latch M M 4 5 S M Synchronous operation Level sensitive Not allowed input sequence M 3 (any changes in S and R as = will be reflected onto outputs) R
Clocked JK Latch NAND SR J S = hold = active No not allowed combination K R J K n n S R n+ n+ Operation Hold Hold Reset = Reset Set Set Toggle Toggle OSC 6
AOI-based Implementation of NOR-based Clocked JK Latch The AOI-based implementation has a very small transistor count, and a more compact circuit compared to all-nand realization. V DD V DD K J 7
JK Toggle Switch J =K= J= JK K= Latch T Iff JKP > T (awkward to implement) Output changes only once per clock period» No not allowed input» Timing issues» Level sensitive 8
Master-Slave Flip-Flop J S NAND m S NAND s K R SR m R SR s Two cascaded latches operating on opposite clock phases insures that the flip-flop is never transparent; i.e., a change occurring in the primary inputs is never reflected directly to the outputs. Eliminates oscillations when J = K =. Still level sensitive. Number of transistors:» NAND-based: 36» AOI-based: 8 9
D-Latch D-latch is obtained by modifying the clocked NOR-based SR latch circuit. The circuit has a single input D which is connected to S input, and D is also inverted and connected to R input. The applications of D-latch are primarily for temporary storage of data or as a delay element. D SR Latch If = n+ = D 3 If = n+ = n
D-Latch (Cont.) D-latch is a mux-based latch which can be represented as D D = + In = + In Negative latch (transparent when = ) Positive latch (transparent when = ) 3
D-Latch Implementation with Transmission Gates Transmission gate D-latch: Use switch-like properties of transmission gates D 3 Operation: For =, n+ =D and n+ =D. A bit is loaded. For =, n+ = n and n+ = n. Thus, a bit is stored. Note that Propagation delay to is less than delay to. What about changes in D relative to changes in? Setup time and Hold time relative to : Device counts for TG-based reduced from AOI/OAI» AOI-based: 4» TG-based: 8 (plus to invert clock)
D-Latch Implementation with Three-State D = D = Similar to the TG-based implementation, except as if connection between n and pfets in a driving inverter and input side of a driven transmission gate is served. Require addition of inverter at input first. VDD VDD VDD D 33
D-Latch Implementation with Three-State (Cont.) The first three-state inverter acts as the input switch. Accept the input signal when is high, the second three-state inverter is at its high impedance state, and = D. The first three-state inverter is inactive when the goes low, and the second three-state inverter completes the two-inverter loop, which preserves its state ( n+ = n ) VDD VDD VDD D 34
D-Latch Setup Time and Hold Time t setup D t hold t clock-to- 35 T setup : time before the negative- edge the D-input has to be stable» The setup time is the delay between the data input of the register and the storage element. As the data takes a finite time to travel to the storage point, the clock cannot be changed until the correct data value appears. T hold : time after the negative- edge D-input has to remain stable» The hold time relates to the delay between the clock input to the register and the storage element. That is, the data has to be held for this period while the clock travels to the point of storage. T clock-to- : Delay from the negative- edge to new value of output
Edge Triggered Master-Slave Operation Negative D-Latch D = D = D Positive D-Latch D = D = D 36
Positive Edge Triggered Master-Slave Flip-Flop Master Slave m m s s D For =. =: Master m tracks current D; D m s Slave s =previous D sample. = : Master stores m = D(new D sample). For = D m s 3. =:Master passes m = D to Slave output s 4. = : Slave locks in new D, and Master m begins tracking D. 37
DFF Transient Response 38
DFF Transient Response with Setup Time Violation 39
D Flip-Flop Clock Skew Issues In a TG or three-state implemented flip-flop, if and changes are skewed (misaligned) enough, then a change in Master can immediately propagate into Slave violating the master-slave (edgetriggered) concept. If global or shared drivers used, can use the following to reduce skew: IN Adjust devices sizes to match inverter delay For the global case, skew can also arise due to interconnect delay. 4
Non-Bistable Sequential Schmitt Trigger The Schmitt trigger has an inverter-like voltage transfer characteristic, but with two different threshold voltages for increasing and decreasing input signals. In Out V out V OH VTC with hysteresis V OL Restores signal slopes (positive feedback) V M V M+ V in 4
Schmitt Trigger Application Noise Suppression 4 Digital Integrated Circuits nd
Schmitt Trigger The Circuit() V DD M M 4 V in X V out M M 3 Moves switching threshold of the first inverter 43
Schmitt Trigger Simulated VTC k M /(k M +k M4 ).5.5...5 V M.5 V X(V)..5 V M V x (V)..5 k = k = k = 3 k = 4 44...5..5..5 V in (V) Voltage-transfer characteristics with hysteresis. (k M +k M3 )/k M...5..5..5 V in (V) The effect of varying the ratio of the PMOS devicem 4. The width is k*.5 m. m Digital Integrated Circuits nd
Schmitt Trigger The Circuit() V DD M 4 M 3 M 6 In Out M X M 5 V DD M 45 Digital Integrated Circuits nd
Multivibrator Circuits R S Bistable Multivibrator flip-flop, Schmitt Trigger T Monostable Multivibrator one-shot Astable Multivibrator oscillator Digital Integrated Circuits nd 46
Transition-Triggered Monostable In DELAY t d Out t d Digital Integrated Circuits nd 47
Astable Multivibrators (Oscillators) N- Ring Oscillator simulated response of 5-stage oscillator Digital Integrated Circuits nd 48