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FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption : = 3.0V C-grade: 29mA (@55ns) operating current I -grade: 30mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade: 25mA (@70ns) operating current 0.45uA (Typ.) CMOS standby current = 5.0V C-grade: 6mA (@55ns) operating current I -grade: 70mA (@55ns) operating current C-grade: 5mA (@70ns) operating current I -grade: 60mA (@70ns) operating current 2.0uA (Typ.) CMOS standby current High speed access time : -55 55ns -70 70ns Automatic power down when chip is deselected Fully static operation PRODUCT FAMILY Very Low Power/Voltage CMOS SRAM 512K X bit Data retention supply voltage as low as 1.5V Easy expansion with and OE options Three state outputs and TTL compatible DESCRIPTION The is a high performance, very low power CMOS Static Random Access Memory organized as 524,2 words by bits and operates from a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 0.45uA at 3.0V/25 o C and maximum access time of 55ns at 3.0V/5 o C. Easy memory expansion is provided by an active LOW chip enable (), and active LOW output enable (OE) and three-state output drivers. The has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The is available in the JEDEC standard 32L SOP, TSOP, PDIP, TSOP II and STSOP package. PRODUCT FAMILY OPERATING TEMPERATURE RANGE POWER DISSIPATION SPEED ( ns ) STANDBY Operating PKG ( I CCSB1, Max ) ( I CC, Max ) 55ns :3.0~5.5V TYPE = 3.0V = 3.0V =5.0V 70ns :2.7~5.5V =5.0V 70ns 70ns TC TSOP- 32 STC STSOP-32 SC +0 O C to +70 O C 2.4V ~ 5.5V 55 / 70 5uA 30uA 24mA 5mA SOP -32 EC TSOP2-32 PC PDIP -32 TI TSOP-32 STI STSOP-32 SI -40 O C to +5 O C 2.4V ~ 5.5V 55 / 70 10uA 60uA 25mA 60mA SOP - 32 EI TSOP2-32 PI PDIP - 32 PIN CONFIGURATIONS BLOCK DIAGRAM A11 A9 A A13 WE A17 A15 VCC A1 A16 A14 A12 A7 A6 A5 A4 A1 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. 1 32 2 31 3 30 4 29 5 2 6 27 7 26 SC 25 9 SI 24 10 EC 23 EI 11 PC 22 12 PI 21 13 20 14 19 15 1 16 17 TC STC TI STI VCC A15 A17 WE A13 A A9 A11 OE A10 DQ7 DQ6 DQ5 DQ4 DQ3 32 31 30 29 2 27 26 25 24 23 22 21 20 19 1 17 OE A10 DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 A0 A1 A2 A3 1 A13 A17 A15 A1 A16 A14 A12 A7 A6 A5 A4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE OE Vdd GND Address Input Buffer Control 22 Row Decoder Data Input Buffer Data Output Buffer 204 Memory Array 204 X 204 204 Column I/O Write Driver Sense Amp 256 Column Decoder 16 Address Input Buffer A11 A9 A A3 A2 A1 A0 A10

PIN DESCRIPTIONS Name A0-A1 Address Input Function These 19 address inputs select one of the 524,2 x -bit words in the RAM Chip Enable Input WE Write Enable Input OE Output Enable Input DQ0-DQ7 Data Input/Output Ports is active LOW. Chip enables must be active when data read from or write to the device. if chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when OE is inactive. These bi-directional ports are used to read data from or write data into the RAM. Power Supply GND Ground TRUTH TABLE MODE WE OE I/O OPERATION CURRENT Not selected X H X High Z I CCSB, I CCSB1 Output Disabled H L H High Z I CC Read H L L DOUT I CC Write L L X DIN I CC ABSOLUTE MAXIMUM RATINGS (1) SYMBOL PARAMETER RATING UNITS VTERM Terminal Voltage with Respect to GND -0.5 to +0.5 TBIAS Temperature Under Bias -40 to +5 TSTG Storage Temperature -60 to +150 PT Power Dissipation 1.0 W IOUT DC Output Current 20 ma 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. V O C O C OPERATING RANGE RANGE AMBIENT TEMPERATURE CAPACITAN (1) (TA = 25 o C, f = 1.0 MHz) SYMBOL PARAMETER CONDITIONS MAX. UNIT CIN Input VIN=0V 6 pf Capacitance CDQ Input/Output Capacitance VI/O=0V pf 1. This parameter is guaranteed and not 100% tested. Commercial 0 O C to +70 O C 2.4V ~ 5.5V Industrial -40 O C to +5 O C 2.4V ~ 5.5V 2

DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 5 o C ) PARAMETER NAME VIL VIH 1. Typical characteristics are at TA = 25 o C. 2. Fmax = 1/t RC. 3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. IccSB1_MAX. is 5uA/30uA at =3.0V/5.0V and TA=70 o C. 5. Icc_MAX. is 30mA(@3.0V)/70mA(@5.0V) under 55ns operation. DATA RETENTION CHARACTERISTICS ( TA = -40 to + 5 o C ) SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS V DR PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Guaranteed Input Low = 3.0 V 0. Voltage (3) -0.5 -- V = 5.0 V 0. Guaranteed Input High = 3.0 V 2.0 Voltage (3) -- +0.3 V = 5.0 V 2.2 IIL Input Leakage Current = Max, VIN = 0V to -- -- 1 ua = Max, = VIH, or OE = VIH, ILO Output Leakage Current -- -- 1 ua VI/O = 0V to = 3.0 V 0.4 VOL Output Low Voltage = Max, IOL = 2.0mA = 5.0 V -- -- 0.4 V VOH Output High Voltage = Min, I OH = -1.0mA = 3.0 V 2.4 -- -- V = 5.0 V 2.4 ICC Operating Power Supply = VIL, IDQ = 0mA, 70ns = 3.0 V 25 -- -- ma Current F=Fmax (2) 70ns = 5.0 V 60 = 3.0 V 0.5 ICCSB Standby Current-TTL = VIH, IDQ = 0mA -- -- ma = 5.0 V 1.0 (4) ICCSB1 Standby Current-CMOS for Data Retention -0.2V, VIN - 0.2V or VIN 0.2V - 0.2V VIN - 0.2V or VIN 0.2V = 3.0 V = 5.0 V -- 0.45 2.0 10 60 1.5 -- -- V ua I CCDR Data Retention Current - 0.2V VIN - 0.2V or VIN 0.2V -- 0.3 1.3 ua t CDR t R Chip Deselect to Data Retention Time Operation Recovery Time See Retention Waveform 0 -- -- ns T RC (2) -- -- ns 1. = 1.5V, T A = + 25 O C 2. t RC = Read Cycle Time 3. IccDR_MAX. is 0.uA at TA=70 O C. LOW V CC DATA RETENTION WAVEFORM ( Controlled ) Data Retention Mode VDR 1.5V t CDR t R VIH - 0.2V VIH 3

AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels / 0V KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Input Rise and Fall Times 1V/ns MUST BE STEADY MUST BE STEADY Input and Output Timing Reference Level Output Load 0.5 C L = 30pF+1TTL C L = 100pF+1TTL MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H, DON T CARE: ANY CHANGE PERMITTED WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOWN DOES NOT APPLY NTER LINE IS HIGH IMPEDAN OFF STATE AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 5 o C ) READ CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION CYCLE TIME : 55ns ( = 3.0~5.5V) MIN. TYP. MAX. CYCLE TIME : 70ns ( = 2.7~5.5V) MIN. TYP. MAX. t AVAX t RC Read Cycle Time 55 -- -- 70 -- -- ns t AVQV t AA Address Access Time -- -- 55 -- -- 70 ns t ELQV t ACS Chip Select Access Time -- -- 55 -- -- 70 ns t GLQV t OE Output Enable to Output Valid -- -- 30 -- -- 35 ns t ELQX t CLZ Chip Select to Output Low Z 10 -- -- 10 -- -- ns t GLQX t OLZ Output Enable to Output in Low Z 10 -- -- 10 -- -- ns t EHQZ t CHZ Chip Deselect to Output in High Z -- -- 30 -- -- 35 ns t GHQZ t OHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns t AXOX t OH Data Hold from Address Change 10 -- -- 10 -- -- ns UNIT SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) t RC ADDRESS t OH t AA t OH D OUT 4

READ CYCLE2 (1,3,4) t ACS t CLZ t CHZ D OUT READ CYCLE3 (1,4) t RC ADDRESS t AA OE t OE t OH t CLZ t ACS t OLZ t OHZ t (1,5) CHZ D OUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when = VIL. 3. Address valid prior to or coincident with transition low. 4. OE = VIL. 5. The parameter is guaranteed but not 100% tested. 5

AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 5 o C ) WRITE CYCLE JEDEC PARAMETER NAME PARAMETER NAME DESCRIPTION CYCLE TIME : 55ns ( = 3.0~5.5V) MIN. TYP. MAX. CYCLE TIME : 70ns ( = 2.7~5.5V) MIN. TYP. MAX. t AVAX t WC Write Cycle Time 55 -- -- 70 -- -- ns t E1LWH t CW Chip Select to End of Write 55 -- -- 70 -- -- ns t AVWL t AS Address Set up Time 0 -- -- 0 -- -- ns t AVWH t AW Address Valid to End of Write 55 -- -- 70 -- -- ns t WLWH t WP Write Pulse Width 30 -- -- 35 -- -- ns t WHAX t WR Write Recovery Time (, WE) 0 -- -- 0 -- -- ns t WLOZ t WHZ Write to Output in High Z -- -- 25 -- -- 30 ns t DVWH t DW Data to Write Time Overlap 25 -- -- 30 -- -- ns t WHDX t DH Data Hold from Write Time 0 -- -- 0 -- -- ns t GHOZ t OHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns t WHQX t OW End ot Write to Output Active 5 -- -- 5 -- -- ns UNIT SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE1 (1) t WC ADDRESS (3) t WR OE (11) t CW t AW WE t AS (4,10) t OHZ t WP (2) D OUT t DH t DW D IN 6

WRITE CYCLE2 (1,6) t WC ADDRESS (11) t CW t AW WE t AS (4,10) t WHZ t WP (2) t OW (7) () D OUT t DW t DH (,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of or WE going high at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL ). 7. DOUT is the same phase of write data of this write cycle.. DOUT is the read data of next address. 9. If is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of going low to the end of write. 7

ORDERING INFORMATION X X Z Y Y SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green P: Pb free GRADE C: +0 o C ~ +70 o C I: -40 o C ~ +5 o C PACKAGE S: SOP E: TSOP 2 ST: Small TSOP T: TSOP P: PDIP Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS WITH PLATING b c c1 BASE METAL b1 SECTION A-A SOP -32

TSOP2-32 TSOP - 32 9

PACKAGE DIMENSIONS (continued) STSOP - 32 PDIP - 32 10