Low Cost JFET Input Operational Amplifiers ADTL/ADTL FEATURES TL/TL compatible Low input bias current: pa maximum Offset voltage 5.5 mv maximum (ADTLA/ADTLA) 9 mv maximum (ADTLJ/ADTLJ) ±5 V operation Low noise: nv/ Hz Wide bandwidth: 5 MHz Slew rate: V/μs CMRR: db minimum Total harmonic distortion:.% Supply current:. ma typical Unity-gain stable APPLICATIONS General-purpose amplification Power control and monitoring Active filters Industrial/process control Data acquisition Sample and hold circuits Integrators Input buffering GENERAL DESCRIPTION The ADTL and ADTL are JFET input amplifiers that provide industry-leading performance over TLx devices. The ADTLA and ADTLA are improved versions of TLx A, I, and Q grades. The ADTLJ and ADTLJ are industry alternatives to the TLx standard and C grades. The ADTLx family offers lower noise, offset voltage, offset drift over temperature, and bias current over the TLx. In addition, the ADLTx family has better common-mode rejection and slew rates. These op amps are ideal for various applications, including process control, industrial and instrumentation equipment, PIN CONFIGURATIONS OUT A IN A +IN A 3 V ADTLJ TOP VIEW (Not to Scale) +V 7 OUT B IN B 5 +IN B Figure. -Lead SOIC_N (R-) OUT A IN A +IN A 3 V ADTLA TOP VIEW (Not to Scale) +V 7 OUT B IN B 5 +IN B Figure. -Lead MSOP (RM-) OUT A OUT D IN A 3 IN D +IN A 3 ADTLJ +IN D +V TOP VIEW V +IN B 5 (Not to Scale) +IN C IN B 9 IN C OUT B 7 OUT C Figure 3. -Lead SOIC_N (R-) OUT A OUT D IN A +IN A +V +IN B IN B OUT B 3 5 7 ADTLA TOP VIEW (Not to Scale) 3 9 IN D +IN D V +IN C IN C OUT C Figure. -Lead TSSOP (RU-) active filtering, data conversion, buffering, and power control and monitoring. The A grade amplifiers are available in lead-free packaging. The standard grade amplifiers are available in both leaded and leadfree packaging. The ADTLA and ADTLA are specified over the extended industrial ( C to +5 C) temperature range. The ADTLJ and ADTLJ are specified over the commercial ( C to 7 C) temperature range. 75-75- 75-3 75- Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9, Norwood, MA -9, U.S.A. Tel: 7.39.7 www.analog.com Fax: 7..33 7 Analog Devices, Inc. All rights reserved.
ADTL/ADTL TABLE OF CONTENTS Features... Applications... Pin Configurations... General Description... Revision History... Specifications... 3 Absolute Maximum Ratings... Thermal Resistance... Power Sequencing... ESD Caution... Typical Performance Characteristics...5 Outline Dimensions... Ordering Guide... REVISION HISTORY /7 Rev. A to Rev. B Changes to Ordering Guide... /7 Rev. to Rev. A Changes to Table... 3 /7 Revision : Initial Version Rev. B Page of
ADTL/ADTL SPECIFICATIONS VCC = ±5 V, VCM = V, TA = 5 C, over all grades, unless otherwise noted. Table. J Grade A Grade Parameter Symbol Conditions Min Typ Max Min Typ Max Unit INPUT CHARACTERISTICS Offset Voltage VOS 9.5 5.5 mv C TA +7 C mv C TA +5 C 9 mv Offset Voltage Drift ΔVOS/ΔT C TA +7 C 5 μv/ C C TA +5 C μv/ C Input Bias Current IB pa C TA +7 C 3 3 na C TA +5 C 5 na Input Offset Current IOS pa C TA 7 C 3 3 na C TA +5 C 5 na Input Voltage Range VCM +5 +5 V Common-Mode Rejection Ratio CMRR VCM = V to +5 V db Input Impedance RIN Ω Large Signal Voltage Gain AVO RL = kω, V/mV VO = V to + V C TA 7 C 9 9 V/mV C TA +5 C 5 V/mV OUTPUT CHARACTERISTICS Maximum Output Voltage Swing VO RL = kω ± ±3.5 ±3 ±3.5 V C TA +7 C ± ±3 V C TA +5 C ±3 V RL = kω ±.5 ±3.3 V C TA +7 C ± ± V C TA +5 C ± V Short-Circuit Output Current ISC ±7 ±7 ma POWER SUPPLY Power Supply Rejection Ratio PSRR VDD = V to 3 V db Supply Current per Amplifier ISY.... ma C TA +7 C.9.9 ma C TA +5 C. ma DYNAMIC PERFORMANCE Slew Rate SR V/μs Gain Bandwidth Product GBP 5 5 MHz Phase Margin φm 3 3 Degrees Total Harmonic Distortion THD VIN = V rms, f = khz,.. % AV = +, RL = kω Channel Separation CS f = khz db NOISE PERFORMANCE Voltage Noise Density en f = khz nv/ Hz Rev. B Page 3 of
ADTL/ADTL ABSOLUTE MAXIMUM RATINGS Table. Parameter Rating Supply Voltage ± V or +3 V Input Voltage ±V supply Differential Input Voltage ±V supply Output Short Circuit to GND Indefinite Storage Temperature Range 5 C to +5 C Operating Temperature Range C to +5 C Lead Temperature (Soldering sec) 3 C Junction Temperature 5 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 3. Thermal Resistance Package Type θja θjc Unit -Lead SOIC_N (R-) 5 3 C/W -Lead MSOP (RM-) 5 C/W -Lead SOIC_N (R-) 3 C/W -Lead TSSOP (RU-) 35 C/W POWER SEQUENCING The op amp supplies must be established simultaneously with, or before, the application of any input signals. If this is not possible, the input current must be limited to ma. ESD CAUTION Rev. B Page of
ADTL/ADTL TYPICAL PERFORMANCE CHARACTERISTICS V OM MAXIMUM PEAK OUTPUT VOLTAGE (±V) V SY = ±V V SY = ±5V R L = kω k k k M M FREQUENCY (Hz) Figure 5. Maximum Peak Output Voltage vs. Frequency 75-5 V OM MAXIMUM PEAK OUTPUT VOLTAGE (±V) R L = kω R L = kω 75 5 5 5 5 75 5 Figure. Maximum Peak Output Voltage vs. Free-Air Temperature 75- V OM MAXIMUM PEAK OUTPUT VOLTAGE (±V) V SY = ±V V SY = ±5V R L = kω V OM MAXIMUM PEAK OUTPUT VOLTAGE (±V) k k k M M FREQUENCY (Hz) 75- k R L LOAD RESISTANCE (Ω) k 75-9 Figure. Maximum Peak Output Voltage vs. Frequency Figure 9. Maximum Peak Output Voltage vs. Load Resistance V OM MAXIMUM PEAK OUTPUT VOLTAGE (±V) T A = 55 C T A = +5 C R L = kω T A = +5 C k k M M FREQUENCY (Hz) Figure 7. Maximum Peak Output Voltage vs. Frequency 75-7 V OM MAXIMUM PEAK OUTPUT VOLTAGE (±V) R L = Ω ± ±5 ± ±7 ± ±9 ± ± ± ±3 ± ±5 V SY SUPPLY VOLTAGE (V) Figure. Maximum Peak Output Voltage vs. Supply Voltage 75- Rev. B Page 5 of
ADTL/ADTL A VD LARGE SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION (V/mV) k V O = ±V R L = kω PD TOTAL POWER DISSIPATION (mw) NO SIGNAL NO LOAD 75 5 5 5 5 75 5 Figure. Large Signal Differential Voltage Amplification vs. Free-Air Temperature 75-75 5 5 5 5 75 5 Figure. Total Power Dissipation vs. Free-Air Temperature 75-. I SY SUPPLY CURRENT (ma)...... NO SIGNAL NO LOAD I B INPUT BIAS CURRENT (na) 3 75 5 5 5 5 75 5 Figure. Supply Current Per Amplifier vs. Free-Air Temperature 75-55 35 5 5 5 5 5 5 5 5 Figure 5. Input Bias Current vs. Free-Air Temperature 75-5 I SY SUPPLY CURRENT (ma)......... NO SIGNAL NO LOAD IB INPUT BIAS CURRENT (na)..... ± ±5 ± ±7 ± ±9 ± ± ± ±3 ± ±5 V SY SUPPLY VOLTAGE (V) Figure 3. Supply Current vs. Supply Voltage 75-3. 55 35 5 5 5 5 5 5 5 5 Figure. Input Bias Current vs. Free-Air Temperature 75- Rev. B Page of
ADTL/ADTL INPUT AND OUTPUT VOLTAGE (V) OUTPUT INPUT R L = kω C L = pf V N EQUIVALENT INPUT NOISE VOLTAGE (nv/ Hz) 9 7 5 3 A V = k TIME (µs) Figure 7. Large Signal Response 75-7 k k FREQUENCY (Hz) Figure. Voltage Noise Density vs. Frequency 75- V O OUTPUT VOLTAGE (V).5..5.5. R L = kω C L = pf THD TOTAL HARMONIC DISTORTION (%)... A V = Vi (rms) = V.5....... ELAPSED TIME (µs) Figure. Small Signal Response 75-. FREQUENCY (Hz) Figure. Total Harmonic Distortion vs. Frequency 75- CMRR COMMON MODE REJECTION RATIO (db) 95 9 93 9 9 9 9 55 35 5 5 5 5 5 5 5 5 Figure 9. Common-Mode Rejection Ratio vs. Free-Air Temperature 75-9 Rev. B Page 7 of
ADTL/ADTL OUTLINE DIMENSIONS 5. (.9). (.9). (.57) 3. (.97) 5. (.) 5. (.).5 (.9). (.) COPLANARITY. SEATING PLANE.7 (.5) BSC.75 (.).35 (.53).5 (.).3 (.).5 (.9).7 (.7).5 (.9).5 (.99).7 (.5). (.57) 5 COMPLIANT TO JEDEC STANDARDS MS--AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. -Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-) Dimensions shown in millimeters and (inches) 7-A 3. 3.. 3. 3.. 5 5.5.9.5.95.5.75.5. PIN.5 BSC.3. COPLANARITY.. MAX SEATING PLANE.3.... COMPLIANT TO JEDEC STANDARDS MO-7-AA Figure 3. -Lead Mini Small Outline Package [MSOP] (RM-) Dimensions shown in millimeters Rev. B Page of
ADTL/ADTL.75 (.35).55 (.33). (.575) 3. (.9) 7. (.) 5. (.3).5 (.9). (.39) COPLANARITY..7 (.5) BSC.5 (.).3 (.).75 (.9).35 (.53) SEATING PLANE.5 (.9).7 (.7).5 (.97).5 (.9).7 (.5). (.57) 5 COMPLIANT TO JEDEC STANDARDS MS--AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure. -Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-) Dimensions shown in millimeters and (inches) -A 5. 5..9.5..3. BSC 7.5.. PIN.5.5.5 BSC.3.9. MAX SEATING PLANE..9 COPLANARITY. COMPLIANT TO JEDEC STANDARDS MO-53-AB- Figure 5. -Lead Thin Shrink Small Outline Package [TSSOP] (RU-) Dimensions shown in millimeters.75..5 Rev. B Page 9 of
ADTL/ADTL ORDERING GUIDE Model Temperature Range Package Description Package Option Branding ADTLJR C to +7 C -Lead SOIC_N R- ADTLJR-REEL C to +7 C -Lead SOIC_N R- ADTLJR-REEL7 C to +7 C -Lead SOIC_N R- ADTLJRZ C to +7 C -Lead SOIC_N R- ADTLJRZ-REEL C to +7 C -Lead SOIC_N R- ADTLJRZ-REEL7 C to +7 C -Lead SOIC_N R- ADTLARZ C to +5 C -Lead SOIC_N R- ADTLARZ-REEL C to +5 C -Lead SOIC_N R- ADTLARZ-REEL7 C to +5 C -Lead SOIC_N R- ADTLARMZ-R C to +5 C -Lead MSOP RM- A ADTLARMZ-REEL C to +5 C -Lead MSOP RM- A ADTLJR C to +7 C -Lead SOIC_N R- ADTLJR-REEL C to +7 C -Lead SOIC_N R- ADTLJR-REEL7 C to +7 C -Lead SOIC_N R- ADTLJRZ C to +7 C -Lead SOIC_N R- ADTLJRZ-REEL C to +7 C -Lead SOIC_N R- ADTLJRZ-REEL7 C to +7 C -Lead SOIC_N R- ADTLARZ C to +5 C -Lead SOIC_N R- ADTLARZ-REEL C to +5 C -Lead SOIC_N R- ADTLARZ-REEL7 C to +5 C -Lead SOIC_N R- ADTLARUZ C to +5 C -lead TSSOP RU- ADTLARUZ-REEL C to +5 C -lead TSSOP RU- Z = RoHS Compliant Part. Rev. B Page of
ADTL/ADTL NOTES Rev. B Page of
ADTL/ADTL NOTES 7 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D75--/7(B) Rev. B Page of
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