EFFICIENT DESIGN AND IMPLEMENTATION OF ADDERS WITH REVERSIBLE LOGIC

EFFICIENT DESIGN AND IMPLEMENTATION OF ADDERS WITH REVERSIBLE LOGIC Manoj Kumar K 1, Subhash S 2, Mahesh B Neelagar 3 1,2 PG Scholar, 3 Assistant Professor, Dept of PG studies, VTU-Belagavi, Karnataka (India) ABSTRACT The addition of two binary numbers is the important and most frequently used arithmetic process on microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits (ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits. The Reversible Logic has received great attention in the past recent years due to its ability in reducing the power dissipation, the major concern in digital designing is low power dissipation. To generate a useful gate function the Reversible Gates require constant inputs, called Ancillary Inputs, and some additional unused outputs, called Garbage Outputs, in order to maintain the reversibility of the digital circuits. In today era, reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we have proposed a design and implementation of the four adder topologies using reversible logic gates new method to reduce quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx 14.7 and implemented in Spartan 6 FPGA. Keywords: Reversible Logic, Quantum cost, Garbage output, Xilinx ISE 14.7 I. INTRODUCTION Normal Combinational Logic Circuits dissipate heat for every bit of information lost during their operation. Due to this, the recovery of a piece of information once lost is completely impossible. However, if the same circuit is constructed using the Reversible Logic Gates, not only is the recovery possible but also the dissipation of heat reduced. [1]In the 1960s, R. Landauer demonstrated that even with high technology systems when designed using Irreversible hardware result in high energy dissipation and efficiency loss. He showed that the loss per bit of information exchange dissipates KT.ln2 Joules of energy where K is Boltzmann Constant and T the Absolute Temperature at which the operation is performed. [2]Later in 1973, Bennett showed that this amount of energy loss can be overcome if the circuit is designed using the Reversible Logic technique. With the number of chip components doubling every 18 months, as per Moore s Law, the Irreversible Technologies would dissipate a lot of heat and reduce circuit life. It is here the Reversible Logic comes into action in not only recovering the lost information but also dissipating less heat. A Reversible Logic Gate is an n-input, n-output device with n-to-n Mapping, which helps determining the outputs from the inputs and vice versa. Wherever necessary, extra outputs can be added to make the output count equal to that of the input. The main challenges are diminishing Number of Gates, Memory Usage, Delay and Quantum Cost. 124 P a g e

II. REVERSIBLE LOGIC Reversible logic is a successful computing design pattern which presents a method to construct a computer with no heat generation. Reversible Logic Gate is an n-input, n-output device that provides n-to-n Mapping between input and output, which helps determining the outputs from the inputs and vice versa. The input that is added to an NXN function to make it reversible is called constant input (CI). Garbage outputs (GO) are the outputs of the reversible circuit that do not contribute to reversible logic realization. Any output that will not take part in the realization of circuit in which the gate used will be considered as garbage outputs. Quantum cost (QC) refers to the cost of the circuit in terms of the cost of a primitive gate. This can be computed knowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit. These parameters have to be reduced while designing a reversible circuit. Some of the major constraint of the reversible logic synthesis are that do not allow fan-out s, and also feedback from gate outputs to inputs is not allowed. A reversible circuit should have minimum number of reversible logic gates. Wherever required, extra outputs can be added to make the output count equal to input. The main challenges are reduction in Number of Gates, Memory Usage, Delay and Quantum Cost. The basic reversible logic gates encountered during the design are listed below: 2.1 HNG Gate [13] It is a 4x4 gate and its logic circuit is as shown in the figure1. It has quantum cost six. It is used for designing adders like ripple carry adder. It reduces the garbage and gate counts by producing the sum and carry in the same gate. 2.2 Toffoli Gate [12] It is a 3x3 gate and its logic circuit is as shown in the figure1. It has quantum cost two. It is used to realize various Boolean functions such as XOR, AND. 2.3 Peres Gate [11] It is a 3x3 gate and its logic circuit is as shown in the figure1. It has quantum cost four. It is used to realize various Boolean functions such as XOR, AND. 2.4 Fredkin Gate [12] It is a 3x3 gate and its logic circuit is as shown in the figure1. It has quantum cost five. It can be used to implement a Multiplexer. 2.5 TSG Gate [14] It is a 4x4 gate and its logic circuit is shown in figure1. It can be used to implement adders like carry skip adder and carry bypass adder. Quantum cost is not specified by the author so it is unknown. 125 P a g e

Fig.1. Dfferent Reversible Gates The important design constraints of the reversible logic circuits are 1. Reversible logic circuit should have minimum quantum cost. 2. The design can be optimized so as to produce minimum number of garbage outputs. 3. The reversible logic circuits must use minimum number of constant inputs. 4. The reversible logic circuits must use minimum number of reversible gates. III. ADDER TOPOLOGIES This section presents the design of adder topology. In this work the following adder structures are used: Ripple Carry Adder Carry Save Add Carry Skip Adder Carry Bypass Adder 3.1 Ripple Carry Adder The ripple carry adder is constructed by cascading full adders (FA) blocks in series. Single full adder is responsible for the addition of two binary digits at any stage of the ripple carry adder. The carryout of one stage is fed directly to the carry-in of the proceeding stage. Even though this is a simple adder and can be used to add unrestricted bit length numbers, it is however not very efficient when large bit numbers are used. One of the most 126 P a g e

severe drawbacks of this adder is that the delay increases linearly with the bit length. The conventional 8 bit ripple carry adder is shown in the figure2. In reversible ripple carry adder all the full adders are replaced by HNG gate. Reversible 8 bit ripple carry adder s shown in figure3. The quantum cost is 48, constant input (CI) s 8, garbage output (GO)is 16 and number of gates(no) is 8. Fig.2. Conventional 8-Bit Ripple Carry Adder Fig.3. 8-Bit Ripple Carry Adder Using Reversible Logic 3.2 Carry Skip Adder A carry-skip adder consists of a simple ripple carry-adder with a special speed up carry chain called a skip chain. Carry skip adder is better in speed compared to ripple carry adder when addition of large number of bits take place. Carry skip adder has provides a good compromise in delay, along with a simple and regular layout. This chain defines the distribution of ripple carry blocks, which forms the skip adder. A carry-skip adder is designed to speed up a wide adder by aiding the propagation of a carry bit around a portion of the entire adder. The conventional 8 bit carry skip adder is shown in the figure4. in reversible carry skip adder all the full adders are replaced by TSG gate, AND gates are replaced with Peres Gates and OR gates are replaced with FRG gates. Reversible 8 bit carry skip adder is shown in figure5. the constant input(ci) is 14,garbage output(go)is 24 and number of gates(ng) is 16. Fig.4. Conventional 8-Bit Carry Skip Adder 127 P a g e

Fig.5. 8-Bit Reversible Carry Skip Adder 3.3 Carry Save Adder The carry-save adder reduces the addition of 3 numbers to the addition of 2 numbers. The propagation delay is 3 gates regardless of the number of bits. The carry-save unit comprises of n full adders, each of which computes a single sum and carries bit based solely on the corresponding bits of the three input numbers. The entire sum can then be computed by shifting the carry sequence left by one place and appending a 0 to the front (most significant bit) of the partial sum sequence and adding this sequence with RCA produces the resulting n + 1-bit value. This procedure can be continued indefinitely, adding an input for each level of full adders, without any intermediate carry propagation. These stages can be arranged in a binary tree structure, with cumulative delay logarithmic in the number of inputs to be added, and invariant of the number of bits per input. The conventional 8 bit carry save adder is shown in the figure6. in reversible carry save adder all the full adders are replaced by HNG gate and all the half adders are replaced with the. Reversible 8 bit carry save adder is shown in figure7. The quantum cost is 78, constant input(ci) s 16,garbage output(go)is 23 and number of gates(ng) is 16. Fig.6. Conventional 8-Bit Carry Save Adder Fig.7. 8-Bit Reversible Carry Save Adder 128 P a g e

3.4 Carry Bypass Adder As in a ripple-carry adder, every full adder cell has to wait for the incoming carry before an outgoing carry can be generated. This dependency can be eliminated by introducing an additional bypass (skip) to speed up the operation of the adder. An incoming carry Ci,0=1 propagates through complete adder chain and causes an outgoing carry C0,7=1 under the conditions that all propagation signals are 1. This information can be used to speed up the operation of the adder, as shown in Figure8. When BP = P0P1P3P4P5P6P7P8 = 1, the incoming carry is forwarded immediately to the next block through the bypass and if it is not the case, the carry is obtained via the normal route. If (P0P1P3P4P5P6P7 = 1) then C0,7 = Ci,0 else either Delete or Generate occurred. Hence, in a CBA the full adders are divided into groups, each of them is bypassed by a multiplexer if its full adders are all in propagate. The conventional 8 bit carry bypass adder is shown in the figure8. in reversible ripple carry adder all the full adders are replaced by TSG gate,and gates are replaced with Peres Gate and mux s replaced with Fredkin Gate. Reversible 8 bit carry bypass adder s shown in figure9.the constant input(ci) is12,garbage output(go)is 24 and number of gates(ng) is 16. Fig.8. Conventional 8-Bit Carry Bypass Adder Fig.9. 8-Bit Reversible Carry Bypass Adder IV. RESULT, SIMULATION AND COMPARISON The designs of all the four reversible adders are logically verified using XLINX 14.7 in verilog. The simulation results are shown in figures10, 11, 12 and 13 respectively. The table1 shows the comparison all the four reversible adders in terms of quantum cost (QC), constant inputs (CI), garbage outputs (GO) and number of gates(ng). 129 P a g e

Table 1. Comparison of Reversible Adders ADDERS QC CI GO NG RCA 48 8 16 8 CSkA --- 14 24 16 CSaA 78 16 23 16 CByA --- 15 24 16 Fig.10. Simulation Result of Ripple Carry Adder Fig.11. Simulation Result of Carry Skip Adder Fig.12. Simulation Result of Carry Save Adder Fig.13. Simulation Result of Carry Bypass adder V.CONCLUSION This paper presents implementation of four different adder topologies using reversible logic gates. In reversible logic gates there is no information loss so the heat generation also zero. So by using reversible logic gate we can reduce the power dissipation. The proposed design has minimum number of garbage output, minimum number of constant input, minimum number of quantum cost and minimum number of gates. 130 P a g e

REFERENCE [1] Landauer,"Irreversibility and Heat Generation in the computational Process", IBM Journal of Research and Development, 5, pp.183-191, 1961. [2] C.H. Bennett, "Logical reversibility of Computation", IBM J. Research and Development, pp.525-532, November 1973 [3] Divyansh Mathur, Arti Saxena, Abneesh Saxena Arithmetic and Logic Unit Designing Using Reversible Logic Gate International Journal of Recent Technology and Engineering (IJRTE) ISSN: 2277-3878, Volume-1, Issue- 6, January 2013 [4] H. Thapliyal and M.B. Srinivas, "Novel Reversible multiplier Architecture Using Reversible TSG Gate",Proc. IEEE International Conference on Computer Systems and Applications, pp. 100-103, March 2006. [5] Nidhi, Gurinderpal Singh Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low QuantumCost and Low Power Consumption Nidhi Int. Journal of Engineering Research and Applications www.ijera.com ISSN : 2248-9622, Vol. 4, Issue 7( Version 3), July 2014, pp.247-251 [6] Praveena Murugesan and Thanushkodi Keppanagounder, Design of Optimal Carry Skip Adder and Carry Skip BCD Adder using Reversible Logic Gates, Journal of Computer Science 10 (5), 2014, pp 723-728. [7] T. Himanshu and M. B. Srinivas, "A new reversible TSG gate and its application for designing efficient adder circuits." ArXiv preprint cs/0603091," 2006. [8] R.UMA,Vidya Vijayan, M. Mohanapriya, Sharon Paul Area, Delay and Power Comparison of Adder Topologies International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012 [9] Manoj Kumar.K, Dr Meghana Kulkarni Implementation of high speed low power vedic multiplier using reversible logic International Journal of Advance Research In Science And Engineering http IJARSE, Vol. No.4, Issue 03, March 2015 [10] Robert Wille, Rolf Drechsler, Towards a Design Flow for Reversible Logic, Springer, 2010. [11] A. Peres, Reversible logic and quantum computers, Phys.Rev. A 32 (1985) 3266-3276. [12] E. Fredkin and T. Toffoli,"Conservative Logic", Int'l 1Theoretical Physics Vo121, pp.219-253, 1982. [13] Shams, M., M. Haghparast and K. Navi, Novel reversible multiplier circuit in nanotechnology.world Appl. Sci. J.,3(5): 806-810. [14] Himanshu Thapliyal and M.B. Srinivas A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures Center for VLSI and Embedded System Technologies,International Institute of Information Technology,Hyderabad-500019, India 131 P a g e