RPN Journal of Engneerng and ppled Scences 2006-2015 san Research Publshng Network (RPN). ll rghts reserved. COMPRISON OF VRIOUS RIPPLE CRRY DDERS: REVIEW Jmn Cheon School of Electronc Engneerng, Kumoh Natonal Insttute of Technology, 61 Daehak-ro, Gum, Korea E-Mal: jmn.cheon@kumoh.ac.kr BSTRCT s portable multmeda and communcatons applcatons emerge, the need for low power, small area, and low delay tme dgtal crcuts becomes more promnent. ddton process s the most used operaton n any DSP because addton s nvolved n all other mathematcal operatons. Therefore, adders desgn s consdered crtcal because t nfluences the performance of the system n terms of power and delay. In ths paper, we ntroduce varous rpple carry adder n terms of statc CMOS logc, dynamc CMOS logc, and others. Keywords: rpple carry adder, statc CMOS logc, dynamc CMOS logc, normal process complementary pass transstor logc (NPCPL). INTRODUCTION Low power, small area, and fast logc desgn became sgnfcant due to the spread of wreless communcaton and portable computng systems. dders construct a major block n any DSP snce all the arthmetc operatons (subtracton, multplcaton and dvson) rely on addton. There are many knds of adder structure, but rpple carry adder (RC) s the most low power, and small area desgn among them. However, even f same RC, there are lots of desgn logcs whch have dfferent performances. In ths paper, we analyze varous RC n terms of statc CMOS logc, dynamc CMOS logc, and others. Ths paper organzed as follows. Secton II ntroduces operaton and characterstc of smple basc RC. Secton III descrbes varous knd of the RC n terms of statc CMOS logc, dynamc CMOS logc, and others and also compares and analyzes performance of each RC. Secton IV concludes the paper. BSIC NLYSIS OF RC Basc unt of RC The basc unt of a RC s a full adder (F). n F adds two bnary numbers wth a carry-n. The Structure representaton of the conventonal CMOS F appears n Fgure-1. There are a total of three nputs for the F, two for the nput numbers and B, and one for the carry-n, C n. The outputs are the Sum and carry-out C out [1]. The logc functons correspondng to termnals Sum and C out are as follows: Basc theory and operaton The basc unt of a RC s an F. It can be extended ndefntely to any number by connectng the carry -out of the prevous 1-bt F to the carry-n of the next 1- bt F. n n-bt RC consstng of n sngle-bt Fs s descrbed n Fgure-2. The fgure clearly shows that the carry bt rpples through the chan of the cascaded Fs, from a lower bt to the next hgher order F [2, 3]. B C n Fgure-1. Structure of an F. 0 B0 n-1 Bn-1 Full dder Full dder... Full dder Sum C out Cn = C1 C2 Cn S 0 S 1 S n-1 Fgure-2. Structure of an RC. Table-1. Comparson between dfferent adders [3]. Sum B (1) C n C out ( B) C B (2) n 10530
RPN Journal of Engneerng and ppled Scences 2006-2015 san Research Publshng Network (RPN). ll rghts reserved. Comparson between dfferent type adders In order to compare the performance of the dfferent adders, a 16 bt adder was used as a test vehcle for each type n [3]. The desgns are mplemented usng standard CMOS cells n 0.5-μm technology. ll the desgns are optmzed for power-delay product. Table 1 shows the comparson results between the RC, carry look ahead adder (CL adder), condtonal sum adder, and carry skp adder n terms of power, delay and area. The comparson result shows that RC has the smallest power and area [3]. dvantage and dsadvantage RC occupes the smallest area and dsspates the lowest power. lso t offers good performance for random nput data [4]. In ths case, average energy consumed by the B Sum C out Fgure-3. Transmsson functon full adder (TF). C n RC s E avg = O(W) where W s the word-length of the operands. For word-length W 16, the error n the theoretcal estmates s around 15% [5]. Nonetheless, ts delay characterstcs depend heavly on the length of the carry propagaton path, thus makng t a relatvely unfavorable choce for crcuts wth nonrandom nput operands. The worst case delay ncreases lnearly wth the length of the carry propagaton path, whch depends on the number of bts processed by the operands, n. lso, the area of the adder s proportonal to n [3]. Therefore, n stuatons when hgh speed performance s crucal and the mnmum amount of hardware s underperformng, usng an RC n the arthmetc operaton would be detrmental. VRIOUS KIND OF RCs Changng an F structure s necessary to mprove performance of an RC. There are lots of F structures, but t can classfy statc CMOS logc, dynamc CMOS logc, and others. Statc CMOS Logc The smple structure of conventonal F cell s based on statc CMOS logc. One F cells desgn usng a total of 32 transstors [6]. Therefore, the conventonal structure has not only large power but also long delay tme. F can be desgned to use multplexers and XORs. Whle ths s mpractcal n a complementary CMOS mplementaton, t becomes attractve when the multplexers and XORs are mplemented as transmsson gates [7]. B C n ~C out Sum Fgure-4. 10-transstor full adder (10-T F). Table-2. Comparson between the two F cells. Fgure-5. Delay tme versus power supply voltage. 10531
RPN Journal of Engneerng and ppled Scences 2006-2015 san Research Publshng Network (RPN). ll rghts reserved. Fgure-7. 1 bt dynamc F. Fgure-6. Power dsspaton versus power supply voltage. One of the Fs based on ths approach s shown n Fgure- 3, the transmsson functon F (TF). The TF conssts of 16 transstors and dsspates less power than conventonal CMOS Fs [8]. Ths structure has meanng of CMOS F desgned by transmsson functon theory. better performance of F structure s Fgure-4, the 10-transstor low power hgh speed F (10-T F) cell [9]. The crtcal path conssts of an XOR gate; an nverter and one pass transstor. In a n-bt adder crcut, the new adder cell wll gve alternate polarty for the carryout n the odd and even postons. The nverters n the structure of the 10-T F cell act as drvers. Therefore, each stage wll not suffer from degradaton n ts dervng capabltes. The saves power, area and tme. Table-2 shows 10-T F has much better performance than TF. Two prototypes of 32-bts rpple carry adder are constructed. One prototype uses a TF, whereas the other prototype, whch uses a 10-T F, s constructed wth a two-transstor nverter drver. Fgure 5 shows the delay tme and Fgure 6 shows power dsspaton of 32-bt RC of each prototype. t a power supply voltage of 2.8 V, the crtcal path delay tme for a 32-bt RC that uses the TF prototype s 7.2 ns, whle t s observed to be 4.1 ns for the 10-T F prototype, thereby exhbtng a speed mprovement of 44 percent over the former. Cleary, the 10-T F prototype outperforms the TF prototype throughout the entre operatng range. For the power consumpton consderaton, t s observed that the 10-T F prototype dsspates 2.1 mw, whch s 81 percent less than the 11 mw dsspated by the TF prototype. Both of the 32-bt RCs were smulated at a supply voltage of 2.8 V and a clock Fgure-8. 16 bt DRC usng DCVS logc. Fgure-9. DCVS DRC components (a) carry generate and propagate (GP) block (b) carry bypass (CB) block and (c) EXOR block. frequency of 125 MHz. It s clear that the 10-transstor prototype dsplays enhanced power dsspaton over the TF for the operatng range of 2.8 V to 5 V. It can operate satsfactorly at frequency up to 350 MHz at a supply voltage of 5 V. Ths means that large archtectures can be bult to operate at very hgh frequences wthout compromsng the small-area and low-power characterstcs, whch are the man crtera for today s evolvng technology. 10532
RPN Journal of Engneerng and ppled Scences 2006-2015 san Research Publshng Network (RPN). ll rghts reserved. Dynamc CMOS logc Dynamc logc s an alternatve logc style whch obtans a smlar result to statc logc, whle avodng statc power consumpton. Wth the addton of a clock nput, t uses a sequence of precharge and condtonal evaluaton phases [7]. Dynamc CMOS logc contans lower number of transstors and faster speed than statc CMOS logc. lso t only consumes dynamc power, but overall power dsspaton can be sgnfcantly hgher compared wth a statc logc gate. Therefore, usng dynamc logc can have mert of area, and delay tme than statc logc on specal condton. Fgure 7 shows 1-bt dynamc full adder. Fgure-8 shows the 16-bt dynamc RC (DRC) usng dfferental cascode swtch voltage (DCVS). DCVS logc s a dfferental logc style derved from domno logc made up of two complementary NMOS logc trees. Ths logc requres true and complementary nput sgnals to swtch the two outputs to dfferent logc states. In selftmed crcuts, ts dual-ral property can be used to generate completon sgnals for combnatonal logc n a general way [4]. The mathematcal formulaton of DCVS logc of DRC s gven below [10]. Let and B be the th bts of the nput data and C -1 the carry-n for stage. Then we have C G PC (3) 1 problems by ncludng 4 transstors. It has not only low delay tme but also small number of transstors than DCVS DRC. Fgure-11 s savng the area by replacng as many as PMOS transstor n NP CMOS DRC wth the NMOS transstors. The resultant structure s called ll-n DRC. Note than an nverter s requred between the carry logc and sum logc. Fgure-12 ntends to elmnate the need of negatve nputs. To acheve ths, however t s necessary to have a all-pmos composton of the sum logc. s wll be seen n smulaton results part, the all-pmos structure has made the desgn slowest among these several DRCs [10]. In order to mantan the advantage of postve nputs of the all-pmos logc (Fgure-12), t needs to replace the statc nverter of all-pmos logc wth a dynamc one (Fgure-13). The fast response tme of the dynamc nverter compensates the speed lost n the all- PMOS sum logc and makes the desgn the fastest among all the proposed DRCs. ~ S C B C P 1 1 (4) ~ P B (5) G B (6) ~ where P s the carry propagate sgnal and G s the carry generate sgnal. In adaptng (3) and (6) to dfferental logc, t s necessary to defne ther complements, whch are expressed as C B PC (7) 1 ~ S C 1 P (8) ~ Fgure-9 shows the each slce of 1-bt s made up of a carry generate and propagate block (GP) whch computes the sgnals P and P n parallel, a carry bypass block (CB), and an EXOR output stage. Ths structure has low delay tme but greatest power and area penalty. Fgure-10 shows DRC usng race-free NP CMOS logc [10]. Conventonal NP CMOS DRC has nherent race problems, but ths logc elmnates race ~ Fgure-10. Race-Free NP CMOS DRC. 10533
RPN Journal of Engneerng and ppled Scences 2006-2015 san Research Publshng Network (RPN). ll rghts reserved. ~ C n ~C n ~ S0 C n ~ ~ C 0 B 0 ~ C n B0 0 B0 B0 0 B0 B0 ~ ~B 0 ~Cn ~B 1 Cn ~ S0 ~ ~ 1 ~C1 C1 ~ ~ ~C 0 S 1 ~C1 ~ 1 B 1 B 1 C1 C 0 ~ 1 ~ S1 ~ ~ ~ ~ Next stage Fgure-11. ll-n (N) dynamc CMOS logc of DRC. Table-3 shows the transstor count, the total transstor wdth, the worst-case delay of 16-bt DRCs usng dfferent cells, as well as those of the statc RC (SRC). The power dsspaton s measured for each crcut wth the worst-case delay. The DCVS DRC, though much faster than the SRC, as the worst delay among all DRCs. Further, t has the greatest power and area penalty. The Fgure-13. Usng dynamc nverter n Fgure 12 s logc. Table-3. Features of varous 16-bt RC [10]. ~ C n 0 B0 B0 B 0 ~ C n ~ B0 Cn ~ S0 dynamc nverter (DI) DRC s the fastest among all RCs. It s 2.3 tmes faster than the SRC and 1.46 tmes faster than the DCVS DRC. The N DRC has the lowest power and area penalty among all DRCs. It s even smaller than the SRC. lthough t consumes more power than the SRC, ts power-delay product (PDP) s superor to that of the SRC [10]. ~C1 1 C 1 B 1 ~ S1 In1 In2 In3 In4 g1 g2 g3 g4 two stage Fgure-12. Prmary nput of DRC becomes postve logc. out ~out Fgure-14. New basc NPCPL cell. 10534
RPN Journal of Engneerng and ppled Scences 2006-2015 san Research Publshng Network (RPN). ll rghts reserved. CKNOWLEDGEMENT Ths paper was supported by Research Fund, Kumoh Natonal Insttute of Technology. REFERENCES [1] K. S. Yeo and K. Roy. 2005. Low-Voltage Low- Power VLSI Subsystems, Mc Graw Hll. Fgure-15. 1 bt F and 2 bts F usng NPCPL cell. Table-4. New nput combnaton. Others Wave ppelnng s a very effcent way to desgn hgh-throughput RC, but t requres accurate delay control. Hence, CMOS normal process complementary pass transstor logc (NPCPL) has been used n place of statc CMOS logc whch suffers delay varaton dependng on nput combnatons. The most mportant advantage of usng NPCPL s that all knds of gates can be mplemented wth the same basc structure, hence the delays of all knds of gates can be kept the same. However, conventonal NPCPL has two major problems for hgh speed wave ppelned desgn. One s the nsuffcent drvng capablty, and the other s the unbalanced loadng. In [11], new basc NPCPL cell solve the two problems of conventonal NPCPL cell. The load unbalancng problem has been solved by a new nput combnaton and the problem of nsuffcent drvng capablty has been overcome by a two-stage buffer. Table 4 shows new nput combnaton and Fgure 14 shows new basc NPCPL cell whch contans two stage buffers. In [11], expermental results obtaned from 16-bt RC usng new NPCPL cell n 0.8-μm technology shows 900 MHz throughput. CONCLUSIONS In ths paper, we analyze and compare varous RCs n terms of statc CMOS logc, dynamc CMOS logc, and others. s we analyzed above, statc CMOS logc can operate n low power dsspaton, whereas dynamc CMOS logc can operate much less delay tme. By usng NPCPL cell, 16-bt RC provdes throughput of 900MHz whch s the fastest among ntroduced RCs. [2] I. Koren. 1993. Computer rthmetc lgorthms, Englewood Clffs, New Jersey: Prentce Hall. [3] M. W. llam and M.I. Elmasry. 1998. Low-power mplementaton of fast addton algorthms. IEEE Canadan Conf. Electrcal and Computer Engneerng. pp. 645-647. [4] G.. Ruz. 1998. Evaluaton of three 32-bt CMOS adders n DCVS logc for self-tmed crcuts. IEEE J. Sold-State Crcuts. 13(4): 604-613. [5] L. Montalvo and K.K. Parh. 1996. Estmaton of verage Energy Consumpton of Rpple-Carry dder Based on verage Length Carry Chans. In: proc. 11 th Desgn of Integrated Crcuts and Systems Conference (DCIS 96), Barcelona, Span. [6] N.H.E Weste and K. Eshraghan. 1993. Prncples of CMOS VLSI desgn: Systems Perspectve, Readng, Massachusetts: ddson-wesley. [7] J. Rabaey. 2003. Dgtal Integrated Crcuts: Desgn Perspectve, Englewood Clffs, NJ: Prentce Hall. [8] N. Zhaung and H. Wu. 1992. New Desgn of the CMOS Full dder. IEEE J. Sold-State Crcuts. 27(5): 840-844. [9] H.. Mahmoud and M.. Bayoum. 1999. 10- transstor low-power hgh-speed full adder cel. In: IEEE Int. Symp. Crcut and Systems, pp. 43-46. [10] C.J. Fang, C.H. Huang, J.S. Wang, C.W. Yeh. 2002. Fast and compact dynamc rpple carry adder desgn. In: Proc. IEEE sa-pacfc Conference. pp. 25-28. [11] H. Cho, S.H. Hwang. 1996. Desgn of waveppelned 900MHz 16b rpple-carry adder usng modfed NPCPL. In: IEEE Int. Symp. Crcut and Systems. pp. 182-184. 10535