19-1951; Rev 3; 1/5 SOT3 Power-Supply Sequencers General Description The are power-supply sequencers for dual-voltage microprocessors (µps) and multivoltage systems. These devices monitor a primary supply voltage and enable/disable an external n-channel MOSFET switch for a secondary supply voltage. The / control local component voltage sequencing when system power-on/power-off characteristics cannot be guaranteed (supplies come from a multivoltage system bus, silver box, or must be sequenced in different modes for components on the same board). These small power-supply sequencers improve system reliability. The include an internal voltage reference/comparator with externally adjustable thresholds to monitor the primary power supply. When the primary supply is below the desired threshold, an external secondary supply MOSFET switch is disabled. When the primary supply exceeds the threshold, an internal charge pump is activated and the external MOSFET switch is enabled to connect the secondary supply to the load. The charge pump fully enhances the n-channel MOSFET switch to provide a very low R DS- ON voltage drop. The devices can be connected to support various supply sequencing priorities such as V I/O before V CORE or V CORE before V I/O. The features a logic-driven EN input to enable/disable the external MOSFET drive and includes an internally fixed ms enable timeout period (V PRIMARY GOOD to V SECONDARY ENABLE ). The allows the enable timeout period to be adjusted with a single external capacitor. Both devices are specified over the automotive temperature range (-4 C to +15 C) and are available in space-saving 6-pin SOT3 packages. Dual-Voltage Microprocessors Multivoltage Systems Digital Signal Processors Power PC Series Processors Applications Features Adjustable Primary Supply Voltage Monitor (Monitors Down to.6v) Internal Charge Pump to Enhance External Secondary Supply n-channel MOSFET Switch Delay from Primary Supply Good to Secondary Supply Enabled Factory Fixed ms () Capacitor Adjustable () Logic Driven ENABLE Input () Immune to Short Voltage Transients Few External Components -4 C to +15 C Operating Temperature Range Small 6-Pin SOT3 Package PART TEMP RANGE Ordering Information PIN- PACKAGE TOP M ARK UT-T -4 C to +15 C 6 SOT3-6 AARF UT-T -4 C to +15 C 6 SOT3-6 AARG Products must be ordered in,5 piece increments. Devices are available in both leaded and lead-free packaging. Specify lead-free by replacing -T with +T when ordering. Typical Operating Circuits PRIMARY SUPPLY (3.3V) SECONDARY SUPPLY (1.8V) TOP VIEW V CC GATE EN ON OFF DUAL-SUPPLY BOARD OR µp Pin Configurations Pin Configurations and Typical Operating Circuits continued at end of data sheet. 1 6 V CC 5 GATE Power PC is a trademark of IBM corp. 3 4 EN SOT3-6 Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-69-464, or visit Maxim s website at www.maxim-ic.com.
ABSOLUTE MAXIMUM RATINGS Referenced to, V CC, EN...-.3V to +6.V, SETD...-.3V to the higher of ( +.3V) and (V CC +.3V) GATE...-.3V to +1.V Input Current/Output Current (all pins)...ma Continuous Power Dissipation (T A = +7 C) 6-Pin SOT3 (derate 8.7mW/ C above +7 C)...696mW Operating Temperature Range...-4 C to +15 C Junction Temperature...+15 C Storage Temperature Range...-65 C to +15 C Lead Temperature (soldering 1s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( or V CC > +.15V to +5.5V, T A = -4 C to +15 C, unless otherwise specified. Typical values are at T A = +5 C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS V Operating Voltage Range CC1, (Note ).9 5.5 V V CC, V CC Supply Current I CC = V CC = +3.3V 6 1 µa V C C 1, V C C D i sab l e M od e C ur r ent = V CC = +3.3V, EN = µa, V CC Slew Rate (Note 3) 6 V/s (Note 4) 1. / t DELAY Undervoltage Lockout (UVLO) V UVLO 1.875..15 V Threshold V TH V rising, enables GATE.6.618.634 V Input Current (Note 3) 1 1 na Threshold Hysteresis V falling, disables GATE -1 % to GATE Delay t DELAY V > V TH, V EN V () 14 8 ms SETD Ramp Current () I SETD or V CC > +.15V 4 5 6 na SETD Voltage () V SETD or V CC > +.15V 1.1 1.4 1.73 V SETD Threshold Hysteresis () V SETD falling -6 mv GATE Turn-On Time t ON C GATE = 15p F, V C C = + 3.3V, V GATE = + 7.8V.5 1.5 1 ms GATE Turn-Off Time t OFF C GATE = 15p F, V C C = + 3.3V, V GATE = +.5V 3 µs With respect to V CC (Note ) R GATE > 5MΩ to V CC 4.5 5.5 6. GATE Voltage V GATE With respect to V CC (Note ) R GATE > 5MΩ to V CC 4. 6. EN Input Voltage V IL.4 or V CC > +.15V to + 5.5V V IH. V V Note 1: 1% production tested at T A = +5 C. Specifications over temperature limit are guaranteed by design. Note : Either or V CC must be >.15V. The other supply can go to. Note 3: Guaranteed by design, not production tested. Note 4: t DELAY (s) =.48 1 6 C SET
(T A = +5 C, unless otherwise noted.) tdelay (ms) 5 4 3 1 19 18 17 16 15 t DELAY vs. TEMPERATURE -4-4 6 8 1 1 TEMPERATURE ( C) () toc1 Typical Operating Characteristics GATE TURN-ON TIME 1ms/div toc C LOAD = 15pF V GATE 5V/div GATE TURN-OFF TIME toc3 1 1 V CC vs. GATE VOLTAGE toc4 V 5mV/div VGATE (V) 8 6 = +3.3V V = 1V V GATE 5V/div 4 C LOAD = 15pF µs/div.5 1. 1.5..5 3. 3.5 4. 4.5 5. V CC (V) 1 1 V CC vs. GATE VOLTAGE toc5 1 1 V CC vs. GATE VOLTAGE toc6 8 8 VGATE (V) 6 4 = V = 1V VGATE (V) 6 4 = +3.3V V = V CC.5 1. 1.5..5 3. 3.5 4. 4.5 5. V CC (V).5 1. 1.5..5 3. 3.5 4. 4.5 5. V CC (V) 3
(T A = +5 C, unless otherwise noted.) V (V).65.64.63.6.61.6.59 V vs. TEMPERATURE -4-4 6 8 1 1 TEMPERATURE ( C) Typical Operating Characteristics (continued) toc7 SUPPLY CURRENT (µa) 114 11 11 18 16 14 1 1 SUPPLY CURRENT vs. TEMPERATURE V EN = V V = V V CC = +3.3V = +5V I CC I CC1-4 - 4 6 8 1 1 TEMPERATURE ( C) V EN = V V = V = +3.3V V CC = +5V toc8 I CC vs. V CC I CC vs. V CC 14 1 toc9 14 1 toc1 1 1 ICC (µa) 8 6 4 = V EN = V V = V ICC (µa) 8 6 4 = 3.3V V EN = V V = V 1 3 4 5 6 V CC (V) 1 3 4 5 6 V CC (V) 4
PIN NAME FUNCTION 1 1 Supply Voltage 1. Either or V CC must be greater than the UVLO to enable external MOSFET drive. Ground 3 3 4 EN 4 SETD 5 5 GATE Pin Description Sequence Threshold Set. Connect to an external resistor-divider network to set the threshold that enables GATE turn-on. The internal reference is.618v. Active-High Enable. GATE drive is enabled t DELAY after EN is driven high. GATE drive is immediately disabled when EN is driven low. Connect to the higher of and V CC if not used. GATE Delay Set Input. Connect an external capacitor from SETD to to adjust the delay from > V TH to GATE turn-on. t DELAY (s) =.484 x 1 6 x C SET (F). GATE Drive Output. GATE drives an external n-channel MOSFET to connect V CC to the load. GATE drive enables t DELAY after exceeds V TH and ENABLE is driven high. GATE drive is immediately disabled when drops below V TH or ENABLE is driven low. When enabled, an internal charge pump drives GATE to V CC + 5.5V to fully enhance the external n-channel MOSFET. 6 6 V CC Supply Voltage. Either or V CC must be greater than the UVLO to enable external MOSFET drive. Detailed Description Many dual-supply processors or multivoltage boards require one power supply to rise to the proper operating voltage before another supply is applied. Improper sequencing can lead to chip latchup, incorrect device initiation, or long-term reliability degradation. If the various supply voltages are not locally generated (coming from a main system bus, an externally purchased silver box, or a nonsequenced power management chip), power-on and power-off sequencing can be difficult to control or predict. Supply loading can affect turnon/turn-off times from board to board. ( ) FOR ONLY The provide proper local voltage sequencing in multisupply systems. The sequencers use an external n-channel MOSFET to switch the secondary supply to the load only when the primary supply is above a desired operating voltage threshold. The n-channel MOSFET operates in a default off mode when the primary supply is below the desired threshold or if neither supply exceeds the sequencer s UVLO level. When the primary supply voltage is above the set threshold, the external MOSFET is driven on. An internal charge pump fully enhances the external MOSFET by providing a gate-to-source voltage (V GS ) of +5.5V (typ). The charge pump fully enhances the MOSFET to yield a low drain-to-source impedance (R DS(ON) ) for reduced switch voltage drop. The MOSFET is never driven on unless the sequencer can provide a minimum V GS enhancement, ensuring that the switch MOSFET never operates in its higher impedance linear range. Either supply may act as the primary source, regardless of the voltage level, provided that or V CC is greater than.15v (Figure 1 and Figure ). 5.6V Figure 1. Functional Diagram UVLO V CC SEQUENCE DELAY/ LOGIC EN (SETD) GATE DRIVE CHARGE PUMP GATE VCC OUT
Applications Information Adjusting t DELAY The features a capacitor adjustable sequence delay. The adjustable delay provides power sequencing for a wide range of devices with different power-supply delay requirements. Connect a capacitor (C SET ) between SETD and to adjust the delay time (Figure ). Calculate the sequence delay time as follows: t DELAY (s) =.48 1 6 C SET Setting Threshold Voltage at The threshold voltage is the minimum voltage at which V CC turn-on is acceptable. To monitor voltages higher than the threshold voltage, connect external resistors as a voltage-divider to, and calculate the minimum V CC turn-on voltage as follows: R1 = R ((V TRIP / V TH) - 1) where V TRIP is the minimum turn-on voltage at and V TH =.618V (Figure ). Since input current is 1nA (typ), high value resistors can be used. R1 R SETD C SET Gate Drive Characteristics The internal charge pump drives the n-channel MOSFET with a gate-to-source voltage (V GS ) of 5.5V, ensuring low MOSFET on-resistance R DS(ON). The charge pump drives the high-impedance capacitive load of a MOSFET gate input. Loading the GATE output resistively adds load current and reduces gate drive capability. The internal charge pump does not require external capacitors. The external pass MOSFET is disabled, and charge pump circuitry is turned off when neither nor V CC are above the 1.875V UVLO or EN is low. Logic Driven Supply Sequencing The offers a logic-compatible enable input (EN) that allows digital devices to control sequencing. When the TTL/CMOS-compatible EN input is logic-low, the GATE output is low. When the EN input is logic-high (and is above the monitor threshold), the GATE output is enabled after an internally fixed ms delay. For a logic-controlled sequencer when voltage monitoring is not desired, connect to or V CC >.6V (Figure 3). Sequencing Three or More Supplies Cascade multiple to sequence more than two supplies. Daisy-chaining devices allows one sequencer to monitor the passed voltage of an upstream sequencer through the comparator inputs. EN allows any sequencer to be shut down independent of the levels. Figure 4 shows an example of a three-supply system in which the first supply must come up before the second supply and the third supply must yield for both supplies. Figure. t DELAY ( ONLY) and V TH Adjust Selecting the Pass MOSFET The external pass MOSFET is connected in series with the sequenced power-supply source. Since the load current and the MOSFET drain-to-source impedance (R DS ) determine the voltage drop, the on characteristics of the MOSFET affect the load supply accuracy. The fully enhance the external MOSFET out of its linear range to ensure the lowest drain-tosource on impedance. For highest supply accuracy/ lowest voltage drop, select a MOSFET with an appropriate drain-to-source on impedance for a gate-to-source bias of 4.5V to 6.V. Negative-Going Voltage Transient Immunity The power-supply voltage sequencers are relatively immune to short-duration (pulse width), negative-going voltage transients (Figure 5). However, the amplitude of the transient is inversely proportional to its pulse width. TRANSISTOR COUNT: 638 PROCESS: BiCMOS Chip Information 6
V EN /V O t ON V CC + 5.5V GATE O t DELAY Figure 3. Timing Diagram 5(V) PRIMARY VOLTAGE SUPPLY 3.3(V) SECONDARY VOLTAGE SUPPLY 1% 9% t OFF 5% 1% 1.8(V) THIRD VOLTAGE SUPPLY V CC GATE V CC GATE MULTISUPPLY BOARD OR µp R 1 R 3 SETD/EN SETD/EN R R 4 Figure 4. Sequencing Three Power Supplies MAXIMUM TRANSIENT DURATION (µs) 18 16 14 1 1 8 6 4 = 5V V CC = SETD = FLOATING GATE DISABLED ABOVE CURVE.1.1 1 THRESHOLD OVERDRIVE, V TH - V (V) Figure 5. Maximum Transient Duration vs. Threshold in Overdrive 7
DC/DC SECONDARY SUPPLY (3.3V) Typical Operating Circuits (continued) R1 R PRIMARY SUPPLY (1.8V) V CC GATE SETD DUAL-SUPPLY BOARD OR µp Pin Configurations (continued) 1 6 V CC 3 4 SOT3-6 5 GATE Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) SETD 6LSOT.EPS PACKAGE OUTLINE, SOT 6L BODY 1 1-58 G 1 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 Maxim Integrated Products, 1 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 5 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.