RF LDMOS Wideband Integrated Power Amplifier

Freescale Semiconductor Technical Data RF LDMOS Wideband Integrated Power Amplifier The MW7IC22N wideband integrated circuit is designed with on--chip matching that makes it usable from 185 to 217 MHz. This multi--stage structure is rated for 26 to 32 Volt operation and covers all typical cellular base station modulation formats. Driver Application 21 MHz Typical Single--Carrier W--CDMA Performance: V DD =28Volts,I DQ1 = 4 ma, I DQ2 = 23 ma, P out = 2.4 Watts Avg., IQ Magnitude Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = 7.5 db @.1% Probability on CCDF. Frequency G ps (%) Output PAR (dbc) 211 MHz 32.6 16.8 7.7 --51.3 214 MHz 32.6 17. 7.6 --51.4 217 MHz 32.4 17. 7.5 --51.6 Capable of Handling 1:1 VSWR, @ 32 Vdc, 214 MHz, P out = 33 Watts CW (3 db Input Overdrive from Rated P out ) Typical P out @ 1 db Compression Point 2 Watts CW Driver Application 18 MHz Typical Single--Carrier W--CDMA Performance: V DD =28Volts, I DQ1 =4mA,I DQ2 = 23 ma, P out = 2.4 Watts Avg., IQ Magnitude Clipping, Channel Bandwidth = 3.84 MHz, Input Signal PAR = 7.5 db @.1% Probability on CCDF. Frequency G ps (%) Output PAR (dbc) 185 MHz 31.8 17.4 7.6 --51.2 184 MHz 31.8 17.4 7.7 --5.2 188 MHz 31.8 17.4 7.7 --51. Document Number: MW7IC22N Rev. 1, 12/213 185-217 MHz, 2.4 W AVG., 28 V SINGLE W -CDMA RF LDMOS WIDEBAND INTEGRATED POWER AMPLIFIER PQFN 8 8 PLASTIC Features Characterized with Series Equivalent Large--Signal Impedance Parameters and Common Source S--Parameters On--Chip Matching (5 Ohm Input, DC Blocked) Integrated Quiescent Current Temperature Compensation with Enable/Disable Function (1) Integrated ESD Protection In Tape and Reel. T1 Suffix = 1 Units, 16 mm Tape Width, 13--inch Reel. V GS1 V GS2 V GS1 V GS2 RF in Quiescent Current Temperature Compensation (1) RF out /V DS2 GND RF in RF in GND 24 23 22 21 2 19 1 18 2 17 3 16 4 15 5 14 6 7 8 13 9 1 11 12 RF out /V DS2 RF out /V DS2 V DS1 Figure 1. Functional Block Diagram V DS1 V DS1 Figure 2. Pin Connections 1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf. Select Documentation/Application Notes -- AN1977 or AN1987., 212--213. All rights reserved. 1

Table 1. Maximum Ratings Rating Symbol Value Unit Drain--Source Voltage V DSS --.5, +65 Vdc Gate--Source Voltage V GS --6., +1 Vdc Operating Voltage V DD 32, + Vdc Storage Temperature Range T stg --65 to +15 C Operating Junction Temperature (1,2) T J 15 C Input Power P in 37 dbm Table 2. Thermal Characteristics Thermal Resistance, Junction to Case Case Temperature 84 C, 2.4 W CW Stage 1, 28 Vdc, I DQ1 = 4 ma, 214 MHz Stage 2, 28 Vdc, I DQ2 = 23 ma, 214 MHz Case Temperature 92 C, 24 W CW Stage 1, 28 Vdc, I DQ1 = 4 ma, 214 MHz Stage 2, 28 Vdc, I DQ2 = 23 ma, 214 MHz Table 3. ESD Protection Characteristics Characteristic Symbol Value (2,3) Unit Test Methodology Human Body Model (per JESD22--A114) 2 Machine Model (per EIA/JESD22--A115) Charge Device Model (per JESD22--C11) Table 4. Moisture Sensitivity Level R JC Class Test Methodology Rating Package Peak Temperature Unit Per JESD22--A113, IPC/JEDEC J--STD--2 3 26 C Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) Characteristic Symbol Min Typ Max Unit A III 9. 1.9 8.6 1.6 C/W Stage 1 Off Characteristics Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =Vdc) Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =Vdc) I DSS 1 Adc I DSS 1 Adc I GSS 1 Adc Stage 1 On Characteristics Gate Threshold Voltage (V DS =1Vdc,I D =12 Adc) Gate Quiescent Voltage (V DS =28Vdc,I DQ1 =4mAdc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ1 = 4 madc, Measured in Functional Test) V GS(th) 1. 2. 3. Vdc V GS(Q) 2.9 Vdc V GG(Q) 6.2 6.9 7.7 Vdc 1. Continuous use at maximum temperature will affect MTTF. 2. MTTF calculator available at http://www.freescale.com/rf. Select Software & Tools/Development Tools/Calculators to access MTTF calculators by product. 3. Refer to AN1955, Thermal Measurement Methodology of RF Power Amplifiers. Go to http://www.freescale.com/rf. Select Documentation/Application Notes -- AN1955. (continued) 2

Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) (continued) Characteristic Symbol Min Typ Max Unit Stage 2 Off Characteristics Zero Gate Voltage Drain Leakage Current (V DS =65Vdc,V GS =Vdc) Zero Gate Voltage Drain Leakage Current (V DS =28Vdc,V GS =Vdc) Gate--Source Leakage Current (V GS =1.5Vdc,V DS =Vdc) Stage 2 On Characteristics Gate Threshold Voltage (V DS =1Vdc,I D =75 Adc) Gate Quiescent Voltage (V DS =28Vdc,I DQ2 = 23 madc) Fixture Gate Quiescent Voltage (V DD =28Vdc,I DQ2 = 23 madc, Measured in Functional Test) Drain--Source On--Voltage (V GS =1Vdc,I D =.75Adc) I DSS 1 Adc I DSS 1 Adc I GSS 1 Adc V GS(th) 1. 2. 3. Vdc V GS(Q) 2.8 Vdc V GG(Q) 4.7 5.5 6.2 Vdc V DS(on).1.3.8 Vdc Functional Tests (1) (In Freescale Test Fixture, 5 ohm system) V DD =28Vdc,I DQ1 =4mA,I DQ2 = 23 ma, P out = 2.4 W Avg., f = 214 MHz, Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 7.5 db @.1% Probability on CCDF. measured in 3.84 MHz Channel Bandwidth @ 5 MHzOffset. Power Gain G ps 31. 32.6 36. db Power Added Efficiency 16. 17. % Adjacent Channel Power Ratio --51.4 --47. dbc Input Return Loss IRL -- 12 -- 1 db Typical Performance over Frequency 21 MHz (In Freescale Test Fixture, 5 ohm system) V DD =28Vdc,I DQ1 =4mA,I DQ2 = 23 ma, P out = 2.4 W Avg., Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 7.5 db @.1% Probability on CCDF. measured in 3.84 MHz Channel Bandwidth @ 5 MHzOffset. Frequency G ps (%) Output PAR (dbc) 211 MHz 32.6 16.8 7.7 --51.3 -- 14 214 MHz 32.6 17. 7.6 --51.4 -- 12 217 MHz 32.4 17. 7.5 --51.6 -- 11 Typical Performances (In Freescale Test Fixture, 5 ohm system) V DD =28Vdc,I DQ1 =4mA,I DQ2 = 23 ma, 211--217 MHz Bandwidth Characteristic Symbol Min Typ Max Unit P out @ 1 db Compression Point, CW P1dB 2 W IMD Symmetry @ 9 W PEP, P out where IMD Third Order IMD sym 25 MHz Intermodulation 3 dbc (Delta IMD Third Order Intermodulation between Upper and Lower Sidebands > 2 db) VBW Resonance Point (IMD Third Order Intermodulation Inflection Point) VBW res 9 MHz Quiescent Current Accuracy over Temperature (2) Stage 1 with2k Gate Feed Resistors (--3 to 85 C) Stage 2 I QT Gain Flatness in 6 MHz Bandwidth @ P out =2.4WAvg. G F.2 db Gain Variation over Temperature G.45 db/ C (--3 C to+85 C) Output Power Variation over Temperature (--3 C to+85 C). 3.7 IRL P1dB.4 db/ C 1. Part internally input matched. 2. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control for the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf. Select Documentation/Application Notes -- AN1977 or AN1987. (continued) % 3

Table 5. Electrical Characteristics (T A =25 C unless otherwise noted) (continued) Typical Performance over Frequency 18 MHz (In Freescale 18 MHz Test Fixture, 5 ohm system) V DD =28Vdc,I DQ1 =4mA, I DQ2 = 23 ma, P out = 2.4 W Avg., Single--Carrier W--CDMA, IQ Magnitude Clipping, Input Signal PAR = 7.5 db @.1% Probability on CCDF. measured in 3.84 MHz Channel Bandwidth @ 5 MHzOffset. Frequency G ps (%) Output PAR (dbc) 185 MHz 31.8 17.4 7.6 --51.2 -- 13 184 MHz 31.8 17.4 7.7 --5.2 -- 9 188 MHz 31.8 17.4 7.7 --51. -- 6 IRL 4

V GG2 R2 C1 C11 C12 V GG1 V DD2 R1 C1 C2 C3 C7 C8 V DD1 C4 C5 MW7IC22N Rev. C9 V DD2 C6 C13 C14 C15 Figure 3. Test Circuit Component Layout Table 6. Test Circuit Component Designations and Values Part Description Part Number Manufacturer C1 1.2 pf, Chip Capacitor ATC6F1R2BT25XT ATC C2, C3, C11, C14 4.7 F, 5 V Chip Capacitors GRM31CR71H475KA12L Murata C4, C9, C1, C13 33 pf Chip Capacitors ATC6F33JT25XT ATC C5 1. F, 1 V Chip Capacitor GRM31CR72A15KA1L Murata C6, C12, C15 1 F, 5 V Chip Capacitors GRM55DR61H16KA88L Murata C7.5 pf Chip Capacitor ATC1BR5BT5XT ATC C8.6 pf Chip Capacitor ATC6FR6BT25XT ATC R1, R2 4.7 k, 1/4 W Chip Resistors CRCW1264K7FKEA Vishay PCB.2, r =3.5 RO435 Rogers 5

TYPICAL CHARACTERISTICS G ps, POWER GAIN 33 32.9 32.8 32.7 32.6 32.5 32.4 32.3 32.2 32.1 32 26 V DD =28Vdc,P out =2.4W(Avg.),I DQ1 =4mA I DQ2 = 23 ma G ps Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth Input Signal PAR = 7.5 db @.1% Probability on CCDF IRL PARC --5 --51 --52 28 21 212 214 216 218 22 222 f, FREQUEY (MHz) Figure 4. Output Peak -to -Average Ratio Compression (PARC) Broadband Performance @ P out = 2.4 Watts Avg. 18 17 16 15 14 --47 --48 --49, POWER ADDED EFFICIEY (%) (dbc) --8 --1 --12 --14 --16 --18 IRL, INPUT RETURN LOSS.4.3.2.1 --.1 PARC IMD, INTERMODULATION DISTORTION (dbc) --2 --3 --4 --5 --6 --7 V DD =28Vdc,P out = 9 W (PEP) I DQ1 =4mA,I DQ2 = 23 ma IM5--U IM5--L Two--Tone Measurements (f1 + f2)/2 = Center Frequency of 214 MHz IM3--U IM3--L IM7--L IM7--U 1 1 1 TWO--TONE SPACING (MHz) Figure 5. Intermodulation Distortion Products versus Two -Tone Spacing G ps, POWER GAIN 34 32 3 28 26 24 OUTPUT COMPRESSION AT.1% PROBABILITY ON CCDF 1 --1 --2 --3 --4 PARC G ps --1dB=5.7W V DD =28Vdc,I DQ1 =4mA I DQ2 = 23 ma, f = 214 MHz Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth --2dB=7.8W Input Signal PAR = 7.5 db @.1% Probability on CCDF --3dB=1.4W 5 43 36 29 22 15, POWER ADDED EFFICIEY (%) --1 --2 --3 --4 --5 --6 (dbc) 22 --5 8 5 1 15 2 25 P out, OUTPUT POWER (WATTS) Figure 6. Output Peak -to -Average Ratio Compression (PARC) versus Output Power --7 6

TYPICAL CHARACTERISTICS G ps, POWER GAIN 35 33 31 29 27 25 23 1 V DD =28Vdc,I DQ1 =4mA,I DQ2 = 23 ma, Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth 217 MHz 214 MHz 211 MHz P out, OUTPUT POWER (WATTS) AVG. 211 MHz 214 MHz 2 217 MHz G ps 1 Input Signal PAR = 7.5 db @.1% Probability on CCDF 1 4 Figure 7. Single -Carrier W -CDMA Power Gain, Power Added Efficiency and versus Output Power 6 5 4 3, POWER ADDED EFFICIEY (%) --1 --2 --3 --4 --5 --6 (dbc) 36 3 Gain --3 24 --6 GAIN 18 --9 IRL 12 --12 V DD =28Vdc 6 P in =dbm I DQ1 =4mA --15 I DQ2 = 23 ma --18 135 155 175 195 215 235 255 275 295 f, FREQUEY (MHz) Figure 8. Broadband Frequency Response IRL W -CDMA TEST SIGNAL 1 1 PROBABILITY (%) 1 1.1.1.1.1 Input Signal W--CDMA. Measured in 3.84 MHz Channel Bandwidth @ 5MHzOffset. Input Signal PAR = 7.5 db @.1% Probability on CCDF 1 2 3 4 5 6 7 8 9 PEAK--TO--AVERAGE Figure 9. CCDF W -CDMA IQ Magnitude Clipping, Single -Carrier Test Signal 1 --1 --2 --3 --4 --5 --6 --7 --8 --9 --1 -- in 3.84 MHz Integrated BW 3.84 MHz Channel BW +in3.84mhz Integrated BW --9 --7.2 --5.4 --3.6 --1.8 1.8 3.6 5.4 7.2 9 f, FREQUEY (MHz) Figure 1. Single -Carrier W -CDMA Spectrum 7

V DD =28Vdc,I DQ1 =4mA,I DQ2 = 23 ma, P out =2.4WAvg. f MHz Z in Z load 26 53.3 -- j5.4 7.28 -- j4.2 28 5.9 -- j5.9 7.28 -- j3.92 21 47.8 -- j51. 7.28 -- j3.82 212 45. -- j51.3 7.3 -- j3.74 214 41.7 -- j51. 7.32 -- j3.68 216 39.4 -- j49.6 7.33 -- j3.61 218 37.4 -- j48.5 7.35 -- j3.54 22 36.1 -- j47.2 7.38 -- j3.49 222 34.9 -- j45.9 7.42 -- j3.46 Z in = Device input impedance as simulated from gate to ground. Z load = Test circuit impedance as simulated from drain to ground. Device Under Test Output Matching Network Z in Z load Figure 11. Series Equivalent Input and Load Impedance 8

f (MHz) Z in ( ) V DD =28Vdc,I DQ1 =3mA,I DQ2 = 195 ma, CW Z load (1) ( ) P1dB Max Output Power P3dB (dbm) (W) (%) (dbm) (W) (%) 211 42. -- j42. 8. -- j1.1 45.5 36 51.3 46. 4 5.9 214 42.6 -- j42. 7.8 -- j1.4 45.5 36 5.7 46. 39 5.4 217 39. -- j45. 7.5 -- j1.5 45.3 34 5.3 45.8 38 5.2 (1) Load impedance for optimum P1dB power. Z in = Impedance as measured from input contact to ground. Z load = Impedance as measured from drain contact to ground. Device Under Test Output Load Pull Tuner Z in Z load Figure 12. Load Pull Performance Maximum P1dB Tuning f (MHz) Z in ( ) V DD =28Vdc,I DQ1 =3mA,I DQ2 = 195 ma, CW Z load (1) ( ) P1dB Max Power Added Efficiency P3dB (dbm) (W) (%) (dbm) (W) (%) 211 43.--j48. 8.1--j4.5 44.3 27 57.2 44.8 3 55.4 214 42.--j48. 7.6--j5.3 44.4 28 56.6 44.8 3 54.8 217 36.5--j5. 7.1--j5.8 44.3 27 56. 44.7 3 54.5 (1) Load impedance for optimum P1dB efficiency. Z in = Impedance as measured from input contact to ground. Z load = Impedance as measured from drain contact to ground. Device Under Test Output Load Pull Tuner Z in Z load Figure 13. Load Pull Performance Maximum Power Added Efficiency Tuning 9

V GG2 R2 C13 C14 V GG1 C12 V DD2 R1 C4 C1 L1 C2 C3 C5 C9 C1 C11 V DD1 C6 C7 C15 MW7IC22N Rev. V DD2 C8 C16 C17 Figure 14. Test Circuit Component Layout 18 MHz Table 7. Test Circuit Component Designations and Values 18 MHz Part Description Part Number Manufacturer C1, C6, C12, C15 33 pf Capacitors ATC6F33JT25XT ATC C2 1.1 pf Chip Capacitor ATC6F1R1BT25XT ATC C3 1.6 pf Chip Capacitor ATC6F1R6BT25XT ATC C4, C5, C13, C16 4.7 F, 5 V Chip Capacitors GRM31CR71H475KA12L Murata C7 1. F, 1 V Chip Capacitor GRM31CR72A15KA1L Murata C8, C14, C17 1 F, 5 V Chip Capacitors GRM55DR61H16KA88L Murata C9.3 pf Chip Capacitor ATC1BR3BT5XT ATC C1.5 pf Chip Capacitor ATC6FR5BT25XT ATC C11 1 pf Capacitors ATC6F1JT25XT ATC L1 12 nh Chip Inductor L8512JESTR AVX R1, R2 4.7 k, 1/4 W Chip Resistors CRCW1264K7FKEA Vishay PCB.2, r =3.5 RO435 Rogers 1

TYPICAL CHARACTERISTICS 18 MHz G ps, POWER GAIN 32.3 32.2 32.1 32 31.9 31.8 31.7 31.6 31.5 IRL 31.4 31.3 176 PARC G ps V DD =28Vdc,P out =2.4W(Avg.) I DQ1 =4mA,I DQ2 = 23 ma Single--Carrier W--CDMA 3.84 MHz Channel Bandwidth Input Signal PAR = 7.5 db @.1% Probability on CCDF --53 178 18 182 184 186 188 19 192 f, FREQUEY (MHz) Figure 15. Output Peak -to -Average Ratio Compression (PARC) Broadband Performance @ P out = 2.4 Watts Avg. 19 18 17 16 15 --48 --49 --5 --51 --52, POWER ADDED EFFICIEY (%) (dbc) --5 --8 --11 --14 --17 --2 IRL, INPUT RETURN LOSS.3.2.1 --.1 --.2 PARC G ps, POWER GAIN 34 32 3 28 26 24 22 1 V DD =28Vdc,I DQ1 =4mA,I DQ2 = 23 ma, Single--Carrier W--CDMA, 3.84 MHz Channel Bandwidth 188 MHz 184 MHz 185 MHz P out, OUTPUT POWER (WATTS) AVG. 185 MHz 184 MHz G ps 2 188 MHz 1 Input Signal PAR = 7.5 db @.1% Probability on CCDF 1 4 Figure 16. Single -Carrier W -CDMA Power Gain, Power Added Efficiency and versus Output Power 6 5 4 3, POWER ADDED EFFICIEY (%) --1 --2 --3 --4 --5 --6 (dbc) 36 3 Gain --4 24 --8 GAIN 18 --12 IRL 12 --16 V DD =28Vdc 6 P in =dbm I DQ1 =4mA --2 I DQ2 = 23 ma --24 14 1525 165 1775 19 225 215 2275 24 f, FREQUEY (MHz) Figure 17. Broadband Frequency Response IRL 11

V DD =28Vdc,I DQ1 =4mA,I DQ2 = 23 ma, P out =2.4WAvg. f MHz Z in Z load 176 46.6 + j14. 14.4 -- j7.6 178 54. + j15.2 14. -- j6.89 18 62.4 + j14.5 13.6 -- j6.71 182 7.8 + j11.4 13.2 -- j6.53 184 78.8 + j5.7 12.9 -- j6.34 186 85.2 -- j2.64 12.6 -- j6.14 188 88.8 -- j12.5 12.4 -- j5.94 19 89.2 -- j22.9 12.1 -- j5.74 192 86.7 -- j32.6 11.9 -- j5.53 Z in = Device input impedance as simulated from gate to ground. Z load = Test circuit impedance as simulated from drain to ground. Device Under Test Output Matching Network Z in Z load Figure 18. Series Equivalent Input and Load Impedance 18 MHz 12

PACKAGE DIMENSIONS 13

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PRODUCT DOCUMENTATION, SOFTWARE AND TOOLS Refer to the following documents, software and tools to aid your design process. Application Notes AN1955: Thermal Measurement Methodology of RF Power Amplifiers AN1977: Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family AN1987: Quiescent Current Control for the RF Integrated Circuit Device Family Engineering Bulletins EB212: Using Data Sheet Impedances for RF LDMOS Devices Software Electromigration MTTF Calculator RF High Power Model.s2p File Development Tools Printed Circuit Boards For Software and Tools, do a Part Number search at http://www.freescale.com, and select the Part Number link. Go to the Software & Tools tab on the part s Product Summary page to download the respective tool. The following table summarizes revisions to this document. REVISION HISTORY Revision Date Description Jan. 212 Initial Release of Data Sheet 1 Dec. 213 Replaced Case Outline 98ASA176D, Rev. O with Rev. A, pp. 13--14. Mechanical outline drawing modified to reflect the correct lead end features. Format of the mechanical outline was also updated to the current Freescale format for Freescale mechanical outlines. 16

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