THERE is currently a great deal of activity directed toward

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 2097 A 2.5-GHz BiCMOS Transceiver for Wireless LAN s Robert G. Meyer, Fellow IEEE, William D. Mack, Senior Member IEEE, and Johannes J. E. M. Hageraats Abstract A BiCMOS transceiver intended for spread spectrum applications in the 2.4 2.5 GHz band is described. The IC contains a low-noise amplifier (LNA) with 14 db gain and 2.2 db NF in its high-gain mode, a downconversion mixer with 8 db gain and 11 db NF, and an upconversion mixer with 17 db gain and P01 db of +3 dbm out. An on-chip local oscillator (LO) buffer accepts LO drive of 010 dbm with a half-frequency option allowed by an on-chip frequency doubler. Power consumption from a single 3-V supply is 34 ma in transmit mode, 21 ma in receive mode, and 1 A in sleep mode. Index Terms BiCMOS, doubler, inductor, low-noise amplifier, mixer, transceiver, wireless LAN. I. INTRODUCTION THERE is currently a great deal of activity directed toward realization of wireless local-area networks (WLAN s) based on 802.11 specifications. Successful implementation of such systems will require the availability of low-cost highperformance transceivers operating in the 2.4 2.5 GHz band. In this paper we describe a low-cost Si IC realized in a highvolume BiCMOS process which contains most of the elements required to realize the RF transmit and receive paths of a WLAN transceiver meeting 802.11 requirements. The IC is part of a chip set based on BiCMOS technology which allows future migration to higher levels of integration in which the RF front end, synthesizers, IF amplifier, in-phase/quadrature (I/Q) generators, and baseband signal processing may all be combined on a single chip. transmit and receive modes. The intermediate frequency (IF) in this application is 350 MHz. Both mixers are driven by an on-chip local oscillator (LO) buffer which has full-frequency LO and half-frequency LO input options, selectable via the LO switch at pin 11. An on-chip frequency doubler in the LO buffer together with on-chip LC filters deliver a full-frequency LO signal to the selected mixer with half-frequency LO inputs applied. The receive mixer differential output is converted to single-ended 50- operation with an external balun. This mixer has 8 db gain and 11 db single sideband (SSB) NF. The transmit mixer accepts single-ended or differential inputs and uses on-chip LC filters together with a medium power buffer to generate 17-dB gain and deliver 3 dbm output at 2.45 GHz to a separate power amplifier. Pin 17 selects transmit or receive modes. In the receive mode, the LNA, receive mixer, and the selected LO buffer option are powered up while the transmit mixer and output buffer are powered down. If the transmit mode is selected, the LNA and receive mixer are powered down while the transmit path is activated with the selected LO buffer option. The current consumption of the IC from a 3-V supply is 34 ma typical in transmit and 21 ma typical in receive. The whole chip can be powered down by the chip-enable function at pin 13 with a typical sleep-mode current drain of 1 A. Chip enable/disable times, transmit/receive, and receive/transmit switching times are 1 s typical using 50-pF external coupling capacitors. II. SYSTEM ARCHITECTURE The chip architecture is shown in Fig. 1. The 2.7 mm die is mounted in a 24-pin plastic package (TSSOP24). A low-noise amplifier (LNA) is switchable between high- (14 db) and lowgain ( 13 db) modes. The high-gain mode with 2.2 db noise figure (NF), dbm input, and dbm input is utilized in weak signal conditions. The low-gain mode with dbm input and dbm input can be selected in moderate-to-strong signal conditions. The LNA performance is optimized for signal frequencies in the range of 2.3 to 2.5 GHz. The signal goes off-chip from the LNA to an external image-rejection filter and is then input to the receive mixer via pin 19, which is also shared by the upconversion mixer output. This allows use of the same external filter in both Manuscript received June 17, 1997; revised August 1, 1997. R. G. Meyer is with the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720 USA. W. D. Mack was with Philips Semiconductors, Sunnyvale, CA 94088 USA. He is now with Maxim Integrated Products, Sunnyvale, CA 94086 USA. J. J. E. M. Hageraats is with Philips Semiconductors, Sunnyvale, CA 94088 USA. Publisher Item Identifier S 0018-9200(97)08268-1. III. CIRCUIT DESIGN CONSIDERATIONS A simplified schematic of the LNA is shown in Fig. 2. In the high-gain mode, the large area (72 ) device biased to 4 ma is the amplifying device. Input impedance matching is achieved via bond-wire inductance emitter degeneration [1]. In order to temperature compensate the gain, is biased to a proportional-to-absolute temperature (PTAT) current derived on-chip from Measured gain temperature coefficient of 0.002 db/ C has thus been realized. The low-gain parallel path is via emitter follower connected to the same output pin through matching elements. When the high-gain path is disabled by turning on and other shunt MOSFET s, connects to the input and is turned on to improve input matching and emulate the high-gain mode input impedance. When the high-gain path is active, current-source is turned off and pulls the emitter of high, turning it off. Thus, the path switching at the LNA is simply realized by hardwiring the two paths in parallel and alternately activating either one. A simplified schematic of the LO buffer is shown in Fig. 3. When the full frequency input is selected, current source 0018 9200/97$10.00 1997 IEEE

2098 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 Fig. 1. Transceiver architecture and pinout. Fig. 2. Simplified LNA schematic. is on and activates differential pair Current sources and are held off using MOS switches. The full frequency LO input at 2.1 GHz (IF at 350 MHz) is amplified by and the on-chip LC loads tuned to 2.1 GHz. The resulting LO voltage at is buffered by followers and amplified by additional LC-tuned differential amplifier stages that drive the transmit and receive mixers with an optimum LO voltage swing that is relatively independent

MEYER et al.: 2.5-GHz BiCMOS TRANSCEIVER FOR WIRELESS LAN S 2099 Fig. 3. Simplified LO buffer schematic. Fig. 4. Effect of inductor mutual coupling on LO buffer frequency response. of the external LO drive. The amplitude of the LO drive to the mixers is chosen to optimize the dynamic range. While mixer noise figure tends to improve with larger LO drive voltage [5], the value of begins to degrade [4] for LO voltages larger than about 600 mv pp. For half-frequency LO inputs, current source is switched off and and are activated. The four devices and form a frequency doubling circuit [2] that feeds full-frequency LO currents into the tuned signal path described previously. This circuit was originally used in an application for doubling from 10 20 MHz, but using devices with of 20 GHz it functions effectively at 100 times this frequency. The on-chip inductors are invaluable elements in this circuit giving substantial gain boost, improved output voltage headroom, and attenuation of out-of-band signals and noise. The inductors have an unloaded of about five at 2.1 GHz. Mutual coupling between the inductors ( and is layout dependent) has a small but measurable effect on the stage frequency response and should be included in simulations [3]. The sensitivity of the buffer frequency response to coupling between the inductors is illustrated by the computer simulations shown in Fig. 4. The downconversion mixer is shown in Fig. 5. This is a Gilbert-quad-based design with inductive degeneration on the input differential pair provided by on-chip 1-nH spiral inductors. The inductive degeneration improves overload performance and input matching with only a small degradation in mixer noise figure. The second stage of LC-boosted buffering in the LO path is provided by and The 300-

2100 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 Fig. 5. Receive mixer schematic. Fig. 6. Measured receive mixer gain versus LO power. shunt resistors are tailored to drive the quad with an optimized voltage swing of 600 mv pp over a wide range of external LO input ( 13 dbm to 5 dbm). The measured gain of the mixer versus LO power is shown in Fig. 6. The measured input was 2.8 dbm which was close to simulated values. In order to allow operation down to V, a 100- resistor is used for biasing in lieu of an active current source. This gives lower noise than an active current source and better impedance characteristics at 2.4 GHz for rejection of common-mode signals. The dc voltage at node Bias 1 required to bias the receive mixer is generated as shown in Fig. 7. The mixer bias current ma is derived from an on-chip bandgap-stabilized current source A This requires multiplication by 25 which is achieved by ratioing emitter resistors plus base resistors. Thus K K Transistors and appear in parallel as a 24 device for bias purposes. For the same reason, the 1-K base bias resistors together add 500 to the effective base resistance of the combination. The 50-pF capacitor is a filter to attenuate bias circuit noise fed to the mixer. The current helper in the mirror is a pnp npn up down combination that allows operation down to 2.7 V on Measured and simulated (using the Spectre RF simulator) SSB NF of the receive mixer were both close to 11 db. The major noise contributors as shown by simulation were the base resistances of and followed by the base resistances of the switching quad. Device sizing to reduce noise is limited by the effect of device parasitic capacitance in degrading mixer performance [4]. Computer optimization of the final configuration was used to fine-tune the values of the degeneration inductors. The mixer noise performance is independent of the choice of LO mode in both simulation and measurement. The receive mixer input node and transmit mixer buffer output node share the same package pin. Traditional microwave

MEYER et al.: 2.5-GHz BiCMOS TRANSCEIVER FOR WIRELESS LAN S 2101 Fig. 7. Receive mixer bias circuit. Fig. 8. Transmit mixer schematic. design techniques would require physical realization of a single-pole double-throw switch to select either one of these two paths. Such switches have insertion losses which adversely impact performance (such as NF degradation) and often must be realized as expensive stand-alone elements. Here we take advantage of the capabilities available on-chip in monolithic form to realize this function in a simple way with minimal performance degradation. The upconversion mixer is similar to the schematic of Fig. 5 except for the use of resistive emitter degeneration in the input pair (noise figure is less important in the transmit path and the low IF signal frequency means that the inductors required could not be realized on-chip). Since the desired output signal of the transmit mixer is at 2.45 GHz, onchip spiral inductors can be used to form LC-tuned loads at the quad output to select the 2.45-GHz component and attenuate all other outputs. A schematic is shown in Fig. 8. The circuit is biased from the same source as the receive mixers of Fig. 5. Nodes Bias 1 or Bias 2 are connected to node in Fig. 7 by MOSFET switches which select either the receive or transmit mixer function and power down the other. In Fig. 8 the transmit mixer quad is driven by its own tuned preamp which is powered up only when the transmit mode is selected. The output from the upconversion mixer is passed to the single-ended medium-power buffer shown in Fig. 9. Output device is biased to 10 ma with 25 of emitter degeneration in order to improve linerarity. This stage delivers 3 dbm output ( point) at 2.45 GHz to a 50- load at pin 19. The

2102 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 Fig. 9. Transmit buffer power amplifier. Fig. 10. RF port s11 in transmit and receive modes. Fig. 11. Measured transmit mixer and versus frequency. output is 11 dbm, which is sufficient to limit spectral regrowth in the power amplifier chain. Both the receive input (Fig. 5) and transmit output (Fig. 9) are connected to the same package pin and the desired function is selected by powering down either circuit via and other pull-down MOSFET s in the bias circuits. A single 3-nH external inductor acts as a pull-up in the transmit mode and as a matching element in either transmit or receive mode. Thus the switching function is achieved with minimum complexity and negligible gain, power, and noise degradation. The success of this approach is illustrated in the simulated data obtained using Spectre RF and shown in Fig. 10. This shows of the RF port from 2.2 to 2.8 GHz in both transmit and receive modes. Acceptable matches have been achieved with minimal variation between receive and transmit modes. Similar performance is observed in measurements on packaged parts. Measured transmit mixer and versus frequency are shown in Fig. 11. These agreed closely with computer simulations. Measured LO feedback to the LNA input was 46 dbm. This was achieved by careful modeling and choice of package pinout, bondwire orientation, circuit layout, and LO trace shielding.

MEYER et al.: 2.5-GHz BiCMOS TRANSCEIVER FOR WIRELESS LAN S 2103 Fig. 12. BiCMOS process cross section. Fig. 13. Die photograph. IV. PROCESS DESCRIPTION The BiCMOS process used for this design contains an extensive set of devices applicable to high-frequency mixed-signal designs. This includes 20-GHz NPN s, 0.7- m CMOS, 250- and 2000- /sq. poly resistors, 2 ff/ m oxide capacitors, Schottky diodes, lateral PNP s, plus three layers of metal. Minimum MOS devices feature 0.8 1.0 m gates, and use a metal strap technology to decrease parasitic capacitance. Minimum NPN emitter size is 0.7 1.0 m, and peak occurs at 210 A, while sidewall spacer technology produces very low noise NPN s. The process supports both medium- and high-frequency (GHz range) designs powered from 1 5.5 V in high-volume production. Interconnect pitch is 2.4 m without contacts and 2.8 m with contacts. Special contact technology allows the contacts and vias to be directly stacked to increase

2104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 12, DECEMBER 1997 TABLE I IC DEVICE PARAMETERS Parameter Double-Base NPN Lateral PNP AE 0.7 2 1.0 m 2 1.4 2 1.4 m 2 Basewidth 0.1 m 0.75 m Beta 100 61 VAF 20 V 26 V LV ceo 4.9 V 8.5 V FT 22 GHz 200 MHz IFT (peak) 210 A 10 A RE 36 35 RB-max 1011 260 CJE 3.5 ff 9.1 ff CJC 3.7 ff 10.5 ff CJS 14.4 ff 26.5 ff Parameter NMOS PMOS Gate-Oxide 150 Å 150 Å L e 0.70 m 0.75 m VT 0.65 V 00.75 V packing density. A cross section of the process is shown in Fig. 12. Device parameters are summarized in Table I. A die photograph is shown in Fig. 13. [4] R. G. Meyer, Intermodulation in high-frequency bipolar transistor integrated-circuit mixers, IEEE J. Solid-State Circuits, vol. SC-21, pp. 534 537, Aug. 1986. [5] C. D. Hull and R. G. Meyer, A systematic approach to the analysis of noise in mixers, IEEE Trans. Circuits Syst. I, vol. 40, pp. 909 919, Dec. 1993. Robert G. Meyer (S 64 M 68 SM 74 F 81) was born in Melbourne, Australia, on July 21, 1942. He received the B.E., M.Eng.Sci., and Ph.D. degrees in electrical engineering from the University of Melbourne in 1963, 1965, and 1968, respectively. In 1968, he was employed as an Assistant Lecturer in Electrical Engineering at the University of Melbourne. Since September 1968, he has been employed in the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, where he is now a Professor. His current research interests are high-frequency analog integrated-circuit design and device fabrication. He has acted as a consultant on electronic circuit design for numerous companies in the electronics industry. He is co-author of the book Analysis and Design of Analog Integrated Circuits (Wiley, 1993) and editor of the book Integrated Circuit Operational Amplifiers (IEEE Press, 1978). Dr. Meyer was President of the IEEE Solid-State Circuits Council and was an Associate Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS and of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. V. CONCLUSIONS A BiCMOS transceiver operating in the 2.4 2.5 GHz band has been described. The IC contains an LNA with two selectable gain values. In the high-gain mode the gain is 14 db with 2.2 db NF and of 3 dbm input. In the lowgain mode the gain is 13 db with dbm input. The downconversion mixer shares the RF pin with the upconversion mixer and has 8 db gain with 11 db SSB NF. The upconversion mixer has 17 db of gain with of 3 dbm out. An on-chip LO buffer accepts LO drive of 10 dbm with a half-frequency option allowed by an onchip frequency doubler. Power consumption from a single 3-V supply is 34 ma in transmit mode, 21 ma in receive mode, and 1 A in sleep mode. ACKNOWLEDGMENT The authors acknowledge C. Conkling for inspiring this project, the Philips BiCMOS Technology Development team for making the process production worthy, and K. McAdams for extensive measurement support. REFERENCES [1] R. G. Meyer and W. D. Mack, A 1-GHz BiCMOS RF front-end IC, IEEE J. Solid-State Circuits, vol. 29, pp. 350 355, Mar. 1994. [2] K. Kimura and H. Asazawa, Frequency mixer with a frequency doubler for integrated circuits, IEEE J. Solid-State Circuits, vol. 29, pp. 1133 1137, Sept. 1994. [3] A. M. Niknejad and R. G. Meyer, Analysis and optimization of monolithic inductors and transformers for RF IC s, in 1997 IEEE CICC Dig., pp. 375 378. William D. Mack (S 76 M 79 SM 95) was born in San Francisco, CA, on December 12, 1955. He received the B.S. and M.S. degrees in electrical engineering and computer science from the University of California (U.C.), Berkeley, in 1977 and 1979, respectively. He held Teaching Assistant/Associate positions at U.C. Berkeley, summer positions at the U.C. Berkeley Space Sciences Laboratory, Ampex Corporation, and Tektronix IC Design Group. In 1979, he joined the Philips Signetics Company, Sunnyvale, CA, where he held positions as Analog Designer in the Research Group, Senior Design Engineer, Bipolar Methodology Manager in the Linear Products Group, BiCMOS Methodology Manager in the Applications Specific Product Group, Philips Components, and Advanced Technology Group Manager in the Communications Products Group, Philips Semiconductors. He is currently the Director of Wireless Design at Maxim Integrated Products, Sunnyvale, CA, where his current area of interest is state-of-the-art RF IC designs for the wireless communications market. Mr. Mack is a member of Eta Kappa Nu. Johannes J. E. M. Hageraats was born in Amsterdam, The Netherlands, in 1967. He received the M.Sc. degree from the Delft University of Technology, The Netherlands, in 1991, working on broadband microwave components for optical receivers. In 1991, he joined Philips Research Laboratories, Eindhoven, The Netherlands, and has been involved in the research of multigigabit/s communications systems and their related optical and electrical circuits. Since 1996, he has been with Philips Semiconductors, Sunnyvale, CA. He is currently working on RF integrated circuit design for wireless communication.