A High-Driving Class-AB Buffer Amplifier with a New Pseudo Source Follower

A High-Driving Class-AB Buffer Amplifier with a New Pseudo Source Follower Chih-Wen Lu, Yen-Chih Shen and Meng-Lieh Sheu Abstract A high-driving class-ab buffer amplifier, which consists of a high-gain input stage and a pseudo source follower, is proposed. The pseudo source follower consists of two same types of differential pairs rather than two complementary error amplifiers. The high-driving capability is mainly provided by the folded amplifiers. An experimental prototype buffer amplifier implemented in a 0.35-μm technology demonstrates that the circuit dissipates an average static power consumption of only 660 μw at a power supply of 3.3 V, and exhibits the slew rates of 2.7 V/μs and 3.8 V/μs for the rising and falling edges, respectively, under a 300Ω/150 pf load. The second and third harmonic distortions (HD2 and HD3) are -67 db and -65 db, respectively, at 20 KHz under the same load. Index Terms class-ab, buffer amplifier, pseudo source follower, error amplifier. I. INTRODUCTION HE class-ab buffer amplifier is widely used for driving Theavy resistive or capacitive loads [1-5]. To achieve the extended voltage swing, the output transistors should be connected in a common-source configuration. The quiescent current of the output transistors should be small, while the dynamic current should be as large as possible. The gates of the two output transistors are normally driven by two in-phase ac signals separated by a dc voltage. For example, Hogervorst et al. [4-5] proposed a two-stage, compact, power-efficient 3 V operational amplifier, in which the output stage is biased by a floating class-ab control. Langen et al. [6] also proposed compact low-voltage power-efficient operational amplifier cells for VLSI, in which a class-ab control is used to bias the output transistors. The above amplifiers are compact and power-efficient. Another approach, which employs a pseudo source follower shown in Fig. 1 to realize class-ab buffer amplifiers, have been widely used for a large voltage swing output. It is composed of a pair of complementary common-source transistors with two feedback loops consisting of a pair of complementary error amplifiers [7-10]. This offers a wide output voltage swing and a large ratio between the maximum transient current (class B current) and the quiescent current. However, when the input voltage of the pseudo source follower is near to VDD/VSS, the gate-to-source voltage of the output transistors cannot reach a The authors are with the Department of Electrical Engineering, National Chi Nan University, Taiwan, R.O.C. (e-mail: cwlu@ ncnu.edu.tw). large value [5]. Fig. 2 shows the schematic of the conventional pseudo source follower. When the input voltage is near to VSS, the maximum gate-to-source voltage of M12 is only V SG8 V SD8 where V SG8 and V SD8 are the source-to-gate and source-to-drain voltages of M8, respectively. This limits the drive capability of the pseudo source follower. Also, the NMOS input error amplifier (M1~M5) conducts no current for a low level input. Then the node at the gate of M11 is high impedance and is easy to be disturbed. In this work, a new pseudo source follower is proposed to overcome this problem. The pseudo source follower employs two same types of error amplifiers rather than the complementary ones. Each error amplifier uses a folded amplifier to obtain a driving capability. The proposed buffer amplifier is designed to work at voice band frequencies for the telecommunication and audio applications. Fig. 1 The conventional architecture of class-ab buffer amplifier. II. PROPOSED CLASS-AB BUFFER AMPLIFIER The proposed class-ab buffer amplifier has the same architecture in Fig. 1 but its pseudo source follower employs two same types of differential pairs. Fig. 3 shows the first error amplifier, A1, which drives the output PMOS transistor, M23. This error amplifier, which is consisted of M1~M9, is a folded amplifier. M2 and M3, which are biased by M1, form the input differential pair. The active load, M4 and M5, is folded by the constant current sources, M8 and M9. M6-M7 are two common-gate amplifiers. When the voltage of the inverting input terminal, in1-, is increased, the current flowing in M3 is reduced but the current in M5 is increased. Then the gate voltage of the PMOS output transistor, M23, is pulled down to a lower level, so M23 starts to charge the output node. 978-1-4244-1710-0/07/$25.00 c 2007 IEEE 105

Since the gate voltage of M23 can be pulled down to minimum level of V DS7(triode) +V DS9(triode), which is very close to VSS, M23 has a large driving capability. Fig. 3 The proposed first error amplifier, A1. Fig. 2 The schematic of the conventional pseudo source follower. The second error amplifier, A2, is shown in Fig. 4. The differential pair is biased by M10 and its currents are mirrored to the folded active load by the current mirrors of M13-M16. M21-M22 are the folded active load of the differential pair. When the voltage of the inverting input terminal is reduced, the currents in M12, M14, and M15 are increased. However, the current flowing in M21 is reduced. This increases the gate voltage of the output NMOS transistor, M24. M24 then discharges the output node. Since the gate voltage of M24 can be raised up to a maximum value of VDD (V SD18(triode) + V SD20(triode) ), which is very close to VDD, M24 has a large discharge capability. This means that the proposed pseudo source follower has a large driving capability. Fig. 4 The proposed second error amplifier, A2. Fig. 5 shows the complete schematic of the proposed class-ab buffer amplifier where M25-M31 consists of a two-stage amplifier, M1-M9 and M10-M22 form the first and second error amplifier, respectively, and M23-M24 are two output transistors. The resistors of Rcs1-Rcs3 and capacitors of Ccs1-Ccs3 are used for the Miller compensation. Since all of the differential pairs are the same types, they have the same input common-mode range. When the input voltage is near to VSS, the gate voltage of M23 is still well controlled. This overcomes the above problem of the conventional circuit. 106 2007 IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2007)

Fig. 5 The complete schematic of the proposed class-ab buffer amplifier. III. EXPERIMENTAL RESULTS The proposed output buffer amplifier was fabricated using a 0.35-μm technology. The die photograph is shown in Fig. 6. The active area of the buffer is only 242 47 μm 2.Fig. 7 shows the measured result of the output with the input of 2.4 V swing of a 20 KHz triangular wave of the unity-gain buffer capacitor. It can be seen that the output basically follows the input. The step responses of the unity-gain buffer amplifier with the same load with the voltage swings of 20 mv and 2.4 V are shown in Fig s. 8 and 9, in which Fig. 8 shows the small signal response with 20 mvpp and Fig. 9 shows the large signal response with 2.4 Vpp. The slew rates are 2.7 V/μs and 3.8 V/μs for the rising and falling edges, respectively. Fig. 10 shows the measured results of the output with the input of a large dynamic range (2.4 Vp-p) of a 20 KHz sinusoidal wave for the unity-gain buffer amplifier. Fig. 11 shows its magnitude spectrum of the proposed buffer amplifier with a 2.4 Vp-p output swing into a 300Ω/150pF load. The second and third harmonic distortions (HD2 and HD3) are -67 db and -65 db, respectively, at 20 KHz under the same load. All of the measured results are summarized in Table 1. IV. CONCLUSION A high-driving class-ab buffer amplifier, which employs two pseudo source followers, has been presented. An experimental prototype buffer amplifier implemented in a 0.35 μm technology demonstrates that the circuit dissipates an average static power consumption of only 660 μw at a power supply of 3.3 V, and exhibits the slew rates of 2.7 V/μs and 3.8 V/μs for the rising and falling edges, respectively, under a 300Ω/150 pf load. The second and third harmonic distortions (HD2 and HD3) are -67 db and -65 db, respectively, at 20 KHz under the same load. Fig. 6 The die photograph. Fig. 7 The measured result of the output with the input of 2.4 V swing of a 20 KHz triangular wave of the unity-gain buffer 2007 IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2007) 107

capacitor. Fig. 8 The measured step response of the unity-gain buffer capacitor with the voltage swing of 20 mv. Fig. 10 The measured results of the output with the input of a large dynamic range (2.4 Vp-p) of a 20 KHz sinusoidal wave for the unity-gain buffer amplifier. Fig. 11 The measured magnitude spectrum of the proposed buffer amplifier with a 2.4 Vp-p output swing into a 300Ω/150pF load. Fig. 9 The measured step response of the unity-gain buffer capacitor with the voltage swing of 2.4 V. ACKNOWLEDGMENT The authors would like to thank the Chip Implementation Center of National Science Council for their support in chip fabrication. REFERENCES [1] Chih-Wen Lu and Chung Len Lee A Low Power High Speed Class-AB Buffer Amplifier for Flat Panel Display Application, IEEE Transactions on VLSI Systems, Vol 10, No. 2, pp. 163-168, April 2002. [2] Chih-Wen Lu A Low Power High Speed Class-AB Buffer Amplifier for Flat Panel Display Driver Application, Digest of SID, pp. 281-283, 2002. [3] Fan You, S.H.K. Embabi and Edgar Sanchez-Sinencio, Low-Voltage Class AB Output Amplifiers with Quiescent Current Control, IEEE 108 2007 IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2007)

Journal of Solid-State and Circuits. Vol.33, No.6, pp. 915-920, June 1998. [4] Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, A Compact Power-Efficient 3V Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries, IEEE ISSCC pp.244-245, 1994. [5] Ron Hogervorst, John P. Tero, Ruud G. H. Eschauzier, and Johan H. Huijsing, A Compact Power-Efficient 3V Rail-to-Rail Input/Output Operational Amplifier for VLSI Cell Libraries, IEEE Journal of Solid-State and Circuits. Vol. 29, No.12, pp. 1505-1513, December 1994. [6] Klaas-Jan de Langen, Johan H. Huijsing, Compact Low-Voltage Power-Efficient Operational Amplifiers Cells for VLSI, IEEE Journal of Solid-State and Circuits. Vol. 33, No.10, pp. 1482-1496, October 1998. [7] A. Torralba, R.G. Carvajal, J. Martinez-Heredia and J. Ramirez-Angulo, Class AB output stage for low voltage op-amps with accurate quiescent current control, ELECTRONICS LETTERS Vol. 36, No. 21, 12 th October 2000. [8] Kevin E. Brehmer, and James B. Wieser, Large Swing Power Amplifier IEEE Journal of Solid-State and Circuits. Vol. SC-18, No.6, pp. 624-629, December 1983. [9] John A. Fisher, A High-Performance Power Amplifier IEEE Journal of Solid-State and Circuits. Vol. SC-20, No.6, pp. 1200-1205, December 1985. [10] Joongsik Kih, Byungsoo Chang, Deog-Kyoon Jeong, and Wonchan Kim, Class-AB Large-Swing Buffer Amplifier with Controlled Bias Current, IEEE Journal of Solid-State and Circuits. Vol. 28, No.12, pp. 1350-1353, December 1993. [11] Gaetano Palumbo, and Salvatore Pennisi, High-Frequency Harmonic Distortion in Feedback Amplifiers: Analysis and Applications, IEEE Transactions on Circuits and Systems-E Fundamental Theory and Applications, Vol. 50, No. 3, pp. 328-340, March 2003. [12] P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits, 3 rd ed. New York: Wiley, 1993. [13] Frank N. L. Op t Eynde, Patrick F. M. Ampe, Lode Verdeyen, and Willy M. C. Sansen, A Large-Swing Low-Distortion Three-Stage Class AB Power Amplifier, IEEE Journal of Solid-State and Circuits. Vol. 25, No.1, pp. 265-273, February 1990. Table 1 Performance summary. This work Brehmer [6] Fisher [7] Kih [8] Technology 0.35-μm 1P4M Proprietary P 2 5-μm 1.2-μm 2P2M Die area 242 47 μm 2 (active) 1500 mils 2 1000 mils 2 103 mils 2 Power 3.3 V ± 5V ± 5V 5V supply Open loop 85 db 83 db 93 db 85 db gain Slew rate 2.7 V/μs (rise) 3.8 V/μs 0.6 V/μs 1.5 V/μs 0.65 V/μs Harmonic distortion Input common mode range Power dissipation (fall) (freq. = 20 KHz, V out,pp =2.4 VR L = 300 Ω, C L = 150 pf) HD2 = -67 db HD3 = -65 db (freq. = 4 KHz,V IN = 3.3 V P R L = 300 Ω, C L = 1000 pf) -49.9 db (freq. = 3 KHz,V IN =3V P R L =200Ω) HD2 = -73 db HD3 = - 78 db 2.4 V NA +3.3 ~ -5.5 V (freq. = 5 KHz, V out,pp = 3.5 V R L =300Ω, C L = 150 pf) THD = -63.6 db 4.25 V 660 μw 5 mw 12.7 mw 4.7 mw 2007 IFIP International Conference on Very Large Scale Integration (VLSI-SoC 2007) 109