Zero voltage switching active clamp buck-boost stage Cuk converter

Zero voltage switching active clamp buck-boost stage Cuk converter B.R. Lin and C.L. Huang Abstract: The paper presents an active clamp buck-boost stage Cuk converter to achieve soft switching commutation. An auxiliary switch and a clamp capacitor are connected in parallel with the primary side of the transformer to absorb all the energy stored in the transformer leakage inductance. The resonant inductance and the clamp capacitance are resonant to achieve zero-voltage switching (ZVS) of the auxiliary switch. On the other hand, the resonance between the resonant inductance and output capacitance of the main switch will achieve ZVS of the main switch in the proposed converter. The principle of operation and system analysis are presented. Design considerations of the proposed converter are also provided. Experimental results for a 170 W prototype circuit operating at 70 khz are given to demonstrate the effectiveness of the proposed converter. 1 Introduction Soft-switching techniques, such as zero-voltage switching (ZVS) and zero-current switching (ZCS) [1, 2] for DC/DC converters, have been proposed to substantially reduce switching losses and, hence, attain high efficiency at increased frequency. However, the voltage stresses on the power switches are too high in the resonant converters, especially for the high-input DC voltage. The asymmetrical PWM techniques [3 5] were proposed to achieve ZVS turn-on and to increase circuit efficiency. The drawback of the asymmetrical converter is that the voltage and current stresses of switching devices are related to duty cycle. Full-bridge converters with phase-shift pulse-width modulation (PWM) technique [6, 7] have been proposed to regulate the output DC voltage and to achieve ZVS operation of power switches. However, the high cost and narrow ZVS range for the lagging leg of the phase-shift full-bridge converter are the main disadvantages. Active clamp techniques [8 10] were proposed to limit the voltage stress of the main switch and to reduce the switching losses. The high frequency operation in the Cuk converter is desirable because of the reduction of reactive component size and cost. Buck-boost conversion ratio in the Cuk converter enables arbitrary output voltage. An isolated ZVS Cuk converter is proposed in this paper to achieve ZVS operation for both main and auxiliary switches. An active clamp buck-boost stage circuit added to the Cuk converter allows the utilisation of leakage inductance of the transformer to achieve ZVS operation and to limit the voltage stress on the power switches. The ZVS operation will reduce the switching losses and increase the circuit efficiency. The circuit configuration, principle of # The Institution of Engineering and Technology 2007 doi:10.1049/iet-epa:20060157 Paper first received 23rd April and in revised form 19th July 2006 The authors are with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin 640, Taiwan E-mail: linbr@yuntech.edu.tw operation and design considerations of the proposed converter are presented. First, the circuit configuration of the proposed converter is discussed. The system analysis, steady state analysis and circuit design consideration are presented. Finally, experimental results based on a 170W prototype circuit are presented to verify the effectiveness and performance of the proposed converter. 2 Circuit configuration The circuit configuration of the proposed converter is shown in Fig. 1. L 1 and L 2 are input and output inductors, respectively. S and S a are main and auxiliary switches. The capacitors C 1 and C 2 are medium for transferring energy from the source to the load. C c and C o are the clamp capacitor and output capacitor, respectively. L m is the magnetising inductor of the isolation transformer. D is a freewheeling diode. L r and C r are resonant inductor and resonant capacitor, respectively. The active clamp circuit, including the auxiliary switch S a and the clamp capacitor C c, allows the utilisation of transformer leakage inductance to achieve ZVS operation and limits the peak voltage stress of the main switch S. If the turn ratio of the isolation transformer is one, the proposed converter provides an output voltage which is less than or greater than the input voltage. In the proposed converter, main switch S and clamp switch S c are all turned on at ZVS, based on the resonance during the commutation interval. This enables the converter to operate with higher switching frequency and reduction in the size of the reactive components. 3 Operation principle Some assumptions of the proposed converter are made for the system analysis: (1) the clamp capacitance C c is larger than the resonant capacitance C r and the clamp capacitor voltage v Cc is a constant value when main switch S is turned on; (2) the input voltage v in is a constant value; (3) the input and output inductances L 1 and L 2 are IET Electr. Power Appl., 2007, 1, (2), pp. 173 182 173

Fig. 1 Circuit configuration of the proposed active clamp Cuk converter large enough. (The input and output currents i L1 and i L2 are considered as the constant values); (4) Joule and iron losses are neglected in both inductances and transformer; (5) the resonant inductance L r is smaller than the magnetising inductances L m ; (6) all semiconductor components are modelled as ideal; (7) the turn ratio between the primary winding turn of transformer and the secondary winding turn is n ¼ n p =n s ; and (8) the energy stored in the resonant inductance L r is greater than energy stored in the resonant capacitance C r to achieve ZVS operation. The key waveforms of the proposed converter are given in Fig. 2. Based on Fig. 2, the main and auxiliary switches are turned on at ZVS. The switching losses due to switch turn-on instant are effectively reduced. However, both switching are not turned off at ZCS, therefore there are some switching losses at turn-off instant. The features of the proposed converter are ZVS turn-on, low-voltage stresses on the main and auxiliary switches, less additional circuit components in the conventional isolated Cuk converter (one switch and one clamp capacitor) and easy control algorithm using commercial PWM IC and gate driver. There are six operating stages of the proposed converter in a switching period. Fig. 3 gives the equivalent circuits of the proposed converter for each operating stage. Fig. 3 Operation stages of proposed converter a Stage 1 [t 1 t 2 ] b Stage 2 [t 2 t 3 ] c Stage 3 [t 3 t 4 ] d Stage 4 [t 4 t 5 ] e Stage 5 [t 5 t 6 ] f Stage 6 [t 6 t 1 ] Stage 1 (t 1, t, t 2, Fig. 3a): In the first stage, main switch S is turned on and auxiliary switch S a is turned off. The input current charges the inductor L 1. The input current i L1 increases linearly: i L1 ðtþ ¼i L1 ðt 1 Þþ v in L 1 ðt t 1 Þ The capacitor voltage v Cr ¼ v S,ds ¼ 0. The magnetising inductor voltage v Lm ¼ v C1 L m =ðl m þ L r Þ. The magnetising current i Lm decreases linearly. The inductor current i Lr is expressed as ð1þ Fig. 2 174 Key waveforms of proposed converter i Lr ðtþ ¼i C2 ðtþ=n i Lm ðtþ ¼ i C2 ðtþ=n þ v C1L m ðt t 1 Þ i L m þ L Lm ðt 1 Þ r L m i C2 ðtþ=n þ v C1 ðt t 1 Þ=L m i Lm ðt 1 Þ ð2þ IET Electr. Power Appl., Vol. 1, No. 2, March 2007

The main switch current i S ¼ i L1 þ i Lr ¼ i L1 þ i C1. The secondary winding voltage of transformer v s ¼ v C1 L m / [n(l m þ L r )]. The diode D is turned off. The inductor current i L2 equals i C2 and increases linearly i L2 ðtþ ¼i C2 ðtþ i L2 ðt 1 Þþ 1 v C1 L m L 2 nðl m þ L r Þ þ v C2 v o ðt t 1 Þ i L2 ðt 1 Þþ 1 v C1 L 2 n þ v C2 v o ðt t 1 Þ The positive current i C2 discharges capacitor C 2. This stage ends at time t ¼ t 2 when main switch S is turned off. Stage 2 (t 2, t, t 3, Fig. 3b): At time t ¼ t 2, main switch S is turned off. The input inductor current i L1 and capacitor current i C1 charge capacitor C r from 0 to v C1 þ v Cc. The capacitor voltage v Cr can be given approximately as ð3þ v Cr ðtþ i S ðt 2 Þ C r ðt t 2 Þ ð4þ The primary side voltage v Lm ¼ (v Cr 2 v C1 )L m / (L m þ L r ) v Cr 2 v C1. The secondary side voltage v s ðv C1 v Cr Þ=n. The magnetising current of the transformer in this stage is expressed as i Lm ðtþ ðv Cr v C1 Þðt t 2 Þ L m þ i Lm ðt 2 Þ ð5þ The time interval in this stage is very short, and the input current i L1, switch current i S and capacitor current i C1 are almost constant in this stage. The diode current at the secondary side i D ¼ 0. The output inductor current in this stage is given as i L2 ðtþ ¼i C2 ðtþ 1 L 2 v C1 v Cr n þ v C2 v o ðt t 2 Þþi L2 ðt 2 Þ At time t ¼ t 3, the capacitor voltage v Cr ¼ v C1 þ v Cc, the antiparallel diode of auxiliary switch S a turns on and the primary side voltage v Lm v Cc. The diode D turns on at time t ¼ t 3. From (4) the time interval in this stage is given as Dt 23 ¼ t 3 t 2 ¼ ðv C1 þ v Cc ÞC r i S ðt 2 Þ Stage 3 (t 3, t, t 4, Fig. 3c): The antiparallel diode of auxiliary switch S a turns on and the diode D at the secondary side turns on at time t ¼ t 3. The transformer secondary side voltage v s ¼2v C2. Before the clamp current i Cc becomes negative, the auxiliary switch S a should be turned on to achieve ZVS. The input inductor current i L1 decreases linearly with the slope of (v in 2 v C1 2 v Cc )/L 1. The voltage across the primary side v Lm ¼ nv C2. The clamp capacitor voltage v Cc (t 3 ) ¼ nv C2 (L m þ L r )/L m. The capacitor voltage v C1 is almost constant in this stage. The resonant current i Lr and clamp ð6þ ð7þ voltage v Cc are expressed as follows! t t v Cc ðtþ¼v Cc ðt 3 Þcos pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 þði L1 ðt 3 Þ C c ðl m þ L r Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! L þ i Lr ðt 3 ÞÞ m þ L r t t sin pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 C c C c ðl m þ L r Þ t t i Lr ðtþ¼ði L1 ðt 3 Þþi Lr ðt 3 ÞÞcos pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 C c ðl m þ L r Þ sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi! C v Cc ðt 3 Þ c t t sin pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 i L m þ L L1 ðt 3 Þ r C c ðl m þ L r Þ Before the clamp capacitor current i Cc becomes negative value, the auxiliary switch S a turns on at ZVS. The clamp capacitor current i Cc will decrease from a positive to a negative value. When the current i Cc becomes negative, the clamp capacitor C c begins to discharge. The capacitor voltage v Cr ¼ v C1 þ v Cc. As the inductor voltages v L1 and v L2 are negative, the input and output inductor currents i L1 and i L2 decrease linearly. The diode current i D ¼ i o 2 i C2. The magnetising inductor current increases linearly. The capacitor current i C2 ¼ n(i Lr þ i Lm ). The capacitor current i C2 will decrease from a positive to a negative value. This operating stage ends when auxiliary switch S a turns off. Stage 4 (t 4, t, t 5, Fig. 3d): At time t ¼ t 4, the auxiliary switch S a turns off. As i Lr þ i L1, 0, therefore the main switch current i S is negative. The primary side voltage v Lm ¼ nv C2 and the magnetising inductor current increases linearly. The negative switch current i S1 discharges capacitor C r from v Cc þ v C1 to 0 in this stage. The voltage v Cr is approximately given as! ð8þ ð9þ v Cr ðtþ v Cc ðt 4 Þþv C1 þ i Lrðt 4 Þþi L1 ðt 4 Þ C r ðt t 4 Þ ð10þ where i Lr ðt 4 Þþi L1 ðt 4 Þ is negative. To ensure ZVS operation of main switch S, the capacitor voltage v Cr should reach zero before the end of this stage. Hence the energy stored in the resonant inductor L r must be greater than the energy stored in the resonant capacitor C r L r C r½v Cc ðt 4 Þþv C1 Š 2 i Lr ðt 4 Þ 2 ð11þ At time t ¼ t 5, the resonant capacitor voltage v Cr ¼ 0 and the antiparallel diode of main switch S turns on. The diode D at the secondary side is in the free wheeling mode. From (10), the time interval in this stage is expressed as Dt 45 ¼ t 5 t 4 ¼ ½v Ccðt 4 Þþv C1 ŠC r i Lr ðt 4 Þ i L1 ðt 4 Þ ð12þ This time interval is very short, therefore the primary side and secondary side currents are almost constant. Stage 5 (t 5, t, t 6, Fig. 3e): At time t ¼ t 5, the resonant capacitor voltage v Cr ¼ 0 and the antiparallel diode of main switch S turns on. The secondary side diode is still in the free wheeling mode. The input inductor current, primary current and main switch current increase linearly. Before the main switch current i S1 becomes positive, the main switch S should be turned on to achieve ZVS operation. The secondary side diode current i D decreases. This stage ends when main switch S turns on at ZVS. IET Electr. Power Appl., Vol. 1, No. 2, March 2007 175

Stage 6 (t 6, t, t 1, Fig. 3f): This stage begins when main switch S turns on at ZVS. The operational principle of the proposed converter in this stage is almost the same as the operation principle in stage 5. The switch current i S increases from a negative to a positive value. In this operating mode, the key voltages and currents of the circuit are expressed as follows v Cr ðtþ ¼0; v Lm ¼ nv C2 ; i Lm ðtþ ¼i Lm ðt 6 Þþ nv C2 L m ðt t 6 Þ; Fig. 5 Photograph of prototype circuit Di L1 Dt 16 ¼ v in =L 1 ; Di L2 Dt 16 ¼ v o =L 2 ð13þ This stage ends at t ¼ t 1 when diode current i D ¼ 0, at which moment Stage 6 ends and the circuit goes to the operating stage 1. 4 Steady state analyses and design consideration Based on the key waveforms shown in Fig. 2, the delay time during the transition interval between main switch S and auxiliary switch S a at stages 2, 4 and 5 is neglected in the system analysis. When main switch S is turned on and auxiliary switch S a is turned off at stage 1, the input and output inductor voltages v L1 ¼ v in and v L2 v C1 =n þ v C2 v o. When main switch S is turned off and auxiliary switch S a is turned on at stage 3, the input and output inductor voltages v L1 ¼ v in v C1 v Cc and v L2 ¼ v o. In the steady-state analysis, the voltage-second product across the input inductor, when main switch and body diode are turned on, should equal the voltage-second product when both main switch and body diode are turned Fig. 4 Design considerations a Relationship between clamp voltage and input voltage with different duty cycle b Relationship between the output voltage and input voltage under D loss ¼ 0.05 and n ¼ 5 c Relationship between the voltage stress of diode and input voltage with different duty cycle 176 Fig. 6 Measured results of the conventional Cuk converter at rated output power a Gate voltage and drain voltage b Drain voltage and drain current IET Electr. Power Appl., Vol. 1, No. 2, March 2007

Fig. 7 Experimental results of gate voltages and drain voltages for switching devices S and S a for different output power a 170 W b 120 W c 60 W d 12 W IET Electr. Power Appl., Vol. 1, No. 2, March 2007 177

off V in DT s ¼ðV C1 þ V Cc V in Þð1 DÞT s ð14þ where D is the duty cycle of main switch S and V in, V C1 and V Cc are average voltage value of input voltage and capacitors C 1 and C c. Based on the voltage-second balance on the output inductor L 2, the following equation, can be given: ðv C1 =n þ V C2 V o ÞðD D loss ÞT s ¼ V o ð1 D þ D loss ÞT s ð15þ where D loss is the duty cycle loss of the converter at the Stage 6. The duty cycle loss depends on the load current. The duty cycle loss at heavy output load is larger than the duty cycle loss at light output load. For the voltage-second balance on the primary and secondary side of transformer, the following equations can be obtained V C1 DT s ¼ V Cc ð1 DÞT s V C1 n ðd D lossþt s ¼ V C2 ð1 D þ D loss ÞT s ð16þ ð17þ Based on (14) (17), the clamp capacitor voltage V Cc, capacitor voltages V C1 and V C2 and output voltage V o are expressed as V Cc ¼ V C1 ¼ V in V C2 ¼ V o ¼ D 1 D V in ð18þ D D loss nð1 D þ D loss Þ V in ð19þ ð20þ Fig. 4a gives the relationship between clamp capacitor voltage and input voltage with different duty cycle. When duty cycle is less than 0.5, the clamp voltage V Cc, V in. When duty cycle is greater than 0.5, the clamp voltage V Cc. V in. Fig. 4b gives the relationship between output voltage and input voltage with different duty cycle. When main switch S is turned on, the current ripple on the magnetising inductor is given as follows Di Lm ðd D loss ÞT s V C1 =L m ¼ðD D loss ÞT s V in =L m ð21þ The ripple currents on the input and output inductors L 1 and L 2 are given as Di L1 ¼ DT s V in =L 1 Di L2 ¼ð1 DþD loss ÞT s V o =L 2 ð22þ ð23þ Fig. 8 Experimental results of gate voltages and drain currents for switching devices S and S a for different output power a 170 W b 120 W c 60 W d 12 W 178 IET Electr. Power Appl., Vol. 1, No. 2, March 2007

Fig. 9 Experimental results under the rated output power a Gate voltage v S,gs, inductor current i L1, drain current i S and capacitor current i C1 b Gate voltage v S,gs, capacitor current i C1, resonant current i Lr and clamp capacitor current i Cc c Gate voltage v S,gs, resonant current i Lr capacitor current i C2 and diode current i D d Gate voltage v S,gs, capacitor current i C2, diode current i D and inductor current i L2 e Drain voltages v S,ds and v Sa,ds, capacitor voltage v C1 and clamp capacitor voltage v Cc f Gate voltage v S,gs, clamp capacitor voltage v Cc, and capacitor voltages v C1 and v C2 If the ripple currents on the input and output inductors are given, the input and output inductances are expressed as L 1 ¼ DT s V in =Di L1 ; L 2 ¼ð1 D þ D loss ÞT s V o =Di L2 ð24þ Based on power balance between the input and output side, the average input current can be obtained as I L1 ¼ P o =ðhv in Þ, where h is the circuit efficiency. The average output inductor current I L2 ¼ I o. The RMS currents on the input and output inductors are expressed as follows sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi I L1;rms I L1 1 þ Di 2 L1 =12; I L1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi I L2;rms I o 1 þ Di 2 L2 =12 I o ð25þ IET Electr. Power Appl., Vol. 1, No. 2, March 2007 179

Fig. 10 Experimental output voltage and load current under the step load variation a Between P o ¼ 60 W and P o ¼ 96 W b Between P o ¼ 96 W and P o ¼ 156 W The maximum input and output inductor currents are given as I L1;max I L1 1 þ Di L1 ; I 2I L2;max I o 1 þ Di L2 ð26þ L1 2I o The average diode current i D is expressed as I D;av I o The peak current of diode D is expressed as i D;max ¼ 2P o V o ð1 D þ D max Þ The voltage stress of the diode is given as V D;stress ¼ V C1 =n þ V C2 ¼ V in =nð1 D þ D loss Þ ð27þ ð28þ ð29þ Fig. 4c gives the relationship between the voltage stress of the diode D and duty cycle. The turn ratio between the transformer secondary side and primary side is equal to n ¼ ðd max D loss ÞV in ð1 D max þ D loss ÞV o ð30þ where D max is the maximum duty cycle when input voltage V in is minimum. The voltage stresses on main switch S and auxiliary switch S a equal v in =ð1 D max Þ. In Stage 4, the energy stored in the resonant inductance must be greater than the energy stored in the resonant capacitance, to ensure the ZVS operation for main switch S, i.e. L r C r ½v Cc ðt 4 Þþv C1 Š 2 =i Lr ðt 4 Þ 2. p The resonant angular frequency in states 2 and 4 is 1= ffiffiffiffiffiffiffiffiffi L r C r. The pdelay time t d at t 2 t 3 and t 4 t 5 can be equal to p ffiffiffiffiffiffiffiffiffi L r C r =2. If the resonant capacitance C r is given, the resonant inductance L r can be expressed as L r ¼ 4td=ðC 2 r p 2 Þ. The clamp capacitor and resonant inductor are resonant about one half of the resonant period in stage 3. We can make the design such that one half of the resonant period approximately equals turn off time of the main switch T r 2 ¼ p p ffiffiffiffiffiffiffiffiffi L r C c ¼ð1 D min;vin ÞT ð31þ where D min;vin ¼ðD max V in;min Þ=V in;max, and therefore the clamp capacitance can be obtained as 5 Experimental results The experimental results are provided in this Section to verify the effectiveness of the proposed converter. The proposed converter was implemented with the following parameters: v in ¼ 130 V 180 V, v o ¼ 12 V, P o,max ¼ 170 W, f s ¼ 70 khz (switching frequency). The ETD-39 core with B max ¼ 2000 G and A e ¼ 1.25 cm 2 was used as an isolation transformer. The turn ratio between the transformer primary side winding turn n p ¼ 34 and secondary side winding turn n s ¼ 4. The magnetising inductance of the transformer is designed as L m ¼ 300 mh. The delay time between the gate signals of main switch S and auxiliary switch S a is 300 ns. The resonant capacitor C r ¼ 450pF. The selected resonant inductor L r is about 30 mh. The input and output inductances are L 1 ¼ 1.5 mh and L 2 ¼ 75 mh. The selected clamp capacitance C c ¼ 490 nf. The selected output filter capacitance C o is 2200 mf. The capacitances C 1 ¼ C 2 ¼ 6.6 mf. The S60SC6M is used for diode D in the secondary side. The MOSFETs IRFP460 are used for main and auxiliary switches in the proposed converter. Fig. 5 shows a photograph of the prototype circuit. Fig. 6 shows the measured gate voltage and drain voltage of power switch S for a conventional hard switching Cuk converter. From Fig. 6a, the drain voltage is still at high voltage level when the gate voltage is changed from low voltage to high C c ¼ ½ð1 D min;vinþtš 2 p 2 L r ð32þ Fig. 11 Measured circuit efficiencies of the proposed converter and conventional Cuk converter 180 IET Electr. Power Appl., Vol. 1, No. 2, March 2007

Fig. 12 Measured results of the proposed converter at the rated output power when input AC source voltage v s ¼ 90 V rms a and b Gate voltages and drain voltages for switching devices S and S a c Drain voltages and drain currents for switching devices S and S a d Gate voltage v S,gs, inductor current i L1, drain current i S and negative capacitor current -i C1 e Gate voltage v S,gs, negative capacitor current -i C1, negative resonant current -i Lr and clamp capacitor current i Cc voltage level. From Fig. 6b, the drain voltage and drain current are overlapped during the transition interval when switch S is turned on. Hance, the switching losses have occurred and the circuit efficiency of the hard switching Cuk converter decreases. Fig. 7 gives measured waveforms of gate voltages and drain voltages of main switch S and auxiliary switch S a for different output power. Before the gate voltages are positive, the drain voltages are zero. Hence, the ZVS conditions of both switches are achieved. Fig. 8 shows the experimental waveforms of gate voltages and drain currents for switches S and S a for different loading conditions. It can be observed that the drain currents i S and i Sa are negative before the gate voltages v S,gs and v Sa,gs are positive. The intrinsic body diodes of switches S and S a are conducting, therefore the active switches S and S a can be turned on to achieve ZVS operation. The key waveforms of the proposed converter at the rated output power are given in Fig. 9. The experimental results of gate voltage v S,gs, inductor current i L1,drain current i S and capacitor current i C1 are shown in Fig. 9a. Before main switch S is turned on, the switch IET Electr. Power Appl., Vol. 1, No. 2, March 2007 181

current i S is negative to discharge capacitor C r in order to achieve ZVS operation for main switch S. Whenmain switch S is turned on, the drain current i S equals input inductor current i L1 and capacitor current i C1. When main switch S is turned off, capacitor current i C1 ¼ i L1 andswitchcurrenti S ¼ 0. Fig. 9b illustrates the measured results of the gate voltage v S,gs, capacitor current i C1, resonant current i Lr and clamp capacitor current i Cc. When main switch S is turned on, the clamp capacitor current is zero and capacitor current i C1 equals the resonant inductor current i Lr. When main switch S is turned off, the auxiliary switch S a is turned on. In this interval, the resonant inductor current i Lr equals the capacitor current i C1 and clamp capacitor current i Cc. Fig. 9c gives the experimental waveforms of gate voltage v S,gs, resonant current i Lr, capacitor current i C2 and diode current i D. The diode current i D equals zero when main switch S is turned on. The measured waveforms of gate voltage v S,gs, capacitor current i C2, diode current i D and inductor current i L2 are shown in Fig. 9d. When switch S turns on, the diode current i D ¼ 0 and i L2 ¼ i C2. If switch S turns off, the output inductor current i L2 ¼ i C2 þ i D. Fig. 9e illustrates the experimental results of drain voltages v S,ds and v Sa,ds, capacitor voltage v C1 and clamp capacitor voltage v Cc. The sum of drain voltages v S;ds þ v Sa;ds ¼ v C1 þ v Cc. When switch S turns off and auxiliary switch S a turns on, the clamp capacitor C c is resonant with magnetising inductor and resonant inductor. Fig. 9f gives the experimental waveforms of gate voltage v S,gs, clamp capacitor voltage v Cc and capacitor voltages v C1 and v C2. The average voltage value of capacitor C 2 equals the output voltage v o. Fig. 10a gives the experimental output voltage and output current under the step load variation between P o ¼ 60 W and P o ¼ 96 W. The measured output voltage and output current under the step load variation between P o ¼ 96 W and P o ¼ 156 W are shown in Fig. 10b. From the measured results in Fig. 10, the output voltage of the proposed converter is less sensitive to the load variations. To compare the circuit efficiency of the proposed converter and the conventional Cuk converter, Fig. 11 shows the measured efficiencies of the proposed converter and the hard switching Cuk converter. Based on Fig. 11, the proposed converter has better circuit efficiency. The measured efficiency of the proposed converter is about 88.5% at the rated output power (12V/14A). Fig. 12 shows the measured results of the proposed xconverter at the rated output power under the input AC source voltage v s ¼ 90 V rms. The ZVS feature of both switches in the proposed converter is also achieved. 6 Conclusion The operational principle, circuit design consideration and the implementation of a Cuk converter with active clamp buck-boost stage are presented in this paper. In the proposed circuit, the leakage inductance of the transformer is also used as one part of the resonant inductance to achieve ZVS operation of main and auxiliary switches. The advantages of the proposed ZVS Cuk converter are low switching losses on power semiconductors, low voltage stress on primary switches, low output inductor current ripple, and smaller transformer required, due to two quadrant core swing. The mathematical equations of the proposed converter in each of the operation stages are analysed. The design consideration of the proposed converter is also included. Finally the experimental results based on a prototype circuit with rated 170W output are provided to verify ZVS operation of both main and auxiliary switches. 7 Acknowledgment This work is supported by the National Science Council of Taiwan under Grant NSC 96-2221-E-224. 8 References 1 Canesin, C.A., and Barbi, I.: Novel zero-current-switching PWM converters, IEEE Trans. Ind. Electron., 1997, 44, (3), pp. 372 381 2 Hua, G., and Lee, F.C.: Soft-switching techniques in PWM converters, IEEE Trans. Ind. Electron., 1995, 42, (6), pp. 595 603 3 Xu, X., Khambadkone, A.M., Leong, T.M., and Oruganti, R.: A 1-MHz zero-voltage-switching asymmetrical half-bridge DC/DC converter: Analysis and Design, IEEE Trans. Power Electron., 2006, 21, (1), pp. 105 113 4 Choi, B., Lim, W., Bang, S., and Choi, S.: Small-signal analysis and control design of asymmetrical half-bridge DC DC converters, IEEE Trans. Ind. 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Signal Process., 2004, 51, (10), pp. 549 551 10 Mezaroba, M., Martins, D.C., and Barbi, I.: A ZVS PWM inverter with active voltage clamping using the reverse recovery energy of the diodes, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., 2005, 52, (10), pp. 2219 2226 182 IET Electr. Power Appl., Vol. 1, No. 2, March 2007