Variability in Sub-100nm SRAM Designs

Variability in Sub-100nm SRAM Designs Ray Heald & Ping Wang Sun Microsystems Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 1

Outline Background: Quick review of what is varying SRAM cell variability analysis SNM Write trip voltage Read current Sense amplifier analysis Combined sense amplifier and memory array analysis SRAM timing circuits Conclusions Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 2

Threshold Voltage, V T, Variability in High Performance Processes Table from ITRS Roadmap 2001[1] L (nm) 250 180 130 90 65 45 V t (mv) 450 400 330 300 280 200 -V t (mv) 21 23 27 28 30 32 -V t /V t 4.7% 5.8% 8.2% 9.3% 10.7% 16% Fewer dopant atoms makes V T control very difficult. 1/(Area) 0.5 dependence means more variation for the smallest transistors. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 3

Line Edge Roughness Becoming Variability Issue Transistor widths and lengths vary due to optical and etch limitations. Smallest transistors will have more variation with less total length or width for averaging. "LER (Line Edge Roughness) may become dominant for 32 nm channel length transistors." Croon, et. al. [2]. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 4

SRAM Sensitivity Most sensitive because: Row Addr Column Addr Row decoder Column 0 Column n Bit Bit Bit Bit M M M M M M M M M Column precharge Column mux Sense amps Write buffers R/W Dout Din Word m Word 0 Small signal analog levels are used together with logic level signals. The smallest viable transistors are used to minimize cell array area. Time available for sensing a memory cell's state is usually less than that necessary to achieve full logic level swing during read operation. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 5

SRAM Evaluation Needs Managing SRAM variability requires analysis and characterization of the SRAM memory cell and other critical circuitry. The remainder of this talk will examine: Memory cell evaluation, Sense amplifier offset evaluation, Combined memory cell and SA limitations and RAM timing circuitry. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 6

Memory Cell Needs Primary: Weakest cell is stable during worst case read operation. Write trip voltage is in reasonable range with worst case cell and voltage offsets. Usually low V cc and low temperature (with V T at its maximum) is most difficult. Minimum read current is enough for worst case read (including off cells bit leakage). Secondary: Standby current (array power). Off cell bit line current. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 7

Cell Stability: Static Noise Margin (SNM) Stability of SRAM cells is usually expressed as static noise margin (SNM): The maximum static noise source which can be tolerated without loss of state. Worst case SNM is during read operation with transfer gate (xsfr) conducting cell read current through memory cell's conducting NMOS pull down transistor (drive). Once sufficient to use Beta ratio W/L-drive:W/L-xsfr. Today with need to maximize margins, Monte Carlo simulation using statistical models is required. Expect SNM is most sensitive to drive and xsfr transistor with the PMOS sensitivity being least significant. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 8

Typical 6T Cell SNM Maximize A B SNM All simulations use U. C. Berkeley BPTM BSIM4 65 nm model [3]. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 9

SNM Simulation Background Good introduction of SNM simulation methods in Seevinck, et. al. [4] including equivalent circuits to rotate axis for Spice measurement. (See also: Bhavnagarwala, et.al.) Use cell inverter curves with the second curve mirrored about the 45 degree line through the origin. SNM is the side of the largest square which can be constructed between the two curves. Memory cell variations with process best analyzed separately from mismatch variations for large arrays. First quickly review normal distribution. Then examine process variations. Mismatch variations will follow. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 10

Normal Distribution Refresher Standard Normal (or Gaussian) Distribution: Density function p(x) = 1/(2 ) 0.5 * exp[(-x 2 )/2] - < x < mean = 0, standard deviation, = 1. Distribution function P(x) = - x p(z)dz probability z x. Distribution function of n identical units which must all work P n (x) = [P(x)] n. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 11

SNM Simulation: Process Process variations limited by foundry practices and standards. Usually wafers beyond a 2-3 sigma process window are rejected. Monte Carlo simulation with process variables for SNMmin(process) gives a more realistic result than process corner simulation. Better coverage of the process range. Avoids impossible corners such as P-fast ( T ox-min ) together with N-slow (T ox-max ). SNMmin(process)=SNM(mean) N (process)* (process) e. g. SNM = 123.1 mv, = 15.6 mv and N = 3, then SNMmin = 123.1 3 * 15.6 = 76.3 mv Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 12

SNM Varying V Tn & V Tp for all Xstrs Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 13

V T Variations Applied to Individual Transistors Pull-up V T ± 30 mv Driver V T ± 30 mv Xsfr V T ± 30 mv Dvr, xsfr & up xstrs V T ± 30 mv Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 14

SNM Variation with Temperature 100C, 125C and 175C SNM plots Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 15

SNM Simulation: Mismatch Note SNM squares not equal when mismatch is included. Hence, SNM = min [ SNM-A, SNM-B ]. Mismatch statistical variations cause a few of many identical circuits to fail on a die. A large circuit-pass sigma range and/or repair is needed to limit the yield loss. With process variations, fabrication specifications determine the range. For mismatch, the number of identical SRAM cells (or other sensitive circuit block) and expected electrical yield to specifications determine the appropriate sigma value. For large RAM blocks > 5 tolerance may be needed. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 16

Local Channel Length Variations Pull-up L ± 3 nm Driver L ± 3 nm Xsfr L ± 3 nm Dvr, xsfr & up xstrs L ± 3 nm Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 17

The Sigma Story Process variables are typically assumed to vary 3 unless otherwise stated in fabrication documentation. Why is 3 not sufficient for all statistical analysis? Gaussian statistics gives 99.73% of the distribution in the 3 range. Hence 2.7 in each 1,000 are outside the 3 range. SNM, I read and many other parameters only cause failure at one edge of range or 1.35 fail per 1,000. A 4MB cache usually contains almost 38 million memory cells. One unstable or unwritable cell in 38 million requires = 5.44 (low SNM or V trip edge only). Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 18

The Sigma Story-2 Mismatch variations for large arrays must be acceptable to 5 or beyond to achieve reasonable yield. Note statistical models of a new process are likely to be even more uncertain than the typical and corner models which may have been used previously. Simulations usually give a distribution of results close to a normal curve, so can use normal distribution functions. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 19

SNM Mismatch Example Say SNM(mean) = 123.1 mv, (SNM-mis) = 9.2 mv, and we require that no more than 1 cell in 3.5 million to have a SNM < SNM(min). Then we are requiring that N (SNM-mis) = 5, which results in SNM(min) = 77.1 mv. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 20

Write Trip Voltage, V trip Write trip voltage is primarily determined by V T of the NMOS xsfr transistor on the side being pulled low. Need the trip voltage far enough from the V cc or V ss that no combination of offsets and noise can cause a write failure. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 21

Write Trip Voltage Example Usually with a symmetric 6T memory cell V trip < V cc /2. Hence, worst case V ss offset plus noise, DV ss, gives V trip lower bound. As with SNM, the process variation range is fixed by fabrication specification while mismatch variation tolerance is determined by the number of cells or circuits used and the acceptable yield loss increase. Vtrip (mean) N (trip-mis) * (trip-mis) > DV ss Example: DV ss = 150 mv, V trip (mean) = 410 m, V and (trip-mis) = 44 mv, then N (trip-mis) = 5.91. This is about 1 in 5.8E08. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 22

Write Trip Voltage Example-2 Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 23

Cell Read Current While SNM and V trip evaluate cell functionality, the cell read current, I read, is a major component in determining array access time. SRAM 6T cell current is set by the series stack of NMOS transfer transistor and NMOS pull down transistor. The PMOS transistor is only a leakage path (source-drain and gate). I read Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 24

Cell Read Current Example With Iread (mean) and read (mis) from simulations: I read (min-mis) = I read (mean) N (I read -mis) * read (mis) Example: Iread (mean) = 100 ma, (I read -mis) = 6 ma, and I read (min) = 70 ma to meet timing. Then N (I read -mis) = 5 (1 cell in 3.5 million). For this set of read current parameters, a reasonable yield of a 4Mb array would require redundancy for replacing low Iread cells as well as non-functioning cells. Test & repair procedures must be capable of detecting and replacing these weak cells. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 25

Read Current with Repair Repair of the slowest 3-5 cells can significantly improve the yield to a fixed access time. Beyond a few cells the improvement is much more limited. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 26

Sense Amplifier, SA Sense amplifier: Converts the small signals from a memory cell (perhaps < 100 mv) to logic levels. Most involve carefully matched transistors designed to minimize I d and V T mismatches. Variations with sub 100 nm significant to array yield. Differential SA: Most rely on careful matching of NMOS differential pair. The V T mismatch is critical so all best historic layout matching practices feasible are used. Layout differential pair (usually at least NMOS) exactly the same (including current direction: 50% split best). Match all other layout as exact as practical & check with 1/2 design rule offset of each layer in all directions. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 27

Sense Amplifier-2 Current mode SA: Less sensitive to V T mismatch but sensitive to I d mismatch. Skewed inverter: Memory cell current gives a very slow voltage slew rate. Inverter trip point is much more sensitive than when used for standard logic. All sense amplifier types need statistical simulation with full number of bit line cells to determine effective SA input offset of the design. Verify that circuit timing with statistically weak cell can overcome this offset. New article: B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier, IEEE Journal of Solid-State Circuits, vol. 39, pp. 1148-1158, July 2004. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 28

Sense Amplifier Example Example: Drain fed differential SA. Critical mismatch is for NMOS differential pair just turning on when V in > V T (mismatch) [5]. Monte Carlo simulation is used with the fail condition measured as a function of DV in at SA-on time, sae. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 29

Sense Amplifier Example-2 Fail condition: Wrong output latched or correct output with inherent noise > maximum allowed is observed. sae : Unlikely that the time when SAE=V cc /2 is a good representation of sae. Most likely to be a time when SAE is just greater than V T. sae is likely to change with SAE slew rate. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 30

Sense Amplifier Example-3 Assume the circuit electrical yield is limited by high side bump with V bump < 200 mv required. Mismatch simulation is done with lowest FO and fast process corner for worst case bump. Assume: Large array using 20,000 identical sense amplifiers, DV in = 3 mv and (SA-mis) = 12.5 mv. Require likelihood of SA bump beyond limit ~1%. This is 1 fail in 2 million, satisfied by N (SA-mis) = 4.9. Then DV in (min) = 3 + 12.5 * 4.9 = 64.25 mv. Finally: verify that statistically weak cell meets timing with this offset. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 31

Critical Path Timing Yield to Max. Delay Involves both memory cell and sense amplifier variations. V min determined for a typical cell's critical path > 64.25 mv [using SA example's result]. How must this be adjusted to allow the low I read to cause a 64.25 mv differential in the maximum delay T max (I = 100 ma and (I) = 6 ma as before)? For I read (min-mis) = I read (mean) 5 * (I read -mis) Then DV in (min) = DV in (mean) + 4.9 * (SA-mis) / {I read (min-mis) / I read (mean)}. So DV in (min) = DV in (mean) + 4.9 * (SA-mis) / {1-5 * (I read -mis) / I read (mean)} = 90.5 mv. Note this is a worst case analysis with statistical limiting. The combined statistical analysis is best but adds simulation time. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 32

SRAM Timing Circuits-1 Reference memory cells, rows, and columns used for timing control are subject to the same statistical variations as the normal circuitry. Column 0 Column n Bit Bit Bit Bit M M M Row Addr Row decoder M M M M M M Word m Word 0 Column Addr Column precharge Column mux Sense amps Write buffers R/W Dout Din Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 33

SRAM Timing Circuits-2 The probability that a single reference is more than 2 away from the expected average is 4.5%. For a cell current reference, the number of cells used must be enough to a get good statistical mean. For a timing reference, the loading and exact structure of delay elements are still critical & must include the correct metal to device gate plus diffusion area ratio for good tracking. Good references are becoming more difficult with larger percent statistical variations in the 90 and 65 nm processes. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 34

SRAM Timing Circuits-3 Clock based timing: With single cycle throughput, only two of the three of usual critical timing signals can be timed from a clock edge. The third critical signal must be self-timed or coupled to a less accurate reference such as a DLL. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 35

Concluding Remarks Variation in device characteristics is becoming an acute problem for SRAM design. Circuit wide process variations of 2 to 3 are typical and will not decrease with future technologies. Within the die, local mismatch parameter variations are not decreasing as quickly as the parameters themselves. Meanwhile, the number of SRAM cells and other circuit blocks which must work on a chip is growing rapidly. Traditional mean and corner simulations must be supplemented with a number of statistical simulations to assure circuits will work and yield at the expected speed and reliability. Repair of slow cells must be made possible by design. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 36

Acknowledgments & Discussion Thanks to the Device Group at UC Berkeley for the very useful Berkeley Predictive Technology Model, BPTM, used in all simulations. http://www-device.eecs.berkeley.edu/~ptm Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, New paradigm of predictive MOSFET and interconnect modeling for early circuit design, Proc. of IEEE CICC, pp. 201-204, Jun. 2000. Discussion: Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 37

References [1] Semiconductor Industry Association (SIA), International Roadmap for Semiconductors 2001 edition, Austin Tx; International SEMITECH, 2001. Available: http://public.itrs.net. [2] J. Croon, et. al., "Line Edge Roughness Characterization, Modeling and Impact on Device Behavior," IEDM, Dec. 2002. [3] Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," Proc. of IEEE CICC, pp. 201-204, Jun. 2000. [4] E. Seevinck Sr., F. List, J. Lohstroh; Static-noise margin analysis of MOS SRAM cells, IEEE Journal of Solid-State Circuits, vol. 22, pp. 748-754, Oct. 1987. [5] A. Hajimiri, R. Heald, "Design Issues in Cross-Coupled Inverter Sense Amplifier," ISCAS Dig. of Technical Papers, May 1998. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 38

Other Related Articles-1 A. Bhavnagarwala, X. Tang, J. Meindl; The impact of intrinsic device fluctuations on CMOS SRAM cell stability, IEEE Journal of Solid-State Circuits, vol. 36, pp. 658-665, April 2001. K. Bowman, B. Austin, J. Eble, X. Tang, J. Meindl; A physical alpha-power law MOSFET model, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1410-1414, October 1999. K. Bowman, S. Duvall, J. Meindl; Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, vol. 37, pp. 183-190, February 2002. K. Bowman, X. Tang, J. Eble, J. Meindl; Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit performance, IEEE Journal of Solid-State Circuits, vol. 35, pp. 1186-1193, August 2000. D. Burnett, K. Erington, C. Subramanian, K. Baker; Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits, Proc. Symp. VLSI Tech., pp. 15-16, June 1994. J. Croon, M. Rosmeulen, S. Decoutere, W. Sansen, H. Maes; An easy-to-use mismatch model for the MOS transistor, IEEE Journal of Solid-State Circuits, vol. 37, pp. 1056-1064, August 2002. P. Drennan, C. McAndrew; A comprehensive MOSFET mismatch model, Proc. IEDM, pp. 167-170, 1999. J. Lohstroh, E. Seevinck, J. de Groot; Worst-case static noise margin criteria for logic circuits and their mathematical equivalence, IEEE Journal of Solid-State Circuits, vol. 18, pp. 803-807, December 1983. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 39

Other Related Articles-2 J. Meindl, V. De, D. S. Wills, J.. Eble, X. Tang, J. Davis, B. Austin, A. Bhavnagarwala; The impact of stochastic dopant and interconnect distributions on gigascale integration, IEEE International Solid-State Circuits Conference, vol. XL, pp. 232-233, February 1997. Y. Nakagome, M. Horiguchi, T. Kawahara, K. Itoh, Review and future prospects of low-power RAM circuits, IBM Journal of Research and Development, vol. 47, no. 5/6, pp. 525-552, September/November 2003. C. Michael, M. Ismail; Statistical modeling of device mismatch for analog MOS integrated circuits, IEEE Journal of Solid-State Circuits, vol. 27, pp. 154-166, February 1992. P. A. Stolk, F. P. Widdershoven, D. B. M. Klaassen; Modeling statistical dopant fluctuations in MOS transistors, IEEE Trans. Electron Devices, vol. 45, pp. 1960-1971, Sept. 1998. X. Tang, V. De, J. D. Meindl; Intrinsic MOSFET parameter fluctuations due to random dopant placement, IEEE Trans. VLSI Syst., vol. 5, pp. 369-376, Dec. 1997. X. Tang, V. K. De, J. D. Meindl; MOSFET fluctuation limits on gigascale integration (GSI), 1998 Eur. Solid- State Device Research Conf. (ESSDERC'98), Bordeaux, France, pp. 508-511, Sept. 1998. B. Wicht, T. Nirschl, D. Schmitt-Landsiedel, Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier, IEEE Journal of Solid-State Circuits, vol. 39, pp. 1148-1158, July 2004. S.-C. Wong, K.-H. Pan, D.-J. Ma; A CMOS mismatch model and scaling effects, IEEE Electron Device Lett., vol. 18, pp. 261-263, June 1997. Ray Heald & Ping Wang ICCAD 2004 Variability in Sub-100nm SRAM Designs 11/9/04 40