Design Rules for Silicon Photonic Packaging at Tyndall Institute

Design Rules for Silicon Photonic Packaging at Tyndall Institute January 2015

About Tyndall Institute Established with a mission to support industry and academia in driving research to market, Tyndall National Institute is one of Europe s leading research centers in Information and Communications Technology (ICT) research and development, and the largest research facility of its type in Ireland. Hosting the only full CMOS, Micro-Electronic-Mechanical Systems (MEMS) and III-V Wafer Semiconductor fabrication facilities and services in Ireland, Tyndall is capable of prototyping new product opportunities for its target industries - electronics, medical devices, energy and communications. Tyndall is a globally leading Institute in its four core research areas of Photonics, Microsystems, Micro/Nanoelectronics and Theory Modeling & Design. About IPIC (Irish Photonic Integration Centre) The Irish Photonic Integration Centre (www.ipic.ie) is a new 30million research centre funded Science Foundation Ireland (SFI). IPIC brings together over 100 researchers from four institutes across Ireland to develop new light-enabled technologies. Targeting the ICT and medical devices sectors, IPIC is working with 18 industry partners to develop the next generation of highly-compact and miniaturized photonic technologies. The Centre s work is focused on revolutionizing the speed of data transfer through faster more energy efficient devices and delivering new smart medical devices for improved diagnosis and treatment of disease. Photonics Packaging Group The Photonics Packaging Group at Tyndall is involved in a wide range of international academic and industry projects, with a special focus on packaging and integration for silicon photonics. The group has extensive design, packaging, testing and reliability-testing facilities. Key capabilities include; optical, mechanical, thermal and electrical design, fibre-coupling (single-fibre and fibrearrays), flip-chip integration of both photonic and electronic devices, jetting of micro solder spheres, active alignment of micro-optical benches, high-speed testing, reliability-lifetime-failure analysis of packaged photonic devices.

Contents 1.0 Introduction Page 1 2.0 Optical Packaging Page 2 2.1 Grating Couplers Page 2 2.2 Edge Couplers Page 4 3.0 Electrical Packaging Page 5 3.1 DC Interconnection Page 5 3.2 RF Interconnection Page 5 4.0 Thermal Management Page 7 5.0 Custom Packaging Solutions Page 8 5.1 Solder-Ball-Bump & Flip-chip of electronic ICs onto PICs Page 8 5.2 Micro-Optical Bench (MOB) Page 9 5.3 Flip-chip fiber to grating-coupler packaging Page 9 5.3 Flip-chip of VCSELs onto PICs Page 9 6.0 Contact Page 10

1.0 Introduction Photonics packaging covers the optical-, electronic- and thermal-coupling of photonics integrated circuits (PICs) to the outside world. To ensure that your PICs can be packaged efficiently and reproducibly at Tyndall, we have developed the following silicon photonics packaging design rules (PDRs). These design rules specify the acceptable dimensions and locations of optical and electronic input/output ports on the Si-PIC, with respect to the physical footprint of the PIC-die. Tyndall offers both standard and custom packaging services to users. Standard-packaging services are commercially available to industry and research partners, while custom-packaging services (Section 5) are typically offered in terms of a collaborative development project. Standard photonics packaging services available at Tyndall include: Optical-coupling of fibers-to-pic (Section 2) Electronic-coupling of PIC-to-PCB using wire-bonding (Section 3) Thermal modeling & characterization of packaged PICs (Section 4) To facilitate clear discussions with the user, we use a compass-coordinate system to unambiguously label each side of the PIC-die. We can provide packaging solutions to all standard PIC-dies, including the miniphotonic blocks from IMEC and CEA-Leti, provided the PDRs are followed. To facilitate low-cost packaging for the user, we have developed a generic Tyndall-PCB that allows for optical-coupling to/from the West-side and East-side of the PIC-die, 2 10 DC electronic connections on the North-side and South-side of the PIC-die, and includes an integrated thermistor for feedback to an optional thermo-electric controller (TEC). To use the Tyndall-PCB, please ensure that your PIC-die has a footprint between 9.0mm 5.5mm and 5.0mm 3.0mm. Figure 1 (a) Compass coordinate system used to unambiguously label the four sides of the PIC-die. (b) Schematic of the Tyndall- PCB showing the 2 10 DC connections and West/East fiber access. (c) A planar fiber-array single-side coupled to a Si-PIC mounted on the Tyndall-PCB. Note the TEC between the PCB and the mechanical aluminum mount. Page 1

2.0 Optical Packaging Tyndall works to offer a flexible range of optical-coupling solutions to their users. We can package single-fiber or fiber-arrays; single-mode fibers (SMFs) or polarization maintaining fibers (PMFs); and work with either grating-coupler or edge-coupler schemes. The more relaxed optical alignment tolerances of grating-couplers, compared to edge-couplers, often makes them the preferred choice for optically-packaging PICs. However, for optical-packaging of edge-emitting laser-chips, or opticallybroadband / polarization-agnostic PICs, edge-coupling can be the better choice. Whatever their choice, the user must carefully follow the following PDRs, to ensure that their Si-PIC can be optically-packaged. 2.1 Grating Couplers For fiber-array to grating-array coupling, Tyndall can package using either a planar geometry, or pigtail geometry - see Figure 2(b) & 2(c). We recommend using the planar geometry whenever possible (especially for single-fiber coupling), because it offers better mechanical stability, and significantly reduces the bulk of the packaged unit. In both planar and pigtail geometries, it is important to ensure that the optical-mode is incident on the grating-coupler at the correct angle-of-incidence (AOI) for optimum coupling-efficiency at the target-wavelength of the Si-PIC design. We offer single-fibers and pigtail fiber-arrays with AOI = 8deg or 10deg geometries, and planar fiber-arrays with AOI = 10deg. Figure 2 (a) Regardless of the coupling geometry being used, grating-arrays should be centered with respect to the PIC-die. (b) A simple schematic of the pigtail fibre-coupling geometry. (c) A simple schematic of the planar fibre-coupling geometry. Page 2

For standard-packaging services, Tyndall uses active optical-feedback to align fibers to grating-couplers. In order to package a fiber-array to grating-coupler array, the user must ensure the following: All grating-couplers are arranged in a straight line, parallel to the edge of the PIC-die The grating-coupler array(s) should be centered with respect to the PIC see Figure 2(a) The first and last grating-couplers in the array form an optical shunt see Figure 3(c) The pitch of the grating-coupler array (P G) matches the fiber diameters see Figure 3(c) As a result of the optical shunt, if a user requires N fiber-channels for PIC operation, then they must include N+2 grating-couplers in their grating-coupler array. For packaging with the planar geometry, Tyndall can only accommodate single-mode fiber-arrays, and requires P G = 250µm. For packaging with the pigtail geometry, Tyndall can accommodate both single-mode and polarization-maintaining fiberarrays, and can work with P G = 250µm or 127µm. To ensure a stable mechanical- and optical-connection, there must be sufficient contact area between the fibers and PIC-die during the application of the UV-cured epoxy-bond - see Figure 3(a) & 3(b). We strongly recommend that single grating-couplers and grating-coupler arrays be located 1.0mm from the edge of the PIC-die, and we require that they be no closer than 0.5mm from edge of the PIC-die. Figure 3 (a) Side-view of a pigtail fiber-array being coupled to a Si-PIC, showing the effect of over-shadowing from the endcap, which creates a large exclusion zone for electronic connections. (b) Side-view of a planar fiber-array being coupled to a Si-PIC, showing the area needed for epoxy-bonding, and where epoxy may flow onto the PIC surface. (c) Schematic of a gratingcoupler array designed for coupling to a fiber-array. The pitch of the grating-coupler array must match the dimensions of the fibers, and the first and last channels must be reserved for optical alignment during packaging. The schematic also shows a plan view of the exclusion zones for electrical connections, depending on the whether planar of pigtail geometry is used. Page 3

The area bounded by (i) the North-South line on which the grating-coupler(s) lie, and (ii) the nearest edge of the PIC-die is an exclusion zone for electronic bond-pads, because it is liable to be covered by bonding-epoxy see Figure 3(c). For fiber-arrays in the pigtail geometry, over-shadowing from the polished end-caps extends this exclusion-zone by 1.4mm towards the center of the PIC-die see Figure 3(a). For fiber-arrays in the planar geometry, this exclusion-zone extends by 0.5mm, to allow for epoxyflow - see Figure 3(b). No electronic bond-pads should be located in the exclusion zone, but integrated PIC components that are not negatively affected by the presence of epoxy can still be added. 2.2 Edge Couplers The alignment tolerances for edge-coupling are more stringent than for grating-coupling. This reduces the flexibility and variety of packaging solutions that Tyndall can provide. For single-fiber edge-coupling to a laser-chip, we offer an f = 10µm lensed-fiber, mounted in a metallic ferrule, locked into the optimum alignment position by means of laser-welding (to a Kovar Butterfly-package). For single-fiber edge-coupling to a PIC, Tyndall offers two options: Optical-packaging with a lensed fiber to an inverted-taper on the PIC Optical-packaging with a flat fiber to a 10µm mode-converter on the PIC We do not provide a PIC-die polishing service, and we do not provide post-processing to add modeconverter structures. It is the responsibility of the user to ensure that their edge-coupler structure is sufficiently close to the edge of the PIC-die to allow for fiber access. Tyndall does not yet offer fiberarray edge-coupling packaging, as part of our standard-packaging services. Page 4

3.0 Electrical Packaging Electronic connections between the Si-PIC and PCB are made by wire-bonding. To ensure reproducible and high-quality wire-bonding, the location and pitch of the bond-pads on the PIC must be controlled. Tyndall requires that optical- and electronic-coupling not be made from the same side of the PIC-die. By default, bond-pads are located along the North- and South-side edges of the PIC-die. If it is not being used for optical-coupling, then bond-pads can also be placed along the East-side edge of the PIC-die. When a Si-PIC design calls for DC and RF electrical-connections, we recommend locating all DC bondpads along one edge of the PIC-die (i.e. along the North-side), and all RF bond-pads along the other edge (i.e. along the South-side). Regardless of type, bond-pad array should be centered with respect to the PIC see Figure 4(a) and be located just 100µm from the edge of the PIC-die - see Figure 4(b). This condition ensures that the wire-bonds are drawn down to the PCB bond-pads with an optimum turnradius that maximizes the mechanical stability of the wire-bond. 3.1 DC Interconnection DC bond-pads on the Si-PIC should be 100µm 100µm, and be separated by a pitch of P DC = 200µm. We recommend against staggering bond-pads on the PIC, because it increases the likelihood of shorting between adjacent wire-bonds. We will accommodate staggered bond-pads, if necessary, but please allow for additional delivery times/costs, as well as potentially lower yields - see Figure 4(d). Users wanting to avail of the Tyndall-PCB should set P DC = 200-300um in their designs see Figure 4(b). 3.2 RF Interconnection RF bond-pads on the Si-PIC should also be 100µm 100µm in size, but should be separated by a pitch (P RF) that closely matches the pitch of the RF lines on the connecting interposer/pcb (P PCB). This ensures that the parallel series of wire-bonds can be drawn between the PIC and the PCB, reducing induction effects and the likelihood of shorting to adjacent wire-bonds. The minimum P PCB for RF lines on the Rogers-layer of a PCB is typically 300µm, and so we recommend P RF = 300µm. However, this is only a recommendation - it is the responsibility of the user to ensure that that P RF = P PCB for their RF interposer/pcb. To avoid the crossing of wire-bonds, users must ensure that the order of RF bond-pads on the PIC coincides with the order of the RF lines on the PCB. Typical layouts for co-planar high-speed single-end and differential RF lines on the Rogers layer of a PCB are as follows: Single-End RF Ground / Signal / Ground Differential RF Ground / Signal(+) / Ground / Signal(-) / Ground To minimize noise and induction effects, the user should ensure that the RF bond-pads on the PIC coincide with the type of RF lines arriving from the PCB see Figure 4(c). Page 5

Page 6 Figure 4 (a) Bond-pads for electronic-coupling must be located along the North- and South-sides of the PIC-die, and centered with respect to the PIC-die. (b) The critical dimensions and locations of the DC and RF bond-pads on the PIC with respect to the edge of the PIC-die. (c) An example of a good match between P RF and P PCB ensuring straight wire-bonds with a low-risk of shorting. (d) An example of staggered bond-pads on the PIC demonstrating a high risk of shorting.

4.0 Thermal Management The thermal behavior of a packaged Si-PIC can impact the performance, stability, and life-time of the device. Tyndall uses a combination of thermal modeling and temperature measurements to characterize the thermal behavior of a packaged PIC. We can also advise users on the need/benefit of using a thermo-electric controller (TEC) in their packed system. 4.1 Thermal Modeling Tyndall uses COMSOL modeling to understand the transient and steady-state temperatures and thermal-gradients in packaged Si-PICs see Figure 5. The fidelity of this modeling is tested (and refined) using feedback from time-resolved temperature measurements of the PIC, PCB, and housing of the packaged module. The results of our modeling can help users fine-tune the design of the temperaturesensitive integrated-components in their PIC (such as micro-ring resonators), to ensure optimum performance in the packaged module. The COMSOL modeling also helps users determine if a TEC is needed to keep their packed PIC design within its nominal operating limits. 4.2 Thermal Design If thermal modeling of the Si-PIC shows that the temperature of key integrated-components could exceed some operational threshold, or if it takes too long for the PIC to stabilize at its steady-state temperature after turn-on, then adding a TEC to the packaged system can improve the PIC performance. Tyndall can carry-out performance testing of a PICs stabilized by TECs operating in free-running mode, and with PID control. For these TEC tests, we recommend that users take advantage of the standard Tyndall-PCB, because it is designed from the ground up to accommodate a TEC, and includes an integrated thermistor for temperature-feedback. Figure 5 (a) Meshing the physical layout of an electronic-ic on a Si-PIC, mounted onto a Peltier-cooler for TEC, for a COMSOL simulation. (b) Results of a COMSOL simulation showing the thermal gradients in a packaged electronic-ic flip-chipped onto a Si-PIC. (c) Image of single-fiber edge-coupled to Silicon Photonic device with a custom-package for thermal control. Page7

5.0 Custom Packaging Services Tyndall is constantly working to develop technology that improves the efficiency and lowers the cost of optical- and electronic-packaging. These advanced photonics packaging solutions may not yet be mature enough to offer commercially as standard services, but we are open to offering them to companies and research partners, in terms of collaborative development projects. 5.1 Solder-Ball-Bump & Flip-chip of electronic ICs onto PICs For high-speed RF photonic devices, the physical length of the electrical connections between the electronic-ic (EIC) and PIC should be minimized. Tyndall offers direct EIC-to-PIC bonding, using a PacTech solder-ball-bumper (SB2), and a FineTech flip-chip system. The SB2 can rapidly apply 50µm solder-balls to an extended 2D array of Au-finished bond-pads on the PIC, which are then aligned with respect to their corresponding bond-pads on the EIC, using the flip-chip system see Figure 6. The EIC and PIC are then brought into contact, and electrically- and mechanically-bonded together by solder reflow at 250 C. For solder-ball-bump & flip-chip packaging, the bond-pads on the PIC and EIC should both be 50µm 50µm in size, and be separated by a pitch of 100µm. To ensure good adhesion of the solder ball to the bond-pad, the Au-thickness on the pads should be at least 500nm. Figure 6 (a) For solder-ball-bump & flip-chipping of EICs onto PICs, the bond-pads should be 50µm 50µm in size, with a pitch of 100µm. (b) An image of flip-chip integration of an electronic-ic on a Silicon Photonic device using solder spheres. (c) An image of fully packaged photonic system a TEC-cooled Si-PIC onto which an electronic-ic has been flip-chip-integrated, using solder spheres, all mounted in a custom RF PCB. Page 8

5.2 Micro-Optical Bench for Laser Integration Tyndall has developed a micro-optical bench system that consists of a laser-chip (or SOA), a micro-lens and a microprism, all mounted on a ceramic base that can be mounted on top of a Si-PIC. Light from the laser-chip is collected and collimated by the micro-lens and then directed by the microprism down towards the PIC with AOI = 10deg, where it can be aligned onto a grating-coupler. The physical dimensions of the micro-optical bench are 1.4mm 1.1mm 0.55mm. The micro-bench has applications for launching light into Si-PICs for sensing and optical-encoding, and also for creating a tunable laser-source, using optical feedback from the PIC. 5.3 Flip-chip fiber to grating-coupler packaging Active optical alignment of fibers to gratingcouplers is a relatively slow process, involving significant input/control from a human operator. Tyndall has recently developed a method of passively aligning fiber-arrays to grating-coupler arrays, using a flip-chip technique. This procedure is faster and more reproducible than active optical alignment, and has an average performance penalty of just 0.5dB with respect to active alignment. We are working to reduce this performance penalty even further, with the aim of making high-throughput passive alignment of fiberarrays a reality. 5.4 Flip-chip of VCSELs onto PICs Hybrid integration of III-V laser sources onto Si-PICs is important for developing active PICs. Tyndall can accurately align single VCSELs onto SOI grating-couplers, using its FineTech flip-chip system. We have developed a low-cost technology that enables us to introduce a tilt in the VCSEL mounting, to ensure the laser-mode is incident on the grating-coupler with the correct AOI for optimum coupling efficiency. We are currently working to further increase the coupling efficiency of light from the VCSEL into the Si-PIC, by customizing the grating-couplers to better match the modeprofile of the VCSEL. Page 9

6.0 Contact The goal of the packaging design rules in this document is to help users better access the photonic packaging solutions provided by Tyndall. By following our design-rules, and adopting our designsuggestions, users can significantly reduce the time and cost of packaging their Si-PICs at Tyndall. If you need clarification or further information about the photonics packaging services available at Tyndall, then please contact Lee Carroll or Peter O Brien: Dr. Lee Carroll Photonics Packaging Group Tyndall National Institute Lee Maltings Complex Cork, Ireland. Lab: +353 21 234 6434 Mob: +353 89 230 8500 lee.carroll@tyndall.ie www.tyndall.ie Dr. Peter O Brien (Head of Group) Photonics Packaging Group Tyndall National Institute Lee Maltings Complex Cork, Ireland. Lab: + 353 21 234 6841 Mob: + 353 87 921 3309 peter.obrien@tyndall.ie www.tyndall.ie Page 10