TL70L, TL7L SERIES LOW-DROPOUT OLTAGE REGULATORS SLS07P SEPTEMBER 987 REISED FEBRUARY 2003 ery Low Dropout oltage, Less Than 0.6 at 0 ma ery Low Quiescent Current TTL- and CMOS-Compatible Enable on TL7L Series 60- Load-Dump Protection Reverse Transient Protection Down to 0 Internal Thermal-Overload Protection Overvoltage Protection Internal Overcurrent-Limiting Circuitry Less Than 00-µA Disable (TL7L Series) TL70L...D PACKAGE (TOP IEW) TL70L... KC PACKAGE (TOP IEW) TL70L... KTE PACKAGE (TOP IEW) OUTPUT 2 3 4 8 7 6 INPUT OUTPUT INPUT OUTPUT INPUT No internal connection TL70L... LP PACKAGE (TOP IEW) TL70L...P PACKAGE (TOP IEW) TL7L...D PACKAGE (TOP IEW) INPUT OUTPUT OUTPUT 2 3 4 8 7 6 INPUT OUTPUT 2 3 4 8 7 6 INPUT ENABLE TO-226AA No internal connection No internal connection TL7L...P PACKAGE (TOP IEW) OUTPUT 2 3 4 8 7 6 INPUT ENABLE description/ordering information No internal connection The TL70L and TL7L series of fixed-output voltage regulators offers -, 8-, 0-, and 2- options. The TL7L series also has an enable (ENABLE) input. When ENABLE is high, the regulator output is placed in the high-impedance state. This gives the designer complete control over power up, power down, or emergency shutdown. The TL70L and TL7L series are low-dropout positive-voltage regulators specifically designed for battery-powered systems. These devices incorporate overvoltage and current-limiting protection circuitry, along with internal reverse-battery protection circuitry to protect the devices and the regulated system. The series is fully protected against 60- load-dump and reverse-battery conditions. Extremely low quiescent current during full-load conditions makes these devices ideal for standby power systems. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated
TL70L, TL7L SERIES LOW-DROPOUT OLTAGE REGULATORS SLS07P SEPTEMBER 987 REISED FEBRUARY 2003 description/ordering information (continued) ORDERING INFORMATION TJ O TYP AT 2 C PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING POWER-FLEX (KTE) Reel of 2000 TL70L0CKTER TL70L0C Tube of 7 TL70L0CD 0L0C Reel of 200 TL70L0CDR SOIC (D) Tube of 7 TL7L0CD L0C Reel of 200 TL7L0CDR TO-92 (LP) Bulk of 000 TL70L0CLP Reel of 2000 TL70L0CLPR 70L0C TO-220 (KC) Tube of 0 TL70L0CKC TL70L0C Tube of 7 TL70L08CD SOIC (D) 8 Reel of 200 TL70L08CDR 0L08C TO-92 (LP) Bulk of 000 TL70L08CLP 70L08C 0 C to 2 C PDIP (P) Tube of 0 TL7L0CP TL7L0C 0 2 SOIC (D) TO-92 (LP) SOIC (D) Tube of 7 Reel of 200 Tube of 7 Reel of 200 Bulk of 000 Reel of 2000 Tube of 7 Reel of 200 Tube of 7 Reel of 200 TL70L0CD TL70L0CDR TL7L0CD TL7L0CDR TL70L0CLP TL70L0CLPR TL70L2CD TL70L2CDR TL7L2CD TL7L2CDR 0L0C L0C 70L0C 0L2C L2C TO-92 (LP) Bulk of 000 TL70L2CLP 70L2C Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available www.ti.com/sc/package. DEICE COMPONENT COUNT Transistors 20 JFETs 2 Diodes Resistors 6 2
TL70L, TL7L SERIES LOW-DROPOUT OLTAGE REGULATORS SLS07P SEPTEMBER 987 REISED FEBRUARY 2003 absolute maximum ratings over operating junction temperature range (unless otherwise noted) Continuous input voltage.................................................................... 26 Transient input voltage, T A = 2 C (see Note )................................................ 60 Continuous reverse input voltage........................................................... Transient reverse input voltage, t 00 ms................................................... 0 Package thermal impedance, θ JA (see Notes 2 and 3): D package............................ 97 C/W (see Notes 2 and 4): KC package........................... 2 C/W (see Notes 2 and 4): KTE package......................... 23 C/W (see Notes 2 and 3): LP package.......................... 6 C/W (see Notes 2 and 3): P package............................ 8 C/W Operating virtual junction temperature, T J................................................... 0 C Lead temperature,6 mm (/6 inch) for 0 seconds........................................ 260 ma Storage temperature range, T stg................................................... 6 C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The transient input voltage rating applies to the waveform shown in Figure. 2. Maximum power dissipation is a function of TJ(max), θja, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) TA)/θJA. Operating at the absolute maximum TJ of 0 C can affect reliability. 3. The package thermal impedance is calculated in accordance with JESD -7. 4. The package thermal impedance is calculated in accordance with JESD -. recommended operating conditions over recommended operating junction temperature range (unless otherwise noted) I Input voltage MIN MAX UNITS TL7xL0 6 26 TL7xL08 9 26 TL7xL0 26 TL7xL2 3 26 IH High-level ENABLE input voltage TL7Lxx 2 IL Low-level l ENABLE input voltage TJ = 2 C TL7Lxx 0.3 0.8 TJ = 0 C to 2 C TL7Lxx 0. 0.8 IO Output current range TL7xLxx 0 0 ma TJ Operating virtual junction temperature TL7xLxxC 0 2 C The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet for ENABLE voltage levels and temperature only. 3
TL70L, TL7L SERIES LOW-DROPOUT OLTAGE REGULATORS SLS07P SEPTEMBER 987 REISED FEBRUARY 2003 electrical characteristics, I = 4, I O = 0 ma, T J = 2 C (unless otherwise noted) PARAMETER TEST CONDITIONS TL70L0 TL7L0 MIN TYP MAX Output voltage I =6to26, IO = 0 to 0 ma TJ = 2 C 4.80.2 TJ = 0 C to 2 C 4.7.2 Input regulation voltage I = 9 to 6 0 I = 6 to 26 6 30 UNIT m Ripple rejection I = 8 to 8, f = 20 Hz 60 6 db Output regulation voltage IO = ma to 0 ma 20 0 m Dropout voltage IO = 0 ma 0.2 IO = 0 ma 0.6 Output noise voltage f = 0 Hz to 00 khz 00 µ IO = 0 ma 0 2 Input bias current I = 6 to 26, IO = 0 ma, TJ = 0 C to 2 C 2 ma ENABLE > 2 0. Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.-µF capacitor across the input and a 0-µF capacitor, with equivalent series resistance of less than 0.4 Ω, across the output. electrical characteristics, I = 4, I O = 0 ma, T J = 2 C (unless otherwise noted) PARAMETER TEST CONDITIONS TL70L08 TL7L08 MIN TYP MAX Output voltage I =9to26, IO = 0 to 0 ma TJ = 2 C 7.68 8 8.32 TJ = 0 C to 2 C 7.6 8.4 Input regulation voltage I = 0 to 7 0 20 I = 9 to 26 2 0 UNIT m Ripple rejection I = to 2, f = 20 Hz 60 6 db Output regulation voltage IO = ma to 0 ma 40 80 m Dropout voltage IO = 0 ma 0.2 IO = 0 ma 0.6 Output noise voltage f = 0 Hz to 00 khz 00 µ IO = 0 ma 0 2 Input bias current I = 9 to 26, IO = 0 ma, TJ = 0 C to 2 C 2 ma ENABLE > 2 0. Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.-µF capacitor across the input and a 0-µF capacitor, with equivalent series resistance of less than 0.4 Ω, across the output. 4
TL70L, TL7L SERIES LOW-DROPOUT OLTAGE REGULATORS SLS07P SEPTEMBER 987 REISED FEBRUARY 2003 electrical characteristics, I = 4, I O = 0 ma, T J = 2 C (unless otherwise noted) PARAMETER TEST CONDITIONS TL70L0 TL7L0 MIN TYP MAX Output voltage I =to26, IO = 0 to 0 ma TJ = 2 C 9.6 0 0.4 TJ = 0 C to 2 C 9. 0. Input regulation voltage I = 2 to 9 0 2 I = to 26 30 60 Ripple rejection I = 2 to 22, f = 20 Hz 60 6 db Output regulation voltage IO = ma to 0 ma 0 00 m Dropout voltage IO = 0 ma 0.2 IO = 0 ma 0.6 Output noise voltage f = 0 Hz to 00 khz 700 µ IO = 0 ma 0 2 Input bias current I = to 26, IO = 0 ma, TJ = 0 C to 2 C 2 ma ENABLE > 2 0. Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.-µF capacitor across the input and a 0-µF capacitor, with equivalent series resistance of less than 0.4 Ω, across the output. electrical characteristics, I = 4, I O = 0 ma, T J = 2 C (unless otherwise noted) PARAMETER TEST CONDITIONS TL70L2 TL7L2 MIN TYP MAX Output voltage I =3to26, IO = 0 to 0 ma TJ = 2 C.2 2 2.48 TJ = 0 C to 2 C.4 2.6 Input regulation voltage I = 4 to 9 30 I = 3 to 26 20 40 Ripple rejection I = 3 to 23, f = 20 Hz 0 db Output regulation voltage IO = ma to 0 ma 0 20 m Dropout voltage IO = 0 ma 0.2 IO = 0 ma 0.6 Output noise voltage f = 0 Hz to 00 khz 700 µ IO = 0 ma 0 2 Input bias current I = 3 to 26, IO = 0 ma, TJ = 0 C to 2 C 2 ma ENABLE > 2 0. Pulse-testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account separately. All characteristics are measured with a 0.-µF capacitor across the input and a 0-µF capacitor, with equivalent series resistance of less than 0.4 Ω, across the output. UNIT m UNIT m
TL70L, TL7L SERIES LOW-DROPOUT OLTAGE REGULATORS SLS07P SEPTEMBER 987 REISED FEBRUARY 2003 TYPICAL CHARACTERISTICS i Transient Input oltage 60 0 40 30 20 TRANSIENT INPUT OLTAGE vs TIME ÎÎÎÎ tr = ms TA = 2 C I = 4 + 46e( t/0.230) for t ms Input Current ma I I 40 3 30 2 20 0 TL70L0 INPUT CURRENT vs INPUT OLTAGE 0 0 0 00 200 300 400 00 600 t Time ms 0 0 2 3 4 6 I Input oltage Figure Figure 2 60 TL70L2 INPUT CURRENT vs INPUT OLTAGE 0 Input Current ma 40 30 20 I I 0 0 0 2 4 6 8 0 2 4 I Input oltage Figure 3 6
TL70L, TL7L SERIES LOW-DROPOUT OLTAGE REGULATORS TYPICAL CHARACTERISTICS SLS07P SEPTEMBER 987 REISED FEBRUARY 2003 Ω ESR Equivalent Series Resistance.0 0.9 0.8 0.7 0.6 0. 0.4 0.3 0.2 TL70L0 EQUIALENT SERIES RESISTAE vs LOAD CURRENT CL = 0-µF Tantalum Capacitor TA = 40 C to 2 C Potential Instability Region Region of Best Stability 0. 0.024 Potential Instability Region 0 0 0 80 20 0 IL Load Current ma Figure 4 7
MECHANICAL DATA MCER00A JANUARY 99 REISED JANUARY 997 JG (R-GDIP-T8) CERAMIC DUAL-IN-LINE 0.400 (0,6) 0.3 (9,00) 8 0.280 (7,) 0.24 (6,22) 4 0.06 (,6) 0.04 (,4) 0.063 (,60) 0.0 (0,38) 0.020 (0,) MIN 0.30 (7,87) 0.290 (7,37) 0.200 (,08) MAX Seating Plane 0.30 (3,30) MIN 0.00 (2,4) 0.023 (0,8) 0.0 (0,38) 0.04 (0,36) 0.008 (0,20) 0 404007/C 08/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a ceramic lid using glass frit. D. Index point is provided on cap for terminal identification. E. Falls within MIL STD 83 GDIP-T8
MECHANICAL DATA MLCC006B OCTOBER 996 FK (S-CQCC-N**) 28 TERMINAL SHOWN LEADLESS CERAMIC CHIP CARRIER 8 7 6 4 3 2 NO. OF TERMINALS ** MIN A MAX MIN B MAX 9 20 0.342 (8,69) 0.38 (9,09) 0.307 (7,80) 0.38 (9,09) A SQ B SQ 20 2 22 23 24 2 26 27 28 2 3 4 0 9 8 7 6 28 44 2 68 84 0.442 (,23) 0.640 (6,26) 0.739 (8,78) 0.938 (23,83).4 (28,99) 0.48 (,63) 0.660 (6,76) 0.76 (9,32) 0.962 (24,43).6 (29,9) 0.406 (0,3) 0.49 (2,8) 0.49 (2,8) 0.80 (2,6).047 (26,6) 0.48 (,63) 0.60 (4,22) 0.60 (4,22) 0.88 (2,8).063 (27,0) 0.020 (0,) 0.00 (0,2) 0.080 (2,03) 0.064 (,63) 0.020 (0,) 0.00 (0,2) 0.0 (,40) 0.04 (,4) 0.04 (,4) 0.03 (0,89) 0.028 (0,7) 0.022 (0,4) 0.00 (,27) 0.04 (,4) 0.03 (0,89) 404040/ D 0/96 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. This package can be hermetically sealed with a metal lid. D. The terminals are gold plated. E. Falls within JEDEC MS-004
MECHANICAL DATA MPDI00A JANUARY 99 REISED JUNE 999 P (R-PDIP-T8) PLASTIC DUAL-IN-LINE 8 0.400 (0,60) 0.3 (9,02) 0.260 (6,60) 0.240 (6,0) 4 0.070 (,78) MAX 0.020 (0,) MIN 0.32 (8,26) 0.300 (7,62) 0.0 (0,38) 0.200 (,08) MAX Gage Plane Seating Plane 0.2 (3,8) MIN 0.00 (0,2) NOM 0.02 (0,3) 0.0 (0,38) 0.00 (2,4) 0.00 (0,2) M 0.430 (0,92) MAX 4040082/D 0/98 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-00 For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
MECHANICAL DATA MPFM00E OCTOBER 994 REISED JANUARY 200 KTE (R-PSFM-G3) PowerFLEX PLASTIC FLANGE-MOUNT 0.37 (9,2) 0.36 (9,27) 0.360 (9,4) 0.30 (8,89) 0.220 (,9) NOM 0.080 (2,03) 0.070 (,78) 0.00 (,27) 0.040 (,02) 0.00 (0,2) NOM 0.420 (0,67) 0.40 (0,4) 0.29 (7,49) NOM 0.320 (8,3) 0.30 (7,87) 0.360 (9,4) 0.30 (8,89) Thermal Tab (See Note C) 3 0.00 (2,4) 0.200 (,08) 0.02 (0,63) 0.03 (0,79) 0.00 (0,2) M Seating Plane 0.004 (0,0) 0.00 (0,3) 0.00 (0,03) 0.00 (0,2) NOM Gage Plane 0.04 (,04) 0.03 (0,79) 3 6 0.00 (0,2) 407337/F 2/00 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. The center lead is in electrical contact with the thermal tab. D. Dimensions do not include mold protrusions, not to exceed 0.006 (0,). E. Falls within JEDEC MO-69 PowerFLEX is a trademark of Texas Instruments.
MECHANICAL DATA MSOI002B JANUARY 99 REISED SEPTEMBER 200 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 8 PINS SHOWN 0.00 (,27) 0.020 (0,) 0.04 (0,3) 0.00 (0,2) 8 0.244 (6,20) 0.228 (,80) 0.008 (0,20) NOM 0.7 (4,00) 0.0 (3,8) Gage Plane 4 A 0 8 0.00 (0,2) 0.044 (,2) 0.06 (0,40) Seating Plane 0.069 (,7) MAX 0.00 (0,2) 0.004 (0,0) 0.004 (0,0) DIM PINS ** 8 4 6 A MAX 0.97 (,00) 0.344 (8,7) 0.394 (0,00) A MIN 0.89 0.337 (4,80) (8,) 0.386 (9,80) 4040047/E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,). D. Falls within JEDEC MS-02
MECHANICAL DATA MSOT002A OCTOBER 994 REISED NOEMBER 200 LP (O-PBCY-W3) PLASTIC CYLINDRICAL PACKAGE 0.20 (,2) 0.6 (4,9) DIA 0.7 (4,44) 0.2 (3,7) 0.20 (,34) 0.70 (4,32) 0.7 (4,00) MAX Seating Plane 0.00 (,27) C 0.00 (2,70) MIN 0.04 (2,6) FORMED LEAD OPTION 0.022 (0,6) 0.06 (0,4) STRAIGHT LEAD OPTION D 0.06 (0,4) 0.04 (0,3) 0.3 (3,43) MIN 0.0 (,40) 0.04 (,4) 0.0 (2,67) 0.09 (2,4) 2 3 0.0 (2,67) 0.080 (2,03) 0.0 (2,67) 0.080 (2,03) 404000-2/C 0/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Lead dimensions are not controlled within this area D. FAlls within JEDEC TO -226 ariation AA (TO-226 replaces TO-92) E. Shipping Method: Straight lead option available in bulk pack only. Formed lead option available in tape & reel or ammo pack.
MECHANICAL DATA MSOT002A OCTOBER 994 REISED NOEMBER 200 LP (O-PBCY-W3) PLASTIC CYLINDRICAL PACKAGE 0.39 (3,70) 0.460 (,70).260 (32,00) 0.90 (23,00) 0.60 (6,0) 0.60 (,0) 0.098 (2,0) 0.020 (0,0) MIN 0.384 (9,7) 0.33 (8,0) 0.433 (,00) 0.33 (8,0) 0.748 (9,00) 0.748 (9,00) 0.27 (,0) 0.689 (7,0) 0.4 (2,90) 0.094 (2,40) 0.4 (2,90) 0.69 (4,30) 0.094 (2,40) 0.46 (3,70) 0.266 (6,7) 0.234 (,9) 0.2 (3,00) 0.488 (2,40) DIA TAPE & REEL 404000-3/C 0/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Tape and Reel information for the Format Lead Option package. 2
MECHANICAL DATA MSOT007A JANUARY 99 REISED SEPTEMBER 99 KC (R-PSFM-T3) PLASTIC FLANGE-MOUNT PACKAGE 0.6 (3,96) 0.46 (3,7) DIA 0.420 (0,67) 0.380 (9,6) (see Note H) 0.20 (3,0) 0.00 (2,4) 0.8 (4,70) 0.7 (4,46) 0.02 (,32) 0.048 (,22) 0.270 (6,86) 0.230 (,84) (see Note H) 0.62 (,88) 0.60 (4,22) (see Note F) 0.2 (3,8) (see Note C) 0.20 (6,3) MAX 0.62 (4,27) 0.00 (2,70) 3 0.03 (0,89) 0.029 (0,74) 0.00 (0,2) M 0.070 (,78) 0.04 (,4) 0.00 (2,4) 0.200 (,08) 0.22 (3,0) 0.02 (2,9) 0.02 (0,64) 0.02 (0,30) 4040207/ B 0/9 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Lead dimensions are not controlled within this area. D. All lead dimensions apply before solder dip. E. The center lead is in electrical contact with the mounting tab. F. The chamfer is optional. G. Falls within JEDEC TO-220AB H. Tab contour optional within these dimensions
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