Voltage-Mode Buck Regulators

Voltage-Mode Regulator V IN Output Filter Modulator L V OUT C OUT R LOAD R ESR V P Error Amplifier - T V C C - V FB V REF R FB R FB2

Voltage Mode - Advantages and Advantages Disadvantages. Stable modulation/less sensitive to noise 2. Single feedback path 3. Can work over a wide range of duty cycles Disadvantages. Loop gain proportional to V IN 2. LC double pole often drives Type III compensation 3. CCM and DCM differences - a compensation challenge 4. Slow response to input voltage changes 5. Current limiting must be done separately

Voltage Mode - Modulator Gain VIN V SW A = M V V IN P V P V C - T V C V RAMP

Voltage Mode - Output Filter V SW A L C O B R LOAD V OUT db 40 20 0 o (L, C o ) R ESR -20-40 (R esr, C o ) ESR Hz V V OUT SW = A B B 0 00,000 0,000 00,000,000,000 * (Rx, Cy) indicate the components that drive the locations of the pole and the zero, detailed equations are in the notes

Voltage Mode - Error Amplifier V OUT F I V C - V FB V REF R FB2 V V C OUT = F I The easiest place to compensate the entire loop is to adjust the compensation around the error amplifier. Several different approaches are possible.

Voltage Mode - Type II Compensation F C C2 V OUT I db 60 40 V C C C R C - V FB V REF R FB2 R FB 20 0 z F - I k p V V C OUT = F I -20 0 00,000 0,000 00,000,000,000 (R c, C c ) (R c, R FB2 ) (R c, C c2 ) Hz * (Rx, Cy) indicate the components that drive the locations of the pole and the zero

Voltage Mode - Type III Compensation F C C2 V OUT I db 60 V C V V C R C C C OUT - = C C3 R C2 V FB V REF F I R FB2 R FB 40 20 0-20 z k 0 00,000 0,000 00,000,000,000 (R c, C c ) (R FB2, C c3 ) z2 P P2 (R c, C c2 ) (R c2, C c3 ) * (R x, C y ) indicate the components that drive the locations of the poles and zeros, Hz

Current-Mode Buck Regulators

Current-Mode Buck Regulator V IN Output Filter Modulator L V OUT C OUT R LOAD R ESR Σ Slope Comp Error Amplifier R FB2 - V C - V FB R C V BG R FB C C

Current-Mode Buck-Regulator Architecture Modulator and Power Stage V IN S e Corrective Ramp S n DT - PWM Comparator Current Sense Amplifier A i - R S T DT L V OUT T C R C (ESR) R L V C Integrated or external A(s) - V OUT Reference Feedback, Error Amplifier, and Compensation

Current Mode - Advantages and Disadvantages Advantages. Power plant gain offers a single-pole roll-off 2. Line rejection 3. Cycle-by-cycle current limiting protection 4. Current sharing Disadvantages. Noise 2. Minimum ON-time 3. Current Probe (Rsense, LEM, )

CMC Sub Harmonic Oscillation D =0.6 D = 0.33

Slope Compensation mc = Internal Slope Comp Vout Vin A = Vin - Vout m m 2 RAMP 5u x (Vin - Vout) 25uA C RAMP CONTROL TIMING Stability criteria > m m 2 m m C C

Current Mode - Output Filter V SW V OUT = z C OUT R ESR C OUT R ESR R LOAD p = C OUT R LOAD f s LC OUT ( m D 0.5)

Current Mode - Error Amplifier V OUT Error Amplifier - V FB R fb2 A FB = = Rfb Rfb2 V V FB out V C R FB R C V REF R OU T g m C C = z2 C C R C = p2 C C R OUT Compensation components internal in some devices A = EA g m R OUT

Current Mode Control Loop Gain = 2 s 2 s p2 p z2 z DC 2 s 2 Q s s s s s A T Complex Pole @ Fsw/2 = D 2 m m D π Q C EA Pole EA ero Output Filter Pole Output Filter ero FB EA CM DC A A A A =

Current-Mode Load Transients Performance Tradeoffs Current mode control behaves like a current source driving the output capacitor The output impedance of a closed loop system is: OUT_CLOSED_LOOP = OUT_OPEN_LOOP Loop_Gain ΔV = OUT OUT ΔI OUT Rule of thumb for high frequency load transients (t SLEW /f CROSSOVER ):

Peak versus Average Current Mode Control Peak CMC Average CMC

Current Mode Control [CMC] Disadvantages of Peak CMC. Poor Noise Immunity (at switching on) 2. Slope Compensation required when D> 0.5 3. Peak to Average current error (ok when ripple <<) 4. Topology problem when il <> iout Advantages of Average CMC. Average Current Tracks well the Current Program in CCM or DCM. Voltage loop control is oblivious. 2. Slope Compensation not required but loop gain @ Fsw is limited to achieve stability 3. Noise Immunity is Excellent even at low Ic (set point) 4. ACMC is ok whatever the topology (il <> iout) is.

Buck ACMC design example

Control Loop Gain at Fsw The amplified current down slope Vca on the PWM comparator must be smaller than the Oscillator ramp up slope Current Amplifier Gain @ Fcrossover < Gstability

Buck ACMC design example