A Review of Phase Locked Loop Design Using VLSI Technology for Wireless Communication.

A Review of Phase Locked Loop Design Using VLSI Technology for Wireless Communication. PG student, M.E. (VLSI and Embedded system) G.H.Raisoni College of Engineering and Management, A nagar Abstract: The wireless communication systems are very useful in day to day life application. A phase locked loop is used as a main part of the system. It is used at the receiver of the wireless communication. The PLL is used to generate a proper output frequency as per the antenna reception. In the designing of this system, various individual systems are combined. In the designing of system, we have to consider a multiple working parameter. These are power requirement of system, output frequency, required input signals and designing technology etc. w. r. to Phase Locked Loop. For the designing of high end phase locked loop, we have to achieve low power consumption with higher frequency generation rate. The newly invented technology is working at the CMOS level designing of any system. The researchers are now developing a various software to achieve these features. As per the literature survey of Phase Locked Loop, the researchers are working on various parameters of working and designing. Researchers are designing a same system by various methods. There are two types of PLL designing. These are analog and digital. This paper is describing the survey of various already designed systems. Also this paper is helpful in getting the market requirements. Key words: Phase Locked Loop (PLL), Voltage Controlled Oscillator (VCO), VLSI technology, Microwind 3.1, low power, 45nm technology. 1. INTRODUCTION The electronics industry is now developing due to various newly invented technology. The electronics industry has reach a fast growth from last two decades, because the advancement in integration technology that is very large scale system design- in short advancement in the VLSI. In the high performance computing telecommunication and consumer electronics, the multiple applications has been rising steadily, and at fast pace. Typically, the required total power of these applications is the working force for the far development of this field. The power is one of the most important specification in designing of system for multi 1 gigahertz communication systems such as wireless devices, microprocessors and controllers, system on chip and ASICs [1]. Power consumption is an important parameter in the microprocessor design. The core of microprocessor requires largest power density on the microprocessor. The supply voltage can be reduced leading to reduction of static and dynamic power consumption of the circuit. But the reduced power supply can effect on the performance of the system, which is unacceptable. 2. NECESSITY The power is a very important parameter in designing of any on chip system. Also the portability of devices is a requirement of users. The high speed performance and low processing power is also a market requirement. The device should be very smart and intelligent to give an answer to individual demands with respect to broadcasting. 3. PROPOSED SYSTEM To lock the phase of input reference signal and feedback signal produced by VCO, the digital phase locked loop is used. Then this signal passes to the divider circuitry. The basic parts of a PLL is includes three main blocks Phase detector (PD). Loop filter and charge pump Voltage controlled oscillator (VCO) The phase detector basically used to compare the phase of two signals. Here, the phase detector compares phase of input signal and phase of VCO signal. The phase detector compares a phase difference between two signals and produces a difference voltage. The difference voltage is depends on the phase difference of the two inputs of phase detector. The difference voltage will passes through the filter circuit. The filter circuit is used to reduce the unwanted part of the signal [2]. Then output of the filter is applied to the input of VCO as a Vcontrol. The VCO produces the

frequency that reduces the phase difference of input signal and local oscillator. The signals are in phase, when the loop is locked. The pull in time is the period of frequencyacquisition. It should be very long or very short, which depends on the bandwidth of phase locked loop. F in Phase detector (XOR Gate) Loop Filter (RC Filter) Voltage controlled oscillator Figure 1. Block diagram of PLL. F out 3.1 Phase Detector Two broad categories of phase detector are: Multiplier circuits Sequential circuits. Multiplier means average product generation. The product of input signal waveform and local oscillator waveform is generated and the DC error signal is obtained. Properly designed multiplier system can operate on an input signal with multiple noise signals. The working of sequential phase detector depends on the zero crossing of the signals. Sequential phase detector generates a output voltage which is function of time interval between the zero crossing of two signals. We can find the phase and frequency difference of signal by using a sequential detectors There are two main phase detectors Multiplier as detector. XOR phase detector. 3.1.1 Multiplier as detector The multiplier phase detector has superior noise performance to all other detectors. This detector operates on the whole input and VCO signal rather than quantizing them to one bit. The PLL is mostly used in a microwave frequency applications and low noise synthesizers so balanced mixers are best suited for PLL. This will results in loop, whose gain is dependent upon the signal amplitude [3]. If non-idealities are implemented in circuit, mixer output is also nonlinear. Figure 2. Mixing phase detector It is advantageous to move to a detector that has immunity to these effects, when noise is not an issue. For multiple reasons, that detector may be desirable to have loop which produces a square wave instead of sinusoidal clock. If anyone over runs the mixer circuit, which is if one uses signals with large amplitudes that the amplifiers saturate, the output signals stop looking sinusoids and start looking like rectangular signals. That a phase detector is shown in Figure. The output of such a phase detector depends on a combination of averaging analysis and heuristics. The one most important feature of the phase detector is that it can be implemented ordesigned using an XOR gate that is Exclusive OR which is shown in figure. In XOR phase detector, the loop gain is independent of input signal amplitude. An XOR phase detector soutput have a larger linear range than a sinusoidal detector (mixer). 3.1.2 XOR phase detector The phase detector compares two signals with respect to their phase. There are two basic types of the phase detectors these are analog and digital. In development of the analog filter, the multiplier circuit is applicable. It will take a product of two signals and shows a resulting signals. For development of digital phase detector, we are using a XOR logic gate. The XOR gate is designed by using various logic gates i. e. AND and OR gate[4][9]. Figure 3. CMOS design of XOR gate 2

3 Table 1. Truth table of XOR gate Input Output 00 0 01 1 11 0 10 1 3.2 Loop filter The loop filter is used to improve the performance of the PLL. o Attenuates high frequency noise of the detector o Increases the hold and capture ranges o Increases the switching speed of the loop in lock. o Easy way to change the dynamics specifications of the PLL Figure 4. Concept of filter A loop filter means a Low pass filter, which passes only a low frequency signals and attenuates the frequencies which are above the cut off frequency of the filter. By observation of transfer function, we can say the gain of filter is more at low frequencies than at higher frequencies. Figure 5. Transfer function of low pass filter Figure 6. RC low pass filter 3.2.1 Filter parameters o Accuracy: To achieve an accuracy using a passive and active filter techniques requires the use of very accurate resistors, capacitors, and sometimes inductor. Accurate components reduces errors. o Cost: The passive RC network is a ideal solution to the requirement of single pole filter. When good accuracy is requirement, the passive components, basically the capacitors, used in the discrete system is very costly; this is very important in very compact designs that require surface-mount components. o Noise: Passive filters generate very less noise, and conventional active filters have lower noise than switched-capacitor ICs. o Offset Voltage: Passive filters does not have inherent offset voltage. When a filter is designed from op amps, resistors and capacitors, then offset voltage will be a function of the offset voltages of the op amps and dc gains of the various stages of filter. o Frequency Range: A passive circuit or an op amp/resistor/ capacitor circuit are developed to operate at very low frequencies, but it will require some very large, and probably expensive, reactive components. o Tunability: It is the ability of filter to attenuate and pass a proper signal. A conventional active and passive filters are designed to have for any center frequency. The center frequency can be changed by changing the values of designing components like resistors and capacitors used. o Aliasing: It means mixing of high frequency signal with low frequency signal. This problem can be solved by simply adding a RC low pass filter at the output that removes some unwanted signals of high frequency. o Design Effort: this advantage is depends on the requirement of the designed application. The easiest way is to use devices, require nothing more than clock. 3.3 Charge pump If output frequency or phase is too slow, then charge pump sources current. Charge pump sinks current if output frequency or phase is too high. It is useful in copying currents. The VCO is basically used to generate a clock at output of PLL. The clock varies by 50 percent at positive or negative of the central frequency for which current mirror or current started circuits will be used. Charge pump

circuits will used to transfer a digital error signal to analog error current [5]. Advantages of charge pumps o Less power consumption than active filters o Less noise at output than active filters o Not have offset voltage of op amps o Provide a pole at the origin or zero. o More compatible with putting the filter on chip 3.4 Voltage Controlled Oscillator It is the most important functional unit in the Phase Locked Loop. Its output frequency shows the effectiveness of PLL. For operating at highest frequency VCO unit consumes the most of the power in the system. The Voltage Controlled Oscillator is developed by using ring oscillator of 7 stages. Ring oscillator is easy and simple to construct and operate using CMOS, as inverter is its basic element. VCO is particularly focussed to reduce the power consumption of the system. The objective of the project is to design a gigahertz frequency range and less power consumption that is in microwatts. Also less phase noise at CMOS VCO. The voltage controlled oscillator gives the output frequency which is controllable by its input voltage. The VCO is commonly used for clock generation in phase lock loop circuits. The current starved inverter chain uses a voltage control to change the current that flows in the N1, P1 branch. The current flowing through N1 and other three NMOS is same, means is mirrored by N2, N3 and N4. The same current flows through P1. The current through P1 is mirrored by P2, P2 and P4. At same time, the change in Vcontrol will shows a global change in the inverter currents, and works directly on the delay. Figure 7. VCO CMOS design 5. SYSTEM SOFTWARE S The system development means describing the various stages of system implementation. It is very necessary to plan How to complete our project. The system development is divided in two important parts i.e. software development and hardware development. This project is totally software dependent project. Here, I am designing a CMOS level design of Phase Locked Loop (PLL). For designing purpose, we are using a MICROWIND 3.1 designing tool. 5.1 Software MICROWIND The designing of physical mask layout of any circuit is made by using a particular process. That uses a set of geometric constraints or rules, which are called layout design rules. The layout design rules are describes a minimum allowable line widths for on chip systems like poly silicon interconnects or diffusion areas, metals, minimum feature dimensions and allowable separations between two designs. If a metal line width is made too small, for example, any line may be breaks during generation process which makes open circuit. When two lines are placed very near to each other in the layout, they may form an unwanted short circuit during or after the fabrication process. The main objective of design rules is to obtain a high overall yield and reliability while using as small as possible silicon area, for any circuit that is manufactured with a particular process [6]-[8]. Table 2. Available CMOS technology Technology file available Minimum gate length Value of lambda Cmos12.rul 1.2µm 0.6µm Cmos08.rul 0.7µm 0.35µm Cmos06.rul 0.5µm 0.25µm Cmos035.rul 0.4µm 0.2µm Cmos025.rul 0.25µm 0.125µm Cmos018.rul 0.2µm 0.1µm Cmos012.rul 0.12µm 0.06µm Soi01.rul 0.12µm 0.06µm Cmos90n.rul 0.1µm 0.05µm Cmos65n.rul 0.07µm 0.035µm Cmos45n.rul 0.05µm 0.025µm 4

5.2 Key features of Microwind : Microwind 3.1 is a layout & simulation tool that can be useful in whole micro-electronics engineering, flexible engineering and science. Microwind 3.1 is a program to provide designers with a hands-on learning experience on nanometer technology. Microwind 3.1 is easy to learn and use so you can focus more of your time on design issues, and less on programming. Microwind 3.1 unifies schematic entry, pattern based simulator, SPICE extraction of schematic, Verilog extractor, cross sectional & 3D viewer,layout compilation, on layout mix-signal circuit simulation,, net list extraction, MOS devices and sign-off correlation is used to unmatched design performance and designer productivity. 6. CONCLUSION Here, author surveyed a various papers. From that anyone can conclude that a PLL system is a combination of various small systems that is phase detector, loop filter, pre-charge circuit and voltage controlled oscillator. Also it describes a specifications of small system and their actual use in the system. The VLSI technology is basically describes a CMOS level designing of the system means a back end design. For designing of that, multiple software are available. The Microwind is a very useful software also handing of that is easy. We can develop a system using that software. REFERENCES [1] Chih-Ming Hung and Kenneth K. O, A Fully Integrated 1.5-V 5.5-GHz CMOS Phase-Locked Loop, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 4, APRIL 2002 [2] Fernando Rangel de Sousa, Student Member, IEEE, and Bernard Huyart, Member, IEEE, A Reconfigurable High-Frequency Phase-Locked Loop, IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 53, NO. 4, AUGUST 2004 [3] Jung-Chien Li and Guan-Chyun Hsieh, Member, IEEE, A Phase/Frequency-Locked Controller for Stepping Servo Control Systems, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 39, NO. 2, APRIL 1992 [4] Jri Lee, Mingchung Liu, And Huaide Wang, A 75- Ghz Phase-Locked Loop In 90-Nm CMOS Technology in IEEE JOURNAL OF SOLID- STATE CIRCUITS, VOL. 43, NO. 6, JUNE 2008 [5] ChaitaliP.Charjan, Asso.Prof.AtulS.Joshi, Phase Locked Loop Using VLSI Technology For Wireless Communication In International Journal Of Innovative Research In Electrical, Electronics, Instrumentation And Control Engineering Vol. 2, Issue 4, April 2014 [6] Ms.Ujwala A. Belorkar and Dr.S.A.Ladhake Design of low power phase locked loop (PLL) using 45nm VLSI technology, in International journal of VLSI design & Communication Systems (VLSICS), Vol.1, No.2, June 2010 [7] ChaitaliP.Charjan, Asso.Prof.AtulS.Joshi Implementation of 2.4 GHz Phase Locke Loop using Sigma Delta Modulator, in International Journal of Application or Innovation in Engineering& Management (IJAIEM) Volume 3, Issue 3, March 2014 [8] VaishaliBhimte, VaishaliPande, Design Of Pd And High Performance Vco For Pll With 45 Nm Cmos Technology In International Journal Of Pure And Applied Research In Engineering And Technology A Path For Horizing Your Innovative Work (Ijpret), 2013; Volume 1(8): 136-143 [9] DelvadiyaHarikrushna, Prof.Mukesh Tiwari, Dr.AnubhutiKhare, Prof. Jay Karan Singh, Design, Implementation And Characterization Of Xor Phase DetectorforDpll In 45 Nm Cmos Technology, in Advanced Computing: An International Journal ( ACIJ ), Vol.2, No.6, November 2011 5