MGA-3889 4MHz - 26MHz Flat Gain High Linearity Gain Block Data Sheet Description Avago Technologies MGA-3889 is a broadband, flat gain, high linearity gain block MMIC amplifier achieved through the use of Avago Technologies proprietary 5um GaAs Enhancement-mode phemt process. The device required simple dc biasing components to achieve wide bandwidth performance. The temperature compensated internal bias circuit provides stable current over temperature and process threshold voltage variation. The MGA-3889 is housed inside a low cost RoHS compliant SOT89 industry standard SMT package (4.5 x 4.1 x mm). Component Image 8GX #1 #2 #3 RFin GND RFout Top View #3 #2 #1 RFout GND RFin Bottom View Notes: Package marking provides orientation and identification 8G = Device Code X = Month of Manufacture Attention: Observe precautions for handling electrostatic sensitive devices. ESD Machine Model = 5 V ESD Human Body Model = 4 V Refer to Avago Application Note A4R: Electrostatic Discharge, Damage and Control. Features Flat Gain 15dB +/-5dB, 4MHz to 26MHz High linearity Built in temperature compensated internal bias circuitry No RF matching components required GaAs E-pHEMT Technology [1] Standard SOT89 package Single, Fixed 5V supply Excellent uniformity in product specifications MSL-2 and Lead-free halogen free High MTTF for base station application Specifications 9MHz; 5V, 65mA (typical) 15.5 db Gain 38 dbm Output IP3 db Noise Figure 2 dbm Output Power at 1dB gain compression 195MHz, 5V, 65mA (typical) 15.7 db Gain 36 dbm Output IP3 2 db Noise Figure 2 dbm Output Power at 1dB gain compression Applications IF amplifier, RF driver amplifier General purpose gain block Note: 1. Enhancement mode technology employs positive gate voltage, thereby eliminating the need of negative gate voltage associated with conventional depletion mode devices.
Absolute Maximum Rating [1] T A = Symbol Parameter Units Absolute Max. V dd,max Device Voltage, RF output to ground V 5.5 P in,max CW RF Input Power dbm 2 P diss Total Power Dissipation [3] W 7 T j,max Junction Temperature C 15 T STG Storage Temperature C -65 to 15 Thermal Resistance Thermal Resistance [2] θ JC = 76 C/W (Vdd = 5 V, Ids = 57.5 ma, Tc = ) Notes: 1. Operation of this device in excess of any of these limits may cause permanent damage. 2. Thermal resistance measured using Infrared measurement technique. 3. This is limited by maximum Vdd and Ids. Derate 13.2 mw/ C for Tc >114 C. Product Consistency Distribution Charts [1, 2] LSL USL LSL USL 6 7 14.5 15 15.5 16 16.5 Figure 1. Ids, LSL=53mA, nominal=65ma, USL=77mA Figure 2. Gain, LSL=14.6dB, nominal=15.7db, USL=16.8dB LSL LSL 33 34 35 36 37 38 39 Figure 3. OIP3, LSL=33dBm, nominal=36dbm 19.2 19.6 2 2 2 Figure 4. P1dB, LSL=19.2dBm, nominal=2dbm USL Notes: 1. Distribution data sample size is 3 samples taken from 3 different wafer lots. Future wafers allocated to this product may have nominal values anywhere between the upper and lower limits. 2. Measurements were made on a characterization test board, which represents a trade-off between optimal OIP3, gain and P1dB. Circuit trace losses have not been de-embedded from measurements above. 2 2.7 Figure 5. NF, nominal=2db, USL=2.7dB 2
Electrical Specifications [1] T A =, Vdd =5V Symbol Parameter and Test Condition Frequency Units Min. Typ. Max. Ids Quiescent current N/A ma 53 65 77 Gain Gain 4MHz 9MHz 195MHz OIP3 [2] Output Third Order Intercept Point 4MHz 9MHz 195MHz NF Noise Figure 4MHz 9MHz 195MHz S11 Input Return Loss, 5Ω source 4MHz 9MHz 195MHz S22 Output Return Loss, 5Ω load 4MHz 9MHz 195MHz S12 Reverse Isolation 4MHz 9MHz 195MHz OP1dB Output Power at 1dB Gain Compression 4MHz 9MHz 195MHz db dbm db 14.6 33 db -16-17 -13 db -16-16.5-13 db -17-17 -22 dbm 19.2 15.9 15.5 15.7 16.8 37 38 36 2.7 21 2 2 Notes: 1. Measurements obtained using demo board described in Figure 3 and 31. 4MHz data was taken with 4MHz - 2GHz Application Test Circuit, 9MHz data with GHz GHz Application Test Circuit and 5GHz data with GHz - GHz Application Test Circuit respectively. 2. OIP3 test condition: F RF1 - F RF2 = 1MHz with input power of dbm per tone measured at worse side band. 3. Use proper bias, heat sink and de-rating to ensure maximum channel temperature is not exceeded. See absolute maximum ratings and application note (if applicable) for more details. 3
Typical Performance (4MHz - 2GHz) T A =, Vdd =5V, Input Signal=CW. Application Test Circuit is shown in Figure 3 and Table 1. 8 17 16 Ids (ma) 7 6 5-4 -3 1 2 3 4 5 Temperature ( C) 6 7 8 9 Gain (db) 15 14 13 12 11 1..1 Figure 6. Ids over Temperature Figure 7. Gain over Frequency and Temperature OIP3 (dbm) 45 44 43 42 41 4 39 38 37 36 35 34 33 32 31 3..1 Figure 8. OIP3 over Frequency and Temperature P1dB(dBm) 25 24 23 22 21 2 19 18 17 16 15..1 Figure 9. P1dB over Frequency and Temperature -5-5 S11 (db) S22 (db) -3..1 Figure 1. S11 over Frequency and Temperature -3..1 Figure 11. S22 over Frequency and Temperature 4
Typical Performance (4MHz - 2GHz) T A =, Vdd =5V, Input Signal=CW. Application Test Circuit is shown in Figure 3 and Table 1. S12 (db) -16-17 -18-19 -21-22 -23-24..1 Figure 12. S12 over Frequency and Temperature NF(dB) 5. 4.5 4. 3.5 3...1 Figure 13. Noise Figure over Frequency and Temperature Typical Performance (GHz - GHz) T A =, Vdd =5V, Input Signal=CW. Application Test Circuit is shown in Figure 3 and Table 2. 8 17 16 Ids (ma) 7 6 5-4 -3 1 2 3 4 Temperature ( C) 5 6 7 8 9 Gain (db) 15 14 13 12 11 1 Figure 14. Ids over Temperature Figure 15. Gain over Frequency and Temperature OIP3 (dbm) 45 44 43 42 41 4 39 38 37 36 35 34 33 32 31 3 Figure 16. OIP3 over Frequency and Temperature P1dB(dBm) 25 24 23 22 21 2 19 18 17 16 15 Figure 17. P1dB over Frequency and Temperature 5
Typical Performance (GHz - GHz) T A =, Vdd =5V, Input Signal=CW. Application Test Circuit is shown in Figure 3 and Table 2. -5-5 S11 (db) S22 (db) -3-3 Figure 18. S11 over Frequency and Temperature Figure 19. S22 over Frequency and Temperature S12 (db) -16-17 -18-19 -21-22 -23-24 Figure 2. S12 over Frequency and Temperature NF(dB) 5. 4.5 4. 3.5 3. Figure 21. Noise Figure over Frequency and Temperature Typical Performance (GHz - GHz) T A =, Vdd =5V, Input Signal=CW. Application Test Circuit is shown in Figure 3 and Table 3. 8 17 16 Ids (ma) 7 6 5-4 -3 1 2 3 4 Temperature ( C) 5 6 7 8 9 Gain (db) 15 14 13 12 11 1 Figure 22. Ids over Temperature Figure 23. Gain over Frequency and Temperature 6
Typical Performance (GHz - GHz) T A =, Vdd =5V, Input Signal=CW. Application Test Circuit is shown in Figure 3 and Table 3. OIP3 (dbm) 45 44 43 42 41 4 39 38 37 36 35 34 33 32 31 3 P1dB(dBm) 25 24 23 22 21 2 19 18 17 16 15 Figure 24. OIP3 over Frequency and Temperature Figure 25. P1dB over Frequency and Temperature -5-5 S11 (db) S22 (db) -3-3 Figure 26. S11 over Frequency and Temperature Figure 27. S22 over Frequency and Temperature S12 (db) -16-17 -18-19 -21-22 -23-24 NF(dB) 5. 4.5 4. 3.5 3. Figure 28. S12 over Frequency and Temperature Figure 29. Noise Figure over Frequency and Temperature 7
Application Schematic Components Table and Demo Board Vdd Top View C1/ C4 C2/ C5 C3/ C6 L1/L2 RFin C7 Vdd RFin 1 GND 2 RFout 3 C8 RFout Note: L1, C1, C2, C3 is for BOM -GHz and -GHz L2, C4, C5, C6 is for BOM 4MHz-2GHz Figure 3. Application Schematic Figure 31. Demo board Layout Recommended PCB material is 1 mils Rogers RO435, with FR4 backing for mechanical strength. Suggested component values may vary according to layout and PCB material. 8
Demo board Part List Table 1. 4MHz - 2GHz Application Schematic Components Circuit Symbol Size Value Part Number Description L2 85 82nH LLQ212-series (Toko) Wire Wound Chip Inductor C4 42 1pF GRM1555C1H11JZ1 (Murata) Ceramic Chip Capacitor C5 42.1uF GRM155R71C14KA88D (Murata) Ceramic Chip Capacitor C6 85 uf GRM21BR61E225KA12L (Murata) Ceramic Chip Capacitor C7 42.1uF GRM155R71C14KA88D (Murata) Ceramic Chip Capacitor C8 42.1uF GRM155R71C14KA88D (Murata) Ceramic Chip Capacitor Table 2. GHz - GHz Application Schematic Components Circuit Symbol Size Value Part Number Description L1 63 1nH LLQ168-FR1 (Toko) Wire Wound Chip Inductor C1 42 1pF GRM1555C1H1JZ1 (Murata) Ceramic Chip Capacitor C2 42.1uF GRM155R71C14KA88D (Murata) Ceramic Chip Capacitor C3 85 uf GRM21BR61E225KA12L (Murata) Ceramic Chip Capacitor C7 42 1pF GRM1555C1H11JZ1 (Murata) Ceramic Chip Capacitor C8 42 1pF GRM1555C1H11JZ1 (Murata) Ceramic Chip Capacitor Table 3. GHz - GHz Application Schematic Components Circuit Symbol Size Value Part Number Description L1 42 5.6nH LL15-FHL5N6 (Toko) MLC Inductor C1 42 1pF GRM1555C1H11JZ1 (Murata) Ceramic Chip Capacitor C2 42.1uF GRM155R71C14KA88D (Murata) Ceramic Chip Capacitor C3 85 uf GRM21BR61E225KA12L (Murata) Ceramic Chip Capacitor C7 42 2pF GRM1555C1H2JZ1 (Murata) Ceramic Chip Capacitor C8 42 2pF GRM1555C1H2JZ1 (Murata) Ceramic Chip Capacitor 9
Test Circuit for S-Parameter and Noise Parameter Top View Port1 RFin 1 GND 2 Vdd RFout 3 Port2 / Bias Tee Figure 32. S-parameter and Noise parameter test circuit 1
Typical S-Parameter (Vdd = 5V, T A =, 5 ohm) Freq (GHz) 11 S11 (db) S11 (ang) S21 (db) S21 (ang).4-17.4-88.23 16.16 167.9.8 6.83-14.55-138.35.1-23.82-99.63 15.83 17.2-6.92-163.34-27.2 6.63 15.78 167.69.3-7.14-16.38-173.98-26.83-116.89 15.78 163.41.5-12 -16.45-179.28-24.42-127.93 15.78 158.71.8-16.72-16.24 176.99-133 15.79 153.85.12-16.34 177.6-134.41 15.81 148.88.16.84-16.37 178.9.18-14.6 15.83 143.85-21 -36-16.39 178.81-19.1-146.29 15.85 138.73-27 -34.85-16.4 178.64-18.13 2.78 15.88 133.58-24 -39.29-16.35 177.88 1-17.42-167 15.91 128.38-22 -43.88-16.16 177.12-16.72-166.54 15.96 123.11-48.37-16.54 175.97-16.21-176.41 16. 117.79-52.85-16.29 174.49.66 173.51 16.3 117-57.37-16.3 175.9 162.73 16.7 16.92-22 -64.76 168.9-14.41 157 16.1 14-26 -66.51.42 164.84-13.67 149 16.12 95.64-22 -79.11 162-12.91 13.11 16.13 89.95-29 -75.69-14.81 155.66-12 12.6 16.13 84.16-27 -82-14.56 151-14 117 16.12 78.29-28 -84.88-14.33 145.47 2 16 16.1 75-89.37-14.14 14.5-9.89 93.15 16.6 66.53-24 -93.79-13.96 134.67-9.25 84.93 16.1 6-21 -98.15-13.84 129.5-8.7 77.25 15.96 54.75-29 2-13.8 124.63-8.17 69.77 15.88 48.83-22.98 6.71-13.8 119.72-7.72 66 15.8 43.2-23.28-111 -13.84 115.8-7.32 55.78 15.7 37.21-23.59-114.68-13.93 11 2.7-6.97 48.95 15.61 35-23.93-118.51-14.7 16.56 2.8-6.68 46 15.51 25.64-24.25-12 -14.28 12.99 2.9-6.44 35.55 15.4 19.84-24.57-125.87-14.56 99.69 3-6.23 28.95 15.3 14.15-24.89-129.4-14.95 96.77 4-4.89-49.49 13.83-45.76-28.13-164 -23.3 97.19 5-9 -116.16 18 6-31 175.49.89 8 6-3 -163.8 8.27-146.84-35 155.55-35 -167.12 7-3 126.91 6.5 159.94-34 116.8 67.94 8-8 63.71 5 17.76-31 73.41 36 9-22 -5 65.1-33.21 35.83-13.7-6.2 1-6 -35.93-6.31 19.48-34.36-2.85-13 -45 11-7 -88.75-19 -37.7-33 -8.45-7 12-8 -113-17.53-45.68-39.48-44 -5.84-86.38 13-5 -128.2-67.24-39.17-49.14-4.59 4 14-1 4-23.85-92 -37.88-64.15-4.29-122 15-1 -179.96-26.91-116.9-37.36-88.21-3.95 2 16-7 166.93-35 -133.25-39.5 6.29-3.2-168.71 17-3 157.77-33.85-145.37-49 9.41-2.77 179.33 18-7 144.27-37.31 5.13-44.53-97.93-4 169.25 19-8 124.17-44 6.44-48 -86-3.33 156.65 2-6 13.21-49.19-139 -46-75.27-3.99 129.84 S12 (db) S12 (ang) S22 (db) S22 (ang)
Typical Noise Parameters (Vdd = 5V, T A =, 5 ohm) Freq (GHz) F min (db) Γ opt Mag Γ opt Ang R n /Z.36 2.19.51-86.19 5.71-76.11-52 5 5 3.17-46 8.16-41 9 1 4-19 8 3. 5 3.7 9 3.5 1 27 5 4. 4 5 58 4 4.5 2.71 7 89 5. 3.39 5 121 3 12
Part Number Ordering Information Part Number No. of Devices Container MGA-3889-BLKG 1 7 Tape/Reel MGA-3889-TR1G 3 13 Tape/Reel SOT89 Package Dimensions D D1 D D1 POLISH E1 E OR E1 E L L S e1 e S e1 e C D2 25 D1 4 3 7 E OR 5 HALF ETCHING DEPTH.1 b b1 MATTE FINISH b POLISH A b1 Dimensions in mm Dimensions in inches Symbols Minimum Nominal Maximum Minimum Nominal Maximum A.55.59.63 L 9 4.35.41.47 b 6 2 8.14.16.18 b1 1 7 3.16.18.3 C 8 3.14.15.17 D 4.4 4.5 4.6.173.177.181 D1 5.55.62.69 D2 5 5.55.62.69 E 3.94-4.25.155 -.167 E1.94.98.12 e1 2.9 3. 3.1.114.118.122 S 5 5 5.26.3.34 e.54.59.63 13
Device Orientation REEL CARRIER TAPE 8GX 8GX 8GX 8GX USER FEED DIRECTION COVER TAPE Tape Dimensions ±.5 ±.5 SEE NOTE 3 4. SEE NOTE 1 Ø +.1/-. 8. Ø MIN. A 5 ±.1 R MAX. 5.5 ±.5 SEE NOTE 3 Bo 1 ±.3 Ko Ao R TYP. A SECTION A - A Ao = 4.6 Bo = 4.9 Ko = DIMENSIONS IN MM NOTES: 1. 1 SPROCKET HOLE PITCH CUMULATIVE TOLERANCE ± 2. CAMBER IN COMPLIANCE WITH EIA 481 3. POCKET POSITION RELATIVE TO SPROCKET HOLE MEASURED AS TRUE POSITION OF POCKET, NOT POCKET HOLE 14
Reel Dimensions 13 Reel R LOKREEL MINNEAPOLIS USA U.S PAT 4726534 ATTENTION Electrostatic Sensitive Devices Safe Handling Required R 1 REF 33. REF 88 REF "A" 96.5 6 PS Detail "B" 6 PS Detail "A" (MEASURED AT HUB) (MEASURED AT HUB) 8.4 + - 1 MAX. Ø 2 Dimensions in mm M IN Ø 13. + - ± For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright 2513 Avago Technologies. All rights reserved. AV2-225EN - November 11, 213