Synchronous Buck PWM Controller Features Single Power Supply Required 0.6 Reference with % Accuracy Shutdown and Soft-Start Function Programmable Frequency Range from 50 khz to 000kHz oltage Mode PWM Control Design Up to 00% Duty Cycle Under-oltage Protection (UP) Over-Current Protection (OCP) SOP-4 Package Lead Free and Green Devices Available (RoHS Compliant) Typical Application Circuit R FS C SS APW707 R OCSET L IN OUT General Description The APW707 is a voltage mode, synchronous PWM controller which drives dual N-channel MOSFETs. The device integrates all of the control, monitoring and protecting functions into a single package, provides one controlled power output with under-voltage and over-current protections. The APW707 provides excellent regulation for output load variation. The internal 0.6 temperature-compensated reference voltage is designed to meet the requirement of low output voltage applications. The device includes a 00kHz free-running triangle-wave oscillator that is adjustable from 50kHz to 000kHz. The APW707 has been equipped with excellent protection functions: POR, OCP, and UP. The Power-On-Reset (POR) circuit can monitor the CC, EN, and OCSET voltage to make sure the supply voltage exceeds their threshold voltage while the controller is running. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the upper MOSFET s R DS(ON). When the output current reaches the trip point, the controller will run the soft-start function until the fault events are removed. The Under-oltage Protection (UP) monitors the voltage at FB pin ( FB ) for short-circuit protection. When the FB is less than 50% of REF, the controller will shutdown the IC directly. Ordering and Marking Information APW707 Assembly Material Handling Code Temperature Range Package Code Applications Graphic Cards Package Code K : SOP - 4 Operating Ambient Temperature Range E : -0 to 70 C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW707 K : APW707 XXXXX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 00% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD- 00C for MSL classification at lead-free peak reflow temperature. ANPEC defines Green to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 500ppm by weight). ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders.
Pin Configuration RT OCSET SS COMP 4 FB 5 EN 6 GND 7 SOP-4 4 CC PCC LGATE PGND 0 BOOT 9 UGATE 8 PHASE Absolute Maximum Ratings (Note ) Symbol Parameter Rating Unit CC, PCC CC, PCC to GND -0. to +6 BOOT BOOT to PHASE -0. to +6 UGATE LGATE UGATE to PHASE <400ns pulse width >400ns pulse width LGATE to PGND <400ns pulse width >400ns pulse width PHASE PHASE to GND <400ns pulse width >400ns pulse width -5 to BOOT +5-0. to BOOT +0. -5 to PCC +5-0. to PCC +0. -0 to +0-0. to 6 RT, OCSET RT, OCSET to GND CC +0. FB, COMP FB, COMP to GND -0. to 7 PGND PGND to GND -0. to +0. T J Junction Temperature Range -0 to 50 C T STG Storage Temperature -65 to 50 C T SDR Maximum Lead Soldering Temperature, 0 Seconds 60 C Note : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics (Note ) Symbol Parameter Typical alue Unit θ JA Junction-to-Ambient Thermal Resistance in Free Air o C/W SOP-4 60 Note: θ JA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Recommended Operating Conditions Symbol Parameter Rating Unit CC, PCC IC Supply oltage 0.8 to. IN Converter Input oltage. to. OUT Converter Output oltage 0.6 to 5 I OUT Converter Output Current 0 to 0 A T A Ambient Temperature Range -0 to 70 C T J Junction Temperature Range -0 to 5 C
Electrical Characteristics Unless otherwise specified, these specifications apply over CC, and T A -0~70 C. Typical values are at T A 5 C. Symbol Parameter Test Conditions INPUT SUPPLY CURRENT I CC POWER-ON-RESET OSCILLATOR APW707 Min. Typ. Max. CC Supply Current (Shutdown Mode) UGATE, LGATE and EN GND - 0.5 ma CC Supply Current UGATE and LGATE Open - 5 0 ma Rising CC Threshold 9 9.5 0.0 Falling CC Threshold 7.5 8 8.5 Rising OCSET Threshold -. - OCSET Hysteresis oltage - 0. - Rising EN threshold oltage -. - EN Hysteresis oltage - 0. - Accuracy -5 - +5 % F OSC Free Running Frequency RT open - 00 - khz Adjustment Range RT pin: resistor to GND; Resistor to CC Unit 50-000 khz OSC Ramp Amplitude (nominal.5 to.95) -.6 - Duty Duty Cycle Range 0-00 % REFERENCE REF Reference oltage - 0.60 - Reference oltage Tolerance - - + % PWM ERROR AMPLIFIER Gain Open Loop Gain R L 0k, C L 0pF (Note ) - 88 - db GBWP Open Loop Bandwidth R L 0k, C L 0pF (Note ) - 5 - MHz SR Slew Rate R L 0k, C L 0pF (Note ) - 6 - /us FB Input Current FB 0.6-0. µa COMP COMP High oltage - 5.5 - COMP COMP Low oltage - 0 - I COMP COMP Source Current COMP - 5 - ma I COMP COMP Sink Current COMP - 5 - ma GATE DRIERS I UGATE Upper Gate Source Current BOOT, UGATE - PHASE -.6 - A R UGATE Upper Gate Sink Impedance BOOT, I UGATE 0.A -.6.4 Ω I LGATE Lower Gate Source Current PCC, LGATE - 4.9 - A R LGATE Lower Gate Sink Impedance PCC, I LGATE 0.A -.5.88 Ω T D Dead Time - 0 - ns PROTECTION FB Under oltage Level Percent of REF 45 50 55 % I OCSET OCSET Source Current OCSET.5 70 00 50 µa ENABLE/SOFT-START I SS Soft-Start Charge Current 4 0 6 µa Note : Guaranteed by design
Typical Operating Characteristics UGATE Source Current (A) UGATE Source Current vs. UGATE oltage.5.5.5 0.5 BOOT PHASE 0 UGATE Sink Current (A).5.5 0.5 UGATE Sink Current vs. UGATE oltage BOOT PHASE 0 0 0 4 6 8 0 UGATE oltage () 0 0 4 6 8 0 UGATE oltage () LGATE Source Current vs. LGATE oltage 6.5 LGATE Sink Current vs. LGATE oltage LGATE Source Current (A) 5 4 PCC LGATE Sink Current (A).5.5 0.5 PCC 0 05 0 0 4 6 8 0 0 4 6 8 0 LGATE oltage () Switching Frequency vs. Junction Temperature LGATE oltage() Reference oltage vs. Junction Temperature 0.60 Switching Frequency(KHz) 00 95 90 85 Reference oltage() 0.60 0.6 0.599 0.598 0.597 0.596 0.595 80-40 -0 0 0 40 60 80 00 0 Junction Temperature ( C) 0.594-40 -0 0 0 40 60 80 00 0 Junction Temperature ( C) 4
Operating Waveforms Power On Power Off cc, in OUT.5, LuH cc, in OUT.5, LuH CH: CC CH: SS (/div) CH: OUT (/div) Time: 0ms/div CH: CC CH: SS (/div) CH: OUT (/div) Time: ms/div EN ( EN CC ) Shutdown ( EN GND ) cc, in OUT.5, LuH cc, in OUT.5, LuH CH: EN CH: SS CH: OUT (/div) Time: 0ms/div CH: EN CH: SS CH: OUT (/div) Time: 0ms/div 5
Operating Waveforms (Cont.) UGATE Rising UGATE Falling cc, in OUT.5, LuH cc, in OUT.5, LuH CH: UGATE (0/div) CH: LGATE CH: PHASE (0/div) Time: 50ns/div CH: UGATE (0/div) CH: LGATE CH: PHASE (0/div) Time: 50ns/div Load Transient Response Under oltage Protection cc, in OUT.5, LuH cc, in OUT.5, LuH CH: OUT (500m/div) CH4: I OUT (5A/div) Time: 00us/div 4 CH: SS CH: I OUT (5A/div) CH: OUT (/div) CH4: UGATE (0/div) Time: 0ms/div 6
Operating Waveforms (Cont.) Over Current Protection Short Test cc, in, OUT.5, LuH R OCSET K, R DS(ON) 8m cc, in OUT.5, LuH 4 4 CH: SS CH: IL (0A/div) CH: OUT (/div) CH4: UGATE (0/div) Time: 0ms/div CH: SS CH: IL (0A/div) CH: OUT (/div) CH4: UGATE (0/div) Time: 0ms/div 7
Function Pin Description CC Power supply input pin. Connect a nominal power supply to this pin. The power-on-reset function monitors the input voltage by this pin. It is recommended that a decoupling capacitor ( to 0µF) be connected to the GND for noise decoupling. PCC This pin provides a supply voltage for the lower gate drive, connect this pin to the CC pin in normal use. BOOT This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. PHASE This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source. This pin is also used to monitor the voltage drop across the MOSFET for over-current protection. GND This pin is the signal ground pin. Connect the GND pin to a good ground plane. PGND This pin is the power ground pin for the lower gate driver. It should be tied to the GND pin on the board. COMP This pin is the output of PWM error amplifier. It is used to set the compensation components. FB This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for undervoltage protection. If the FB voltage is under 50% of reference voltage, the device will be shut down. LGATE This pin is the gate driver for the lower MOSFET of PWM output. SS Connect a capacitor to the GND and a 0µA current source charges this capacitor to set the soft-start time. OCSET This pin serves two functions: a shutdown control and the setting of over current limit threshold. Pulling this pin below. will shutdown the controller, forcing the UGATE and LGATE signals to be low. A resistor (Rocset) connected between this pin and the drain of the high side MOSFET will determine the over current limit. An internal 00µA current source will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the high side MOSFET. The threshold of the over current limit is therefore given by: I PEAK I OCSET (00uA) R R DS(ON) OCSET EN Pull this pin above. to enable the device and pull this pin below. to disable the device. In shutdown, the SS is discharged and the UGATE and LGATE pins are held low. Note that don t leave this pin open. RT This pin allows adjusting the switching frequency. Connect a resistor from RT pin to the ground to increase the switching frequency. Conversely, connect a resistor from RT to the CC to decrease the switching frequency. UGATE This pin is the gate driver for the upper MOSFET of PWM output. 8
Block Diagram CC OCSET GND EN Power-On- Reset I OCSET 00µA BOOT UGATE SS I SS 0µA Soft Start O.C.P Comparator 5kΩ PHASE 50% REF U..P Comparator PCC REF Error Amp PWM Comparator Gate Control 5kΩ LGATE PGND Oscillator Sawtooth Wave FB COMP Typical Application Circuit RT 5. µf Zener 5 PCC CC OCSET N448 nf IN NC NC RT BOOT. 0.µF K µf 0µF 0µF 500µFx ON OFF 0.µF 0nF nf EN SS COMP FB GND UGATE PHASE LGATE PGND.. APM50 APM556 APM50 APM556 7.µH nf. OUT µf 00µFx.k 8.k.8k.k 0nF 9
Function Description Power-On-Reset (POR) The Power-On-Reset (POR) function of APW707 continually monitors the input supply voltage ( CC ), the enable (EN) pin, and OCSET pin. The supply voltage ( CC ) must exceed its rising POR threshold voltage. The voltage at OCSET pin is equal to IN less a fixed voltage drop ( OCSET IN - ROCSET ). EN pin can be pulled high with connecting a resistor to CC. The POR function initiates soft-start operation after CC, EN, and OCSET voltages exceed their POR thresholds. For operation with a single + power source, IN and cc are equivalent and the + power source must exceed the rising CC threshold. The POR function inhibits operation at disabled status (EN pin low). With both input supplies above their POR thresholds, the device initiates a soft-start interval. Soft-Start/EN The SS/EN pins control the soft-start and enable or disable the controller. Connect a soft-start capacitor from SS pin to GND to set the soft-start interval. Figure. shows the soft-start interval. When CC reaches its Power- On-Reset threshold (9.5), internal 0µA current source starts to charge the capacitor. When the SS reaches the enabled threshold about.8, the internal 0.6 reference starts to rise and follow the SS ; the error amplifier output ( COMP ) suddenly raises to.5, which is the valley of the triangle wave of the oscillator, leads the OUT to start-up. Until the SS reaches about 4., the internal reference completes the soft-start interval and reaches to 0.6; and then the OUT is in regulation. The SS still rises to 5.5 and then stops. CSS TSoft Start t t.4 I SS Where: C SS external Soft-Start capacitor I SS Soft-Start current0µa oltage 4..8 Figure. Soft-Start Internal Over-Current Protection (monitor upper MOSFET) The APW707 monitors the voltage across the upper MOSFET and uses the OCSET pin to set the over-current trip point. A resistor (R OCSET ) connected between OCSET pin and the drain of the upper MOSFET will determine the over current limit. An internal 00µA current source will flow through this resistor, creating a voltage drop, which will be compared with the voltage across the upper MOSFET. When the voltage across the upper MOSFET exceeds the voltage drop across the R OCSET, an over-current will be detected. The threshold of the over current limit is therefore given by: I t0 LIMIT I OCSET t t R RDS( ON) OCSET For the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined. OUT Time - The MOSFET s R DS(ON) is varied by temperature and gate to source voltage, the user should determine the maximum R DS(ON) in manufacturer s datasheet. SS - The minimum I OCSET (70µA) and minimum R OCSET should be used in the above equation. - Note that the I LIMIT is the current flow through the upper MOSFET; I LIMIT must be greater than maximum output current add the half of inductor ripple current. 0
Function Description (Cont.) Over-Current Protection (Cont.) An over current condition will shut down the device and discharge the C SS with a 0µA sink current and then initiates the soft-start sequence. If the over current condition is not removed during the soft-start interval, the device will be shut down while the over current is detected and the SS still rises to 4 to complete its cycle. The soft-start function will be cycled until the over current condition is removed. Both over-current protections have the same behavior while an over current condition is detected. Under-oltage Protection The FB pin is monitored during converter operation by their own Under oltage (U) comparator. If the FB voltage drops below 50% of the reference voltage (50% of 0.6 0.), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter s output is latched to be floating. Switching Frequency The APW707 provides the oscillator switching frequency adjustment. The device includes a 00kHz free-running triangle wave oscillator. If operating in higher frequency than 00kHz, connect a resistor from RT pin to the ground to increase the switching frequency. Conversely, if operating in lower frequency than 00kHz, connect a resistor from RT to the CC to decrease the switching frequency. Figure. shows how to select the resistor for the desired frequency. Figure. shows more detail for the higher frequencies and Figure 4 shows the lower frequency detail. RT Resistance (KΩ) RT Resistance (KΩ) RT Resistance (KΩ) 000 900 800 700 600 500 400 00 00 00 0 0 000 Frequency (khz) Figure. Oscillator Frequency vs. RT Resistance 000 900 800 700 600 500 400 00 00 00 0 00 00 400 500 600 700 800 900 000 Frequency (khz) Figure. Oscillator Frequency vs. RT Resistance 000 900 800 700 600 500 400 (High Frequency) 00 00 50 70 90 0 0 50 70 Frequency (khz) Figure4. Oscillator Frequency vs. RT Resistance (Low Frequency)
Application Information Output oltage Selection The output voltage can be programmed with a resistive divider. Use % or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 0.6. The output voltage is determined by: R 0.6 + R OUT OUT GND Where R OUT is the resistor connected from OUT to FB and R GND is the resistor connected from FB to the GND. Output Inductor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor s ripple current and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by: IN OUT I RIPPLE FS L OUT IN OUT IRIPPLE ESR where Fs is the switching frequency of the regulator. Although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will exist between the inductor s ripple current and the regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (F S ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to choose the ripple current to be approximately 0% of the maximum output current. Once the inductance value has been chosen, select an inductor is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage. Output Capacitor Selection Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least. times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately I OUT /, where I OUT is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor µf can be connected between the drain of upper MOSFET and the source of lower MOSFET. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the R DS(ON), reverse transfer capacitance (C RSS ) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following equations: P UPPER I OUT ( + TC)(R DS(ON) )D + (0.5)( I OUT )( IN )( t SW )F S P LOWER I OUT (+ TC)(R DS(ON) )(-D) Where I OUT is the load current TC is the temperature dependency of R DS(ON) F S is the switching frequency t SW is the switching interval D is the duty cycle
Application Information (Cont.) MOSFET Selection (Cont.) Note that both MOSFETs have conduction loss while the upper MOSFET includes an additional transition loss. The switching internal, t SW, is the function of the reverse transfer capacitance C RSS. The (+TC) term is to factor in the temperature dependency of the R DS(ON) and can be extracted from the R DS(ON) vs Temperature curve of the power MOSFET. PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 80 degrees phase shift in the control loop. A compensation network among COMP, FB, and OUT should be added. The compensation network is shown in Figure 8. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is given by: FESR π ESR C OUT The F LC is the double poles of the LC filter, and F ESR is the zero introduced by the ESR of the output capacitor. PHASE L OUT GAIN (db) Figure 5. The Output LC Filter F LC -40dB/dec F ESR C OUT ESR -0dB/dec The PWM modulator is shown in Figure 7. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by: GAIN OSC PWM Output of Error Amplifier IN OSC OSC PWM Comparator Driver Driver Figure 7. The PWM Modulator IN PHASE The compensation network is shown in Figure 8. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin. The transfer function of error amplifier is given by: GAIN s + s + ( ) R+ R R C R+ R C R R C C+ C s s + s + R C C R C The poles and zeros of the transfer function are: F F F F Z Z P P AMP COMP OUT π R C π ( R+ R) C C C π R C+ C π R C // R + sc sc R// R + sc C R C R C Frequency(Hz) Figure 6. The LC Filter GAIN and Frequency OUT R FB REF Figure 8. Compensation Network COMP
Application Information (Cont.) PWM Compensation (Cont.) The closed loop gain of the converter can be written as: GAIN LC X GAIN PWM X GAIN AMP Figure 9. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -0dB/ decade slope and a phase margin greater than 45 degree. The poles and zero of this transfer functions are: F LC R π L C R F S F LC C π R F S OUT. Choose a value for R, usually between K and 5K.. Select the desired zero crossover frequency F Z F Z F P F P F O : (/5 ~ /0) X F S >F O >F ESR Use the following equation to calculate R: OSC FO R R F IN LC. Place the first zero F Z before the output LC filter double pole frequency F LC. F Z 0.75 X F LC Calculate the C by the equation: C π R F 0.75 LC 4. Set the pole at the ESR zero frequency F ESR : GAIN (db) 0log (R /R ) F LC F ESR PWM & Filter Gain Compensation Gain 0log ( IN / OSC ) Frequency(Hz) Converter Gain Figure 9. Converter Gain and Frequency F P F ESR Calculate the C by the equation: C C π R C F ESR 5. Set the second pole F P at the half of the switching frequency and also set the second zero F Z at the output LC filter double pole F LC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at F P with the capabilities of the error amplifier. F P 0.5 X F S F Z F LC Combine the two equations will get the following component calculations: + s ESR COUT GAINLC s L C + s ESR C + OUT OUT 4
Layout Consideration Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at 00kHz,the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separating till combined using the ground plane construction or single point grounding. Figure 0 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: the loads. The input capacitor GND should be close to the output capacitor GND and the lower MOSFET GND. - The drain of the MOSFETs ( IN and PHASE nodes) should be a large plane for heat sinking. APW707 CC PCC BOOT UGATE PHASE LGATE IN Figure 0. Layout Guidelines OUT L O A D - Keep the switching nodes (UGATE, LGATE, and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UGATE, LGATE) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers, boot capacitors, and SS capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near 5
Package Information SOP 4 D SEE IEW A E E h X 45 e b c A A A IEW A L 0.5 GAUGE PLANE SEATING PLANE S Y M SOP-4 B O L MIN. MAX. MIN. A.75 A 0.0 0.5 0.004 MAX. 0.069 0.00 A.5 0.049 b 0. 0.5 0.0 0.00 c 0.7 0.5 0.007 0.00 D 8.55 8.75 0.7 0.44 E 5.80 6.0 0.8 0.44 E.80 4.00 0.50 0.57 e.7 BSC 0.050 BSC h 0.5 0.50 0.00 0.00 L 0.40.7 0.06 0.050 0 0 8 0 8 MILLIMETERS INCHES Note:. Follow JEDEC MS-0 AB.. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.. Dimension E does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0 mil per side. 6
Carrier Tape & Reel Dimensions OD0 P0 P P A E OD B A T B0 W F K0 B A0 SECTION A-A SECTION B-B d H A T Application A H T C d D W E F 0.0.00 50 MIN. 6.4+.00-0.00.0+0.50-0.0.5 MIN. 0. MIN. 6.0 0.0.75 0.0 7.50 0.0 SOP-4 P0 P P D0 D T A0 B0 K0 4.0 0.0 8.0 0.0.0 0.0.5+0.0-0.00.5 MIN. 0.6+0.00-0.40 6.40 0.0 9.00 0.0.0 0.0 (mm) Devices Per Unit Package Type Unit Quantity SOP- 4 Tape & Reel 500 7
Taping Direction Information SOP 4 USER DIRECTION OF FEED Reflow Condition (IR/Convection or PR Reflow) T P Ramp-up tp Critical Zone T L to T P Temperature T L Tsmax Tsmin ts Preheat t L Ramp-down 5 t 5 C to Peak Reliability Test Program Time Test item Method Description SOLDERABILITY MIL-STD-88D-00 45 C, 5 sec HOLT MIL-STD-88D-005.7 000 Hrs Bias @5 C PCT JESD--B, A0 68 Hrs, 00%RH, C TST MIL-STD-88D-0.9-65 C~50 C, 00 Cycles ESD MIL-STD-88D-05.7 HBM > K, MM > 00 Latch-Up JESD 78 0ms, tr > 00mA 8
Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly Average ramp-up rate (T L to T P ) C/second max. C/second max. Preheat 00 C 50 C - Temperature Min (Tsmin) - Temperature Max (Tsmax) 50 C 00 C 60-0 seconds 60-80 seconds - Time (min to max) (ts) Time maintained above: - Temperature (T L ) - Time (t L ) 8 C 60-50 seconds 7 C 60-50 seconds Peak/Classification Temperature (Tp) See table See table Time within 5 C of actual Peak Temperature (tp) 0-0 seconds 0-40 seconds Ramp-down Rate 6 C/second max. 6 C/second max. Time 5 C to Peak Temperature 6 minutes max. 8 minutes max. Notes: All temperatures refer to topside of the package. Measured on the body surface. Table. SnPb Eutectic Process Package Peak Reflow Temperatures Package Thickness olume mm <50 olume mm 50 <.5 mm 40 +0/-5 C 5 +0/-5 C.5 mm 5 +0/-5 C 5 +0/-5 C Table. Pb-free Process Package Classification Reflow Temperatures Package Thickness olume mm <50 olume mm 50-000 olume mm >000 <.6 mm 60 +0 C* 60 +0 C* 60 +0 C*.6 mm.5 mm 60 +0 C* 50 +0 C* 45 +0 C*.5 mm 50 +0 C* 45 +0 C* 45 +0 C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0 C. For example 60 C+0 C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing st Road, SBIP, Hsin-Chu, Taiwan Tel : 886--564000 Fax : 886--564050 Taipei Branch : F, No., Lane 8, Sec Jhongsing Rd., Sindian City, Taipei County 46, Taiwan Tel : 886--90-88 Fax : 886--97-88 9