roceedings of the 5th WSEAS Int. Conf. on Microelectronics, Nanoelectronics, Optoelectronics, rague, Czech epublic, March -4, 6 (pp64-69) DESIGN OF TANSFOME BASED CMOS ACTIVE INDUCTANCES G.SCANDUA, C.CIOFI Dipartiento di Fisica della Materia e TFA Università degli Studi di Messina Salita Sperone 3, I-9866 Messina ITALY Abstract: - In this paper the design of a transforer based CMOS active inductance to be used for the realization of fully integrated F CMOS front ends is discussed. The circuit topology eployed ais at taking the axiu advantage of the liited transconductance gain of MOS devices for copensating the losses of the integrated agnetic structures. In this way, even if a.35 µ technology has been eployed, it has been possible to obtain an equivalent alost ideal inductance of 6 nh at a center frequency of.4 GHz. The circuit operates with a supply voltage of 3.3 V and drives less than A. Moreover, two control voltages can be used in order to tune the axiu quality factor of the inductance and to change in a relatively wide range the frequency at which it occurs. Key-Words: - Active inductance, Integrated transforer, CMOS, Quality factor, F, Circuit design Introduction Modern F front ends to be used for obile counication and wireless networking require a considerable aount of digital signal elaboration thus aking the CMOS technology the andatory choice if one has to design very low cost fully integrated front ends. In the last few years, progresses in the CMOS technology have ade MOSFET with sufficient gain in the GHz frequency range available, and therefore the ain obstacle toward the fully integration of F systes is represented by the difficulties encountered in the integration of high quality inductors. articularly in the case of CMOS processes, integrated passive inductors have typical values of Q that are too low for ipleenting several fundaental F functions (for exaple highly selective filters) [,]. Although the quality factor can be iproved by resorting to special fabrication steps[3,4], the additional processing cost and coplication resulting fro a odification in the process flow ake such an approach quite unsatisfactory. For this reason, there is a strong interest in the possibility of realizing high quality inductances by eploying active circuits. A few topologies of active inductors have been proposed in the literature, which can be classified into three ain categories. A first approach is the one in which no actual inductance is used but an inductive effect is obtained exploiting the ipedance transforation capabilities of circuit such as the gyrator [5-7]. A second possible approach is the one in which a bi-pole with a negative resistance behaviour is put in series to the inductor in order to copensate the losses and increase the resulting quality factor Q[8]. A third approach exploits the agnetic coupling between the spirals of an integrated transforer and a current aplification between priary and secondary introduced by an active device in order to obtain a purely inductive behaviour[9,]. As a general rule, inductorless circuits result in a saller occupied area with respect to transforer based ones. However, it is believed that by resorting to a transforer in which the agnetic coupling controlled by an active device acts in such a way as to increase the quality factor of an otherwise passive inductive structure, one can get better noise and linearity perforances with respect to ipedance transforation circuit such as those based on gyrators. In the case of bipolar technologies, transforer based circuits have allowed the design of LNAs with noise perforances quite close to what would have been obtained in the case of passive, high quality inductors loads[]. In this paper it will be discussed a new topology that can be used for the realization of high quality, transforer based, CMOS active inductances. The design guidelines will be discussed in detail and siulation results will be presented that confir the validity of the followed approach. Open questions that need to be addressed in order to ake the actual design feasible will be discussed as well.
roceedings of the 5th WSEAS Int. Conf. on Microelectronics, Nanoelectronics, Optoelectronics, rague, Czech epublic, March -4, 6 (pp64-69) roble Forulation In a previous work a new topology for the design of transforer based CMOS inductances was introduced that was proven to have significant advantages with respect to the one that would have been directly derived fro the topology eployed in the case of bipolar technologies[]. Here the properties of the new topology will be discussed in detail in order to derive guidelines to be used in the design for a specific application. A siplified diagra of the new topology that has been developed for the realization of high quality active inductances is reported in Fig.. IN C A L V T C V D D Fig.: siplified circuit of the CMOS active inductor proposed The parasitic resistances in series with the coils of the transforer are not shown in the figure. These, however, are shown in the sall signal equivalent circuit reported in Fig. C GS ' IN V GS i L v L L L Fig.: sall-signal equivalent circuit of the CMOS active inductor In order to siplify the discussion the equivalent transconductance (g ) of the cascode stage will be assued to be purely real. The coupled inductances L and L represent the transforer whereas the capacitance C can be realized by eans of a MOS varicap and therefore its value can be changed in a given range by eans of a proper control voltage. The equivalent ipedance IN is the parallel of the ipedance IN in Fig. and of the input capacitance of the MOSFET (C GS ). As long as it can be guaranteed a purely inductive IN, whose inductance value is below that which C g V GS v L L i L would be resonant with C GS at the design frequency, it will be still obtained a purely inductive IN. Let us define the ipedance as: ( s) ( + sl ) () sc It can be written: V in VGS ( + + sl ) il + smgv () GS And therefore, in the frequency doain: ' + + jωl IN jωmg (3) ( + + jωl )( + jωmg ) + ω M g If now the nuerator of Eq.3 is taken into consideration it ay be observed that the ter (+jωmg ) acts in such a way as to increase the phase of IN and therefore it can allow to reach, at a given frequency, a phase quite close or even exactly equal to π/. Note, however, that as the frequency increases, depending on the behaviour of the other ters at the nuerator in Eq. 3, it is possible to end up with a bipole whose phase is larger than π/, that is an equivalent ipedance with a negative real part. This situation has to be avoided as negative equivalent resistances ay lead to instability. Therefore, it ay be stated that the requireents for an equivalent ipedance to be regarded as an ideal inductance at a given angular frequency ω D are: The equivalent resistance in of the ipedance IN has to be at the design frequency ω D. The equivalent resistance in has to be positive in a neighbourhood of ω D. In other words, it can be accepted as a good equivalent of an inductance any ipedance with positive iaginary part provided that the real part has a iniu (close or equal to ) at the desired design frequency. The above conditions translate analytically to the following set of siultaneous equations: in ( jωd ) (4) in ( jω) ω ω ωd Solving the above proble in our case is not difficult in principle, but it ay becoe tedious and coplicated because of the several paraeters that are involved in the design. In order to extract general indications on the actual possibility of designing an ideal inductor with the proposed topology, we ay proceed as follows.
roceedings of the 5th WSEAS Int. Conf. on Microelectronics, Nanoelectronics, Optoelectronics, rague, Czech epublic, March -4, 6 (pp64-69) Let us start by rewriting the ipedance in the following for: + Q s L ( s) ; Q s s L C + + Q (5) In order not to coplicate too uch the discussion, let us assue that in any case the inductances L and L is characterized by the very sae quality factor, that is: L L (6) Now let us define the following quantities: ω ωd r ; α Mg M ; x ; xd (7) With the previous assuptions and position it can be written: ' IN zn ( x) (8) x [ r( x ) + ] + jr ( + jq x)( + jαx) Q + α x x ( x ) + j Q Therefore, finding the conditions for obtaining a purely inductive ipedance at a given design (angular) frequency ω D, is equivalent to solve the syste: [ zn ( x) ] x xd (9) d [ zn ( x) ] x xd x where the relevant design paraeters are reduced to the quantities Q, α and r only. The syste can be solved nuerically for different sets of paraeters and the results are suarized in the graphs in Fig. 3 where the positions ωdl QD xdq ; xd α ωdmg () M have been used. As an exaple of the possible applications of the plots in Fig. 3, let us assue that the design frequency f D is.4 GHz (ω D πf D ). Let us also assue that is available an integrated inductance L.6 nh with a quality factor at the design frequency of 5 (these are realistic paraeters as reported in the AMS C35 process design paraeters). Let us also assue that it can be designed a transforer with L L L and and characterized by a coupling factor k of.8 so that the utual inductance can be assued M nh. In order to obtain a purely inductive equivalent ipedance, fro the plots in Fig. 3 we have: ω D M g ω D /ω,, r 3, 3 4 5 6 7 8 9,,9,8,7,6 r 3,5 3 4 5 6 7 8 9 Fig.3: lots for the design of the active inductance. The values of the quantities ω D /ω and ω D Mg that allow to satisfy Eq. (9) are reported as a function of Q D. ωd ω DMg M.33 ; ().7 and therefore it ust result: g M A/V ; C 88 ff () Once the noinal values of the paraeters g and C are obtained by eans of the siplified approach that has been described so far, the designer can select the MOS transistor widths and the size of the CMOS varicap to be used. It ust be noted that both the bias voltage V and the varicap control voltage can be used as paraeters for the fine tuning of the circuit both at the advanced design level (when verifying the circuit by eans of a circuit siulator) and also as a eans for copensating process paraeters variation or for changing the frequency at which a pure inductance is obtained once the circuit is built. This fact is iportant since it could provide the eans for designing copensation systes for tracking teperature and process paraeters and for allowing the design of prograable high quality inductances. Although the eans by which such systes can be designed and realized have not been investigated yet, it is iportant to understand how each single control Q D Q D
roceedings of the 5th WSEAS Int. Conf. on Microelectronics, Nanoelectronics, Optoelectronics, rague, Czech epublic, March -4, 6 (pp64-69) voltage acts on the equivalent ipedance paraeters. To better understand the role of the varactor (C in Fig.), let s assue it to be reoved (that is C ). The expression of the ipedance IN then becoes: ' + jωl + + jωl + + jω( L + L ) IN jωmg jωmg (3) By setting the values for the various paraeters as in the exaple above, it is possible to plot the phase of the ipedance IN as a function of the frequency as in Fig. 4 (case C ). The other curves in the figure are obtained by plotting the phase of the ipedance IN for different values of the capacitance C. As it is apparent fro the figure, the role of the capacitance C is that of causing the phase to decrease above a certain frequency. If the correct value for C is used (C 9 ff in the figure, quite close to the value in Eq. ), one can obtain the desirable situation of the phase having a axiu exactly equal to π/. The angular frequency ω D shown in Fig. 4 is the one for which the real part of IN is equal to zero, i.e. ω D satisfies the equation: ' ' ' ' L + L QDω DMg ; QD ω D (4) + It is interesting to note that the angular frequency of operation, ω D, in the case in which the value of C is such as to have the axiu of the the phase exactly equal to π/, is quite close to (slightly higher than) the angular frequency ω' D that can be calculated fro Eq.(4). This situation presents itself for alost any reasonable cobination of circuit paraeters, and therefore it can be used for an heuristic but effective fast design procedure. In fact, if we are willing to design an ideal inductance at a given angular frequency ω D, we can start searching for the proper circuit paraeters that allow to satisfy Eq. (4) for an angular frequency ω' D slightly lower than ω D. Note that higher values of g lead to lower value of ω D. As the value of g can be varied in the actual circuit by changing the bias point of the cascode stage, the actual choice of ω D is not critical. As a first order estiation one can try to obtain ω D ω D assuing the lowest value of g which can be obtained out of the cascode stage without degrading too uch its frequency perforances. At this point one can estiate the required value for the capacitance C by observing that the design angular frequency has to be in any case quite close to.7 ω (Fig. 3). π hase π/ ω' D, ω/ω D ω D 9 ff 3 ff C ff Fig.4: hase of IN for different values of the capacitance C. The capacitance value thus obtained can be used to select the characteristics of the varicap to be used for its ipleentation. Fro the above results it can also be concluded that it is the value of g, and therefore of the control voltage V, that has the ost iportant influence on the operating angular frequency ω D, while acting on the varicap control voltage allows to have the correct phase behaviour in the neighbourhood of the design frequency. These observations can be regarded as the starting point toward the design of possible active copensation circuits. 3 Siulation esults The approach described above has been eployed in order to verify the feasibility of designing a purely inductive ipedance above GHz using a low cost.35 µ CMOS process by AMS with a supply of 3.3 V. In order to further reduce the requireents for the transconductance value (g ) a stacked integrated transforer has been designed in which the value of M is increased by increasing the nuber of turns of the secondary coil L. This can be done while aintaining the sae occupied area by reducing the width of the etal path at the cost of an increased value of the parasitic resistance. This does not significantly ipair the perforances of the circuit as long as a sufficiently high value of the output ipedance for the cascode stage is obtained. The designed transforer occupies an area of 7x7 µ. The relevant transforer paraeters have been obtained by proper electroagnetic siulation using the Microwave Office tools and by carefully reproducing the process stack and the characteristic electroagnetic paraeters derived fro the AMS.35 µ process anual for each process layer. A 3D view of the siulated structure is reported in Fig. 5. Note that the vertical scale is not linear in order to evidence the stacked transforer structure.
roceedings of the 5th WSEAS Int. Conf. on Microelectronics, Nanoelectronics, Optoelectronics, rague, Czech epublic, March -4, 6 (pp64-69) 45 4 35 3 8 Q 5 5 6 L(nH) 4 5 3 4 f(ghz) Fig.6: Q-factor and active inductance Fig. 5: 3D view of the siulate transforer structure. All diensions are in icrons. The different layers are represented using different scales in order to evidence the structure of the stacked transforer. The self resonating frequency of the priary and secondary inductances were above 8 GHz, while the luped odel paraeters extracted fro the results of electroagnetic siulation were: L.65nH 7Ω L 5nH 5Ω M. nh (5) By coparing the paraeters obtained fro the luped siplified odel and by eans of direct electroagnetic siulation, it has been possible to verify that the siplified odel provides a good representation of the transforer behaviour as far as our discussion is concerned. All the other devices, including the inductance L and the varicap C, were available as part of the F AMS.35 µ library. All the paraeters were set at the values used in the previous exaple. In particular, the CMOS varicap has been chosen in such a way to obtain a central value for the capacitance of about 8 ff. Fig. 6 suarizes the results obtained after adjusting the bias voltage V and the control voltage of the varicap in such a way as to approach the condition of ideal inductance at about.4 GHz. The value of the inductance results about 5.5 nh. In Fig 7 the different behaviour of Q which can be obtained by setting proper values for the two available control voltages is shown. It ust be noted that the condition of quasi-ideal inductance can be reached in a significantly wide frequency range, fro about. up to.8 GHz. In Table all the relevant paraeters are listed that correspond to the three situations reported in Fig. 7, that is the value of the inductance at the axiu Q, the supplied current, the values of the bias voltage V and of the varicap control voltage. Note that as one end of the varicap control voltage is V itself, the reported values refer to the difference between V and the actual voltage applied to the other control terinal of the varicap. This result is quite encouraging as it suggests that, by designing a proper control syste, such a wide tuning range could be exploited in order to copensate for process and teperature variations. The possibility of designing such a control syste, together with a detailed analysis of the deviation fro the ideal behaviour as can be expected in the actual realization of the circuit does not appear to be an easy task at present, but further investigations 5 45 4 35 3 5 Q 5 5..5..5 3. 3.5 4. f(ghz) Fig.7: Q-factor for several values of the two control voltages are being currently perfored that are expected to provide the correct design guidelines. In order to estiate noise perforances, it has been evaluated the SD (ower Spectral Density) of the equivalent noise current source in parallel to the equivalent inductance. In the case of the axiu Q occurring at.,.4 and.8 GHz, the SD is about.5,. and.5 pa/ Hz, respectively. Although it is difficult to copare noise results with others reported in the literature, because of differences in process paraeters and in target paraeters such as equivalent inductance, power
roceedings of the 5th WSEAS Int. Conf. on Microelectronics, Nanoelectronics, Optoelectronics, rague, Czech epublic, March -4, 6 (pp64-69) dissipation or supply voltage, these noise results are better than those reported in [6] where a differential gyrator is used, thus possibly justifying the larger eployed area with potentially better noise perforances. TABLE f Qax (GHz) L @ f Qax (nh) V (V) V (V) Ι BIAS (A). 5.46 67 3.57.4 5.48 7.9.8 5.7 75 -.3 Linearity is another iportant issue in the case of active inductances. Using typical figures eployed for the characterization of linearity in aplifiers is not feasible in the case of a bipole. In order to get inforation about linearity, a periodic steady state siulation has been perfored using a sinusoidal current source driving the inductance. An equivalent ipedance SS has been evaluated as the ratio between the voltage fundaental haronic across the inductance and the input current for increasing aplitudes. The results obtained in the case of the axiu Q occurring at.4 GHz show that copression effects (db) occur above about A. 4 Conclusion In this paper the design issues for the realization of high quality transforer based active inductances in CMOS technology have been discussed. An original topology has been presented that, while considerably reducing the requireents in ters of gain, transition frequencies and power consuption with respect to other designs, provides for two control voltages that can be used in order to accurately tune the circuit during its actual operation. A.35 µ CMOS technology has been used to deonstrate the validity of the proposed solution which allowed to reach the condition of zero series equivalent resistance (that is a virtually infinite Q) for an inductance value of 6 nh at.4 GHz by properly acting on the above entioned control voltages. By following the proposed approach, alost ideal inductances could be obtained at higher frequencies provided that up to date technologies are eployed. So, in the future, fully integrated CMOS F front ends, for single chip, low cost, WLAN interfaces in the 5-6 GHz frequency range, could be realized. eferences: [] F. Mernyei, F. Darrer, M. ardoen, A. Sibrai, educing the Substrate Losses for F Integrated Inductors, IEEE Microwave and Guided Wave Letters, Vol.8, pp. 3-3,Septeber 998 [] T. Soorapanth, S.S. Wong, A -db IL 4 +- 3MHz Bandpass Filter Utilizing Q-Enhanced Spiral Inductors in Standard CMOS, IEEE J. Solid State Circuits, vol.37, pp.579-586, May [3] A. Elshabini-iad, W.B. Kuhn, F.W. Stephenson, Centre-Tapped Spiral Inductors for Monolithic Bandpass Filter, Electron. Lett., vol., n., pp.65-66, Jan. 995 [4] C.. Yue, S.S. Wong, On-Chip Spiral Inductors with atterned Ground Shields for Si-Based F IC s, IEEE J. Solid State Circuits, vol. 33, pp. 743-75, May 998 [5] A. Thanachayanont, CMOS Transistor-Only Active Inductor for IF/F Applications, IEEE ICIT, Bangkok, Thailand. [6] Grozing, M.; ascht, A.; Berroth, M.; A.5 V CMOS differential active inductor with tunable L and Q for frequencies up to 5 GHz, adio Frequency Integrated Circuits (FIC) Syposiu,. Digest of apers. IEEE, - May pp:7-74 [7] Akbari-Dilaghani,.; ayne, A.; Touazou, C.; A high Q F CMOS differential active inductor, IEEE International Conference on Electronics, Circuits and Systes, 998 Volue 3, 7- Sept. 998 pp:57-6 vol.3 [8] W.B. Kuhn, N.K. Yunduru, A.S. Wyszynski, Q-Enhanced LC Bandpass Filters for Integrated Wireless Applications, Trans. On Microwave Theory and Techniques, vol. 46, n., Dec.998, pp. 577-586; [9] Y.C. Wu, M.F. Chang, On-Chip High Q (>3) Transforer-Type Spiral Inductors), Electronics letters, 3 st January, Vol. 38, No.3 [] G. D Angelo, L. Fanucci, A. Monorchio, A. Monterastelli, B. Neri,, High Quality Active Inductors, IEE Electronics Letter, N., 3th Sept. 999, pp.77-78 [] D. ito, L. Fanucci, B. Neri, S. Di ascoli, G. Scandurra, Single Chip.8GHz Band ass LNA with Teperature Self-Copensation, SCS 3, International Syposiu on Signals, Circuits and Systes, vol., - July 3, pp. - 4 [] G. Scandurra, C. Ciofi, D. ito, A new topology for transforer based CMOS active inductances, esearch in Microelectronics and Electronics, 5 hd,vol., 5-8 July 5 pp. 7-3