The NI PXIe-5644R Vector Signal Transceiver World s First Software-Designed Instrument
Agenda Hardware Overview Tenets of a Software-Designed Instrument NI PXIe-5644R Software Example Modifications Available IP and Examples 2
Hardware Overview
PXIe-5644R 6 GHz Vector Signal Transceiver PXIe-5644R Configuration Frequency Range Bandwidth Features VSA and VSG w/ independent LOs 24 DIO lines @ 250 Mbps 65 MHz to 6 GHz 80 MHz Fast Tuning Mode: <400 μs Small footprint (3 PXIe slots) Support for the latest wireless standards (802.11ac and LTE) Programmable FPGA w/ LabVIEW 4
A Closer Look at the PXIe-5644R RF Input 65 MHz 6 GHz 80 MHz BW RF Output 65 MHz 6 GHz 80 MHz BW Reference In/Out Trigger Digital I/O 24 channels Up to 250 Mbps Additional triggering Calibration In/Out Always keep the calibration cable connected LOs In/Out Independent In & Out MIMO Support 5
PXIe-5644R Block Diagram 6
Hardware Architecture CLK DRAM Baseband Board RF Board 0 LO FPGA DAC RF Up converter RF Out FPGA Virtex 6 LX195/240T RF Board 1 LO ADC RF Down converter RF In PXIe BUS DIO DIO DRAM 7
The Traditional Approach Processor SMC CLK DRAM Baseband Board RF Board 0 LO LabVIEW Application Code FPGA DAC RF Up converter RF Out Instrument Driver Generation FPGA Virtex 6 LX195/240T DSP RF Board 1 LO NI-RFSG Configuration Calibration Data Movement Triggering NI-RFSA Configuration Calibration Data Movement Triggering TCLK Synchronization PXIe BUS Acquisition DSP ADC DIO DIO RF Down converter RF In Open (LabVIEW) Closed (C++/VHDL) DRAM 8
The Software-Designed Approach Processor CLK DRAM Baseband Board RF Board 0 LO LabVIEW Application Code FPGA LabVIEW FPGA Code DAC RF Up converter RF Out NI Design Library Host Code NI Design Library FPGA Code RF Board 1 LO Configuration Configuration ADC RF Down converter RF In Acquisition Generation PXIe BUS Acquisition Generation DIO DIO DSP Synchronization DSP Synchronization Open (LabVIEW) Closed (C++/VHDL) DRAM 9
Software-Designed Instrumentation 10
Software-Designed Advantages 11
VSA Receiver Architectures Single Stage (Single Conversion) Small size and low cost Great for wired or banded measurements Out-of-band alias rejection for over-theair or swept spectral measurements Multi-Stage (Super Heterodyne) Larger size and higher cost Wideband sweeps - spur sweep, spectral emissions, harmonics, etc Over-the-air measurements 12
PXIe-5644R VST Receiver Architecture 40 MHz: 16-bit @ 120 MS/s 40 MHz: 16-bit @ 120 MS/s Zero IF Very small size, low cost, and low power Wide analysis bandwidth Ideal for modulated signal analysis Alias rejection and image suppression IQ Calibration/Equalization 13
PXIe-5644R VST Receiver Architecture Calibration is needed to correct for I/Q gain and phase impairments 40 MHz: 16-bit @ 120 MS/s 40 MHz: 16-bit @ 120 MS/s Zero IF Very small size, low cost, and low power Wide analysis bandwidth Ideal for modulated signal analysis Alias rejection and image suppression IQ Calibration/Equalization 14
Traditional I/Q Calibration Approach Traditional approach only corrects for the impairments at a single frequency Center Frequency 15
Effects of IQ Impairments on QAM Traditional Image Wideband 16
Specifications NI PXIe-5673 VSG NI PXIe-5644R VST 17
Effects on 802.11ac Signal (80MHz) Traditional Correction Wideband Correction EVM -37.6dB EVM -47.2dB 18
Demo: 802.11ac EVM Performance 19
WLAN 802.11ac Performance Comparison 20
Up to 5 Signal Analyzers and Generators in a Single PXI Express Chassis MIMO Configurations Parallel Multi-DUT Test 21
Tenets of a Software-Designed Instrument
Open Source Closed Open 23
Hardware Programmability through Software Configuration and Processes RF Input Equivalent to ~200,000 lines of VHDL RF Output 24
Default Functionality 25
Progression of Customization 26
Component Disaggregation 27
Software-Designed Instrument Architecture Instrument Design Libraries User Application Host Interface Config. & Calibration Waveform Acquisition Waveform Generation Sync. Trigger Host FPGA 28
Multiple Processing Architectures Algorithm Requirements Floating point math Integer and fixed point math I/O High parallelism Complex conditional branching Low latency CPU X X X FPGA X X X X 29
NI PXIe-5644R Software
Instrument Design Library Host and FPGA Code From NI DSP RF In RF Out onboard signal processing RF input hardware configuration and calibration RF output hardware configuration and calibration Basecard ADC and DAC configuration Multirecord Acquisition Multiple waveform acquisition DRAM abstraction Waveform Sequencer Multiple waveform DRAM abstraction for waveform sequencing Trigger Synchronization Multi-module sample clock synchronization, T-Clk-like Embedded Configuration FPGA dynamic reconfiguration through register sequences, LabVIEW FPGA list mode 31
Instrument Design VIs NI PXIe-5644R APIs Color-coded and thicker VI border Bundled into Host and FPGA *.lvlib Located in c:\program Files\National Instruments\LabVIEW 2012\instr.lib Host and FPGA Palettes Typical subvi Instrument Design VI Host FPGA 32
LabVIEW 2012 Sample Projects for the VST Application / Host Layer Firmware / FPGA Layer 33
Simple VSA / VSG Sample Project Host FPGA User Application Simple VSA / VSG Sample Project Trigger Sync. RF In Config. & Cal. DSP Multi- Record Acq. Base- card Config. Wave- form Seq. DSP RF Out Config. & Cal. RF Hardware ADC DAC Instrument Design Libraries RF In RF Out 34
Simple VSA/VSG LabVIEW Sample Project Example Modifications
Example: Frequency Domain Trigger 36
Demo: Frequency Domain Trigger 37
Example: Power Level Servoing The Traditional Approach Settle VSG Settle DUT Measure Power Calculation With FPGA Settle DUT DUT Dig. Gain Measure Power Calc 38
Power Level Servoing Acquisition Loop 39
Demo: Power Level Servoing 40
FPGA-Based Power Level Servoing Results 41
Multiple Design Patterns Instrumentation Implements triggering and multi-record acquisition and generation. Provides a familiar look and feel to traditional instrument drivers on the host. Streaming Implements basic real-time streams to and from the host Serves as a starting point for implementing real-time DSP and re-routing data streams between loops, FPGAs, and host processing 42
VST Streaming Sample Project Host FPGA User Application VST Streaming Sample Project Trigger Sync. RF In Config. & Cal. DSP Base- card Config. DSP RF Out Config. & Cal. RF Hardware ADC DAC Instrument Design Libraries RF In RF Out 43
Streaming LabVIEW Sample Project Example Modifications
FPGA Loop-Back t, f 45
Demo: Streaming Loop-Back 46
Available IP and Examples
IP and Examples /vstgettingstarted Simple VSA / VSG VST Streaming 48
The networking and connectivity subsidiary of Qualcomm, Inc. Leading provider of wired and wireless technologies Serving mobile, computing, consumer electronics and networking channels GPIO GPIO 2.4/5 GHz 11ac Radio Front End WLAN RF CPU and Memory SOC, MAC and PHY Synthesizer PCIE Power Management PCIE 3.3 V REF CLK/ Crystal 802.11ac Device Block Diagram 49
Example WLAN Receive Chain 50
RF Standards Increasing Complexity 802.11a + b + g + 802.11n + 802.11ac 100+ Combinations 1,000+ Combinations 10,000+ Combinations 51
Vector Signal Transceiver / Device Under Test Integration Tx RF-out RF-in VSA Qualcomm Atheros 802.11ac Device Under Test Digital I/O Rx RF-in Digital Device Control RF-out VSG Digital I/O FPGA 52
Hardware Evolution 802.11a + b + g + 802.11n + 802.11ac Early 2000s Traditional Rack and Stack 2007 NI PXI RF Instrumentation 2012 NI PXI Vector Signal Transceiver 10X Faster Than Traditional 200X Faster Than Traditional 53
EVM (db) Versus Average Output Power Chain Results 54
Example: Channel Emulation 55
Real-Time MIMO Channel Emulation using 2 VSTs LabVIEW High-quality, wide-bandwidth RF Hardware Configuration and Application Control Fading Generation Powerful FPGA tightly integrated with RF in and out LabVIEW FPGA Interpolate RFin DDC/ Sample Rate Change BRAM Delay Bank Dot Product DUC/ Sample Rate Change RFout NI PXIe-5644R Vector Signal Transceiver LabVIEW FPGA Interpolate High-throughput, low-latency streaming through PXI Express peer-to-peer RFin DDC/ Sample Rate Change BRAM Delay Bank Dot Product DUC/ Sample Rate Change NI PXIe-5644R Vector Signal Transceiver Scalable and flexible from 1x1 up to 8x8 MIMO RFout Tight sample and phase synchronization for MIMO/ beamforming 56
Real-Time MIMO Channel Emulation using 2 VSTs LabVIEW High-quality, wide-bandwidth RF Hardware Configuration and Application Control Fading Generation Powerful FPGA tightly integrated with RF in and out LabVIEW FPGA Interpolate RFin DDC/ Sample Rate Change BRAM Delay Bank Dot Product DUC/ Sample Rate Change RFout NI PXIe-5644R Vector Signal Transceiver LabVIEW FPGA Interpolate High-throughput, low-latency streaming through PXI Express peer-to-peer RFin DDC/ Sample Rate Change BRAM Delay Bank Dot Product DUC/ Sample Rate Change NI PXIe-5644R Vector Signal Transceiver Scalable and flexible from 1x1 up to 8x8 MIMO RFout Tight sample and phase synchronization for MIMO/ beamforming 57
Demo: Channel Emulation 58
Channel Emulator LabVIEW Front Panel 59
Averna: First NI Partner VST Deployment BASED ON AVERNA S EXTENSIVE RF, FPGA, NI AND DSP EXPERTISE The DCE can generate up to 24 downstream and 8 upstream channels in real-time 60
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