Low Skew Output Buffer General Description The ICS92A-6 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to MHz. ICS92A-6 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 50 ps, the part acts as a zero delay buffer. Features Zero input - output delay Frequency range 25 - MHz (.V) High loop filter bandwidth ideal for Spread Spectrum applications. Less than 200 Jitter between outputs Skew controlled outputs Skew less than 250 between outputs Available in 8 pin 50 mil SOIC or 7 mil TSSOP package..v ±0% operation The ICS92A-6 comes in an eight pin 50 mil SOIC or 7 mil TSSOP package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. Block Diagram Pin Configuration 8 pin SOIC, TSSOP
Pin Descriptions PI UMBER PI AME TYPE REF 2 I reference frequency. 2 CLK2 OUT CLK OUT 4 GD 5 LK 6 VDD 7 LK4 8 LKOUT PWR C OUT C OUT C OUT Buffered clock output Buffered clock output Ground Buffered clock output P WR Power Supply (.V) Buffered clock output otes:. Guaranteed by design and characterization. ot subject to 00% test. 2. Weak pull-down. Weak pull-down on all outputs DESCRIPTIO Buffered clock output. Internal feedback on this pin 2
Absolute Maximum Ratings Supply Voltage....................... 7.0 V Logic s......................... GD 0.5 V to VDD +0.5 V Ambient Operating Temperature.......... 0 C to +70 C Storage Temperature................... 65 C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at.v V DD =.0.6 V, T A = 0 70 C unless otherwise stated DC Characteristics PARAMETER SYMBOL TEST CODITIOS MI TYP MAX UITS Low Voltage High Voltage V IL 0. 8 V V IH 2. 0 V Low Current High Current I IL I IH Output Low Voltage V OL Output High Voltage V OH Power Down Supply Current Supply Current IDD IDD VI = 0V 9 50. 0 µ A VI = VDD 0.0 00. 0 µ A I OL I OH = 25mA 0.25 0. 4 V = 25mA 2. 4 2. 9 V REF = 0 MHz 0. 50. 0 µ A Unloaded oututs at 66.66 MHz SEL inputs at VDD or GD 0.0 40. 0 ma otes:. Guaranteed by design and characterization. ot subject to 00% test. 2. All Skew specifications are mesured with a 50Ω transmission line, load teminated with 50Ω to.4v.. Duty cycle measured at.4v. 4. Skew measured at.4v on rising edges. Loading must be equal on outputs.
Switching Characteristics PARAMETER SYMBOL Output period t period t Duty Cycle Dt Duty Cycle Dt2 Rise Time tr Fall Time tf Rise Time tr Fall Time tf Delay, REF Rising Edge to CLKOUT, 2 R ising Edge Dr Output to Output Tskew Skew Device to Device Tdsk-Tdsk Skew Cycle to Cycle Tcyc-Tcyc Jitter PLL Lock Time tlock Jitter; Absolute Tjabs Jitter Jitter; - Sigma Tjs With CL=0pF With CL=0pF CODITIO MI 40.00 (25) 40.00 (25) TYP MAX 7.5 () 7.5 () UITS ns (MHz) ns (MHz) at.4v; CL=0pF 40. 0 50 60 % at VDD/2 Fout <66.6MHz CL=0pF CL=0pF CL=5pF CL=5pF between 0.8V and 2.0V: between 2.0V and 0.8V; between 0.8V and 2.0V: between 2.0V and 0.8V; 45 50 55 %.2. 5 ns.2. 5 ns ns ns at.4v 0 ± 50 All outputs equally loaded, CL=20pF at VDD/2 on the CLKOUT pins of devices outputs at 66.66 MHz, loaded Stable power supply, valid clock presented on REF pin @ 0,000 CL=0pF @ 0,000 CL=0pF cycles cycles 250 0 700 200.0 ms -00 70 00 4 0 otes:. Guaranteed by design and characterization. ot subject to 00% test. 2. REF input has a threshold voltage of.4v. All parameters expected with loaded outputs 4
Output to Output Skew The skew between CLKOUT and the CLK(-4) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must equally loaded. If the CLK(-4) outputs are less loaded than CLKOUT, CLK(-4) outputs will lead it; and if the CLK(-4) is more loaded than CLKOUT, CLK(-4) will lag the CLKOUT. Since the CLKOUT and the CLK(-4) outputs are identical, they all start at the same time, but different loads cause them to have different rise times and different times crossing the measurement thresholds. REF input and all outputs loaded Equally REF input and CLK(-4) outputs loaded equally, with CLKOUT loaded More. REF input and CLK(_4) outputs loaded equally, with CLKOUT loaded Less. Timing diagrams with different loading configurations 5
50 mil (arrow Body) SOIC IDEX AREA 2 D E H h x 45 A C L In Millimeters In Inches SYMBOL COMMO DIMESIOS COMMO DIMESIOS MI MAX MI MAX A.5.75.052.0688 A 0.0 0.25.0040.0098 B 0. 0.5.0.020 C 0.9 0.25.0075.0098 D E.80 4.00.497.574 e.27 BASIC 0.050 BASIC H 5.80 6.20.2284.2440 h 0.25 0.50.00.020 L 0.40.27.06.050 a 0 8 0 8 e B A SEATIG PLAE VARIATIOS D mm. D (inch) MI MAX MI MAX 8 4.80 5.00.890.968.0 (.004) Reference Doc.: JEDEC Publication 95, MS-02 50 mil (arrow Body) SOIC 0-000 Ordering Information 92AM-6LFT Example: XXXX A M PPP LFT Designation for tape and reel packaging Lead Option (optional) LF = Lead Free, RoHS Compliant Pattern umber (2 or digit number for parts with ROM code patterns) Package Type M = SOIC Revision Designator Device Type 6
IDEX AREA 2 D E E c L In Millimeters In Inches SYMBOL COMMO DIMESIOS COMMO DIMESIOS MI MAX MI MAX A --.20 --.047 A 0.05 0.5.002.006 A2 0.80.05.02.04 b 0.9 0.0.007.02 c 0.09 0.20.005.008 D E 6.40 BASIC 0.252 BASIC E 4.0 4.50.69.77 e 0.65 BASIC 0.0256 BASIC L 0.45 0.75.08.00 0 8 0 8 aaa -- 0.0 --.004 A2 e -Cb A A SEATIG PLAE C aaa VARIATIOS D mm. D (inch) MI MAX MI MAX 8 2.90.0.4.22 Reference Doc.: JEDEC Publication 95, MO-5 0-005 4.40 mm. Body, 0.65 mm. pitch TSSOP (7 mil) (0.0256 Inch) Ordering Information 92AG-6LF-T Example: XXXX A G PPP LFT Designation for tape and reel packaging Lead Option (optional) LF = Lead Free, RoHS Compliant Pattern umber (2 or digit number for parts with ROM code patterns) Package Type G = TSSOP Revision Designator Device Type 7
Revision History Rev. Issue Date Description Page # H 9//2004 Updated Lead Free information 6-7 I /2/2004 Added L option 6-7 J 4/26/2007 Removed L option superceded by LF. 6-7 K 8//2007 Updated Switching Characteristics Rise/Fall time. 4 L 2/9/2008 Removed ICS prefix from ordering information. 6-7 8