A New Multilevel Inverter Topology with Reduced Number of Power Switches

A New Multilevel Inverter Topology with Reduced Number of Power Switches L. M. A.Beigi 1, N. A. Azli 2, F. Khosravi 3, E. Najafi 4, and A. Kaykhosravi 5 Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 UTM Johor Bahru, Malaysia lili_beigi@yahoo.com 1 naziha@ieee.org 2 Abstract Recent years have seen the emergence of various multilevel inverter topologies for high voltage and high power applications. This is mainly due to the attractive advantages of multilevel inverters such as lower Total Harmonic Distortion (THD) in the output voltage, higher efficiency, less stress on the power switches and low Electromagnetic Interference (EMI). The main problem of using multilevel inverters is the number of power switches that normally contributes to the complexity in controlling the power switches and high cost. In this paper a new structure of a nine-level inverter is proposed to improve the multilevel inverter performance by compensating these disadvantages. This topology employs fewer power switches compared to that of conventional multilevel inverters. In addition a modified Pulse width Modulation (PWM) control method has been designed for this new inverter structure that requires less number of carrier signals. The proposed topology and its control method are described and the results of a simulation study conducted have illustrated the performance of the overall system, thus revealing the advantages of this structure compared to conventional topologies. Keywords Multilevel inverter, Total harmonic distortion, PWM method I. INTRODUCTION In recent years multilevel inverters seem to have drawn more attention due to the ability of the topology to perform well in high voltage and high power applications. Although the idea on the multilevel structure of inverters has been introduced more than thirty years ago, majority of the improvements made on it has only been promoted in the past ten years. The output voltage waveform of a multilevel inverter is produced by several sources of DC voltages which may be obtained from batteries, solar cells or fuel cells [1]. With an increasing number of DC voltage sources, the inverter output voltage waveform becomes closer to a sinusoidal waveform. Due to the utilization of several DC sources, the power switches have lower voltage stresses. The power switches can be designed to work at both fundamental and high switching frequency. It must be noted that lower switching frequency causes reduction in the switching losses and increase in efficiency. Various types of multilevel inverters have been proposed in different literature [2], [3]. Among the common ones is the Cascaded H-bridge Multilevel Inverter (CHMI) with separate DC sources and its derivatives [4], the Diode Clamped Multilevel Inverter (DCMI) [5] and the Flying Capacitor Multilevel Inverter (FCMI) [6]. Each of these topologies has a specific method in producing the output levels. Due to the stepped output waveform characteristic of a multilevel inverter, its Total Harmonic Distortion (THD) is low compared to the conventional two-level inverters. All the topologies share a common main drawback in terms of the requirement for large number of power switches as the number of levels is increased. In general, for m number of levels, the number of power switches required is 2(m-1) for CHMI, DCMI and FCMI. The higher number of power switches in a multilevel inverter leads to the complexity of its circuit control high losses and low efficiency. Due to the modularized structure of a CHMI, the problems related to unbalanced DC source do not occur, hence allowing it to be extended to more levels. For this type of multilevel inverter, numerous topologies have been proposed and reported in literature [3]. The DCMI employs a bank of series capacitors [7] while in the FCMI topology floating capacitors rather than series capacitors are applied to clamp the voltage levels [8]. The problems associated with these capacitors have hindered common use of this multilevel inverter type. For the DCMI, balancing of the capacitors is very problematic particularly with high number of levels. Furthermore, because of the neutral-point balancing problems, more than three levels of this structure is not easy to implement [9]. This paper proposes a new multilevel inverter structure with less number of power switches that can contribute to further decrease in losses and thus increases efficiency. For the same number of level, this proposed structure has the advantage of reduced number of switching devices compared to the conventional CHMI and DCMI. Furthermore a modified Pulse width Modulation (PWM) control method is applied to this new multilevel inverter topology in producing its output voltage. Simulation of the designed multilevel inverter structure and its modulation technique is achieved using MATLAB/Simulink. The results of the simulation work are presented in demonstrating its performance in terms of producing the multilevel PWM output. II. THE PROPOSED INVERTER Inverters with higher number of output levels are known to offer several advantages over those with lower number of output levels when employed in applications such as active power filters and induction motor drives [10]. For instance nine-level inverters have smaller output voltage steps hence 978-1-4673-5019-8/12/$31.00 2012 IEEE 55

lower ripple and THD in the output voltage and current, compared with three- and five-level inverters [11], [12]. Another important factor that must be noted is that with a nine-level inverter, the inductor connected at the output of power systems will be smaller in size and value. The main drawback associated with using a nine-level inverter however, is the number of power switches used. Conventional nine-level inverters need sixteen power switches. The high number of switches causes complexity in the control circuit while increasing the overall circuit size. Based on the interesting advantages of a nine-level inverter over the three-, five- and seven- level inverters, a new nine-level inverter with less number of power switches is proposed. Reduction in the number of power switches in inverters contributes to the following advantages: Less losses Easier control Reduction in cost Reduction in weight The structure of the new nine-level inverter is shown in Fig. 1. Its operation is based on a combinational hybrid multilevel inverter, which consists of upper and bottom inverter as illustrated in Fig. 2. The upper inverter has two legs where by a three-level diode clamped phase leg is used in one leg and a conventional two-level phase is used for the other leg. Two DC sources in series are used to supply the upper inverter. The interesting fact about this structure is that, the combinational circuit performs like a single-phase H-bridge inverter and not like a diode clamped inverter and provides a five-level output voltage. The upper multilevel inverter provides a five-level output voltage just by using six switches compared with the conventional CHMIs which use eight power switches to provide the same level. Fig. 3 shows the conventional five-level CHMI for comparison purposes. For the proposed nine-level inverter, the upper five-level inverter works like an H-bridge inverter. The main difference is that in a typical H-bridge inverter, zero cannot be provided in each leg while in this structure by adding two diodes on one of the H-bridge legs, zero voltage can be generated in this leg. By adding zero on the leg of the H-bridge inverter the output voltage breaks to more levels. The bottom inverter consists of a conventional two-level phase inverter, which switches between two levels of +V dc and -V dc. Two DC sources are used to supply the bottom inverter too. The switches at the bottom inverter operate at the fundamental frequency while the switches at the upper inverter operate at a higher PWM frequency. For the bottom inverter power switches with high voltage rating but not necessarily high frequency rating must be used. On the other hand, for the upper inverter power switches with high frequency rating but not necessarily high voltage rating are needed [5]. In general, Insulated Gate-Commutated Thyristors (IGCTs) can be used at a higher volt-ampere rating than Insulated Gate Bipolar Transistors (IGBTs). However, the latter can be operated at a higher switching frequency than the former. This suggests that with the proposed multilevel inverter, IGBTs can be used for the upper inverter to provide the five-level DC outputs of +V dc, +1/2V dc, 0, -V dc and - 1/2V dc while IGCTs can be employed for the bottom inverter to provide the two-level +V dc and V dc. The IGCT based bottom inverter operates at the fundamental switching frequency while the IGBT based upper inverter operates at PWM switching mode. This contributes to further reduction in switching losses for the proposed nine-level inverter compared to the conventional nine-level CHMI as shown in Fig. 4. Fig. 1 The proposed nine-level inverter structure Fig. 2 Upper five-level inverter Bottom two-level inverter 56

The new structure of a nine-level inverter can operate at a higher voltage with lower switching losses and can produce the same outputs as that of conventional nine-level inverters but with reduced number of power switches. Indeed with the proposed structure just eight switches are used to obtain a nine-level output compared with the sixteen switches that are required for conventional nine-level topologies. Table1. Switching states of the new nine-level inverter S1 S2 S3 S4 S5 S6 S7 S8 V out 1 1 0 0 0 1 1 0 2Vdc 0 1 1 0 0 1 1 0 3/2Vdc 0 0 1 1 0 1 1 0 Vdc 0 1 1 0 1 0 1 0 1/2Vdc 1 1 0 0 0 1 0 1 0 0 1 1 0 0 1 0 1-1/2Vdc 1 1 0 0 1 0 0 1 - Vdc 0 1 1 0 1 0 0 1-3/2Vdc 0 0 1 1 1 0 0 1-2Vdc III. PWM CONTROL METHOD Fig. 3 The conventional five-level CHMI As low switching losses is a typical requirement of the PWM process, the bottom inverter of Fig. 2 is controlled at the fundamental frequency while the upper inverter of Fig. 2 is driven at the PWM frequency. In general, the PWM signal is generated by comparing a high frequency carrier with a low frequency sinusoidal signal known as the reference signal. In conventional multilevel inverters the number of carrier signals required to produce the PWM signal is m - 1 where m is the number of levels. Hence, eight carrier signals are required to realize a nine-level inverter, which led to complexity of circuit control. In order to reduce the number of carriers and provide a simpler controller a PWM method as suggested in [13] has been modified for application in the proposed nine-level inverter In this modified PWM method only one carrier signal is needed as such the control signals are easily generated compared to that of conventional multilevel inverters. As can be seen in Fig. 5 by breaking the reference signal into four sections, only one carrier signal is used. The reference signal for the five-level upper inverter of Fig. 2 is broken by using equations (1) - (5). f(t) = 4m a sin(ωt) (1) Fig. 4 The conventional nine-level CHMI Referring to Fig. 1 the output voltage of the bottom inverter is either V dc (S7 closed) or -V dc (S8 closed). This leg is connected in series with the upper five-level inverter, that generates the values of V dc (S1, S2, S6 closed), V dc /2 (S2, S3, S6 closed), 0 (S1, S2, S5 closed or S3, S4, S6 closed), -V dc (S3, S4, S5 closed) and -V dc /2 (S2, S3, S5 closed). Table 1 shows the switching states of the nine-level inverter. From the switching states, it can be deduced that in the positive half cycle, S7 is on, while in the negative half cycle S8 is on. This means that S7 and S8 operate at the fundamental frequency that leads to lower switching losses and simple control circuit as highlighted earlier. 1 ; f t 0 A= 0 ; f t 0 1 ; f t 1 B= 0 ; f t 1 1 ; f t 2 C= 0 ; f t 2 1 ; f t 3 D= 0 ; f t 3 (2) (3) (4) (5) 57

Where; f(t) is the reference signal, m a is the Modulation Index (0-1) A is multiplexing signal #1 B is multiplexing signal #2 C is multiplexing signal #3 D is multiplexing signal #4 Fig. 7 depicts the general PWM signal obtained from the intersection between the broken reference signal and the carrier signal. The gate signals of each of the upper inverter power devices for the nine-level inverter are generated by different combinations of the multiplexing signals and the general PWM signal. These multiplexing signals are as shown in Fig. 6. Fig. 7 ; Intersection of broken signal and carrier signal ; General PWM signal of the upper inverter Fig. 5 ; Reference signal ; Broken reference signal IV. SIMULATION RESULTS OF THE PROPOSED NINE-LEVEL INVERTER A simulation study has been conducted on the proposed single-phase nine-level inverter. The DC source voltage is set to be 50 V for the upper inverter and 100 V for the bottom inverter. The frequency of the carrier signal is 10kHz. The PWM control method as explained earlier is applied to the nine-level inverter. Fig. 8 and Fig. 9 illustrate the simulation results of the PWM output voltage and harmonic order respectively of the proposed nine-level inverter for a modulation index (m a ) of 0.8. By changing m a to a higher value, the fundamental PWM output voltage can be increased. Fig. 10 shows the PWM output voltage of the nine-level inverter for m a =1 while Fig.11 illustrates its harmonic spectra. Although Fig. 8 looks similar to Fig. 10, the difference can actually be observed in terms of the amplitude of the fundamental of the output voltage as well as the THD achieved as depicted from Fig. 9 and Fig. 11 respectively. The difference in the amplitude of the fundamental of the output voltage is obviously due to the difference in the PWM pulse pattern in the output voltage for different values of m a. Fig. 6 The multiplexing signals (A, B, C, D) 58

V. CONCLUSIONS This paper has presented a new structure of a nine-level voltage source inverter with less number of switches. The multilevel inverter has an additional leg that consists of two diode clamps and two switches to generate a zero voltage in this leg. As a result it can provide more voltage levels with less number of switches compared with the conventional multilevel inverter type. Advantages such as less output voltage THD, less voltage stress on the power switches, high efficiency, smaller in size and reduced cost are inevitable with such nine-level inverter structure which can prove to be useful in various applications. Fig. 8 PWM output voltage of the proposed nine-level inverter at m a=0.8 Fig. 9 PWM output voltage harmonic spectra of the proposed nine-level inverter at m a=0.8 Fig. 10 PWM output voltage of the proposed nine-level inverter at m a=1 Fig.11 PWM output voltage harmonic spectra of the inverter at m a=1 proposed nine-level ACKNOWLEDGEMENT The authors would like to thank the Research Management Centre (RMC) of Universiti Teknologi Malaysia and the Ministry of Higher Education (MOHE) for the funding of this project through Vote Number Q.J130000.7123.00H87. REFERENCES [1] J.S. Lai and F.Z. Peng, Multileve Converters A New Breed of Power Converters, IEEE Trans. Ind. Appl., Vol. 32, No.3, 1996, pp. 509-517. [2] R.H. Baker, High-Voltage Converter Circuit, U.S. Patent Number 4,203,151, May 1980. [3] E. Babaei, M. T. Haque, and S. H. Hosseini, A novel structure for multilevel converters, in Proc. ICEMS, 2005, vol. 2, pp. 1278 1283.. [4] K. Corzine and Y. Familiant, A New Cascaded Multilevel H-Bridge Drive, IEEE Transactions Power Electron, Vol. 17, No.1, 2002, pp. 125-131. [5] X. Yuan and I. Barbi, Fundamentals of a New Diode Clamping multilevel Inverter, IEEE Transactions Power Electron., Vol. 15, No.4, 2000, pp. 711-718. [6] J. Rodriguez, J. S. Lai and F. Z. Peng, Multilevel inverters: Survey of topologies, controls, and applications, IEEE Trans. Ind. Applicat., vol. 49, no. 4, pp. 724-738, Aug. 2002. [7] A.Nabae, I. Takahashi, and H. Akagi, A new neutral-point clamped PWM inverter, IEEE Trans. Ind. Applicat., vol. IA-17, no. 5, pp. 518 523, Sep./Oct 1981. [8] T. A. Meynard and H. Foch, Multi-level conversion: High voltage choppers and voltage-source inverters, in Proc. IEEE PESC, Toledo, Spain 1992, pp. 397 403. [9] J. Rodriguez, J. S. Lai and F. Z. Peng, Multilevel Inverters: Survey of Topologies, Controls, and Applications, IEEE Transactions on Industry Applications, vol. 49, no. 4, Aug. 2002, pp. 724-738. [10] Lim, P.Y; Azli, N.A., "Modular Structured Multilevel Inverter Active Power Filters with Unified Constant-Frequency Integration Control for AC loads "Power Electronics and Drives Systems, 2007, PEDS 2007 International Conference [11] J. N. Chiasson, L. M. Tolbert, K. J. McKenzie, Z. Du, A New Approach to Solving the Harmonic Elimination Equations for a Multilevel Converter, IEEE Industry Applications Society Annual Meeting, October 12-16, 2003, Salt Lake City, Utah, pp. 640-645 [12] N. A. Azli and P. Y. Lim, "Modular Structured Multilevel Inverter with Unified Constant-Frequency Integration Control for Active Power Filters," International Conference on Power Electronics and Drives Systems,( PEDS), Vol. 2, pp. 1312 1316, Nov. 2005 [13] Khomfoi, S.; Aimsaard, C.; "A 5-level cascaded hybrid multilevel inverter for interfacing with renewable energy resources," Electrical Engineering/Electronics, Computer, Telecommunications and Technology, 2009. ECTI-CON 2009. 6th International Conference on, vol.01, no., pp.284-287, 6-9 May 2009 59