FDTD Analysis of High-Speed Cells in Silicon Integrated Circuits Neven Orhanovic and Norio Matsui Applied Simulation Technology Gateway Place, Suite 8 San Jose, CA 9 {neven, matsui}@apsimtech.com Abstract This paper introduces FDTD to the problem of Silicon integrated circuit (IC) analysis. The analyzed IC cell is decomposed into active and passive parts. The active part is analyzed using the circuit analysis approach of while the larger passive on-chip interconnect part is analyzed using the full wave finite difference time domain (FDTD) method. The two methods are coupled in the time domain at the connecting ports. All of the modes propagating on the metalinsulator-semiconductor (MIS) interconnect are taken into account accurately. The advantages of both the circuit and the full wave analysis approaches are retained while avoiding inaccuracies associated with the use of transforms or inverse transforms. The analysis procedure is illustrated on a few small IC cell layout examples.. Introduction Continuing advances in high-speed semiconductor device technologies have increased the importance of interconnects in the overall behavior of the integrated circuit (IC). These onchip interconnects typically consist of metal-insulator-semiconductor (MIS) or semiconductor-insulator-semiconductor transmission structures. The presence of the semiconductors gives rise to three fundamental modes of propagation []. The three fundamental modes, combined with the conductor losses, result in serious degradation of the signals propagated on the interconnect. Accurate modeling of interconnect propagation, together with the modeling of semiconductor devices, is an important requirement in the design of advanced ICs. Due to the small size of the semiconductor device compared to the smallest wavelength in the operating frequency spectrum, the devices lend themselves to lumped circuit type modeling. Sophisticated modes have been developed to describe the behavior of semiconductor devices. These ever-improving models contain large numbers of parameters that are either directly related to the physical behavior of the device or serve as curve fitting parameters. In either case, these models are capable of modeling semiconductor devices accurately over wide signal amplitude and frequency ranges. In contrast to the semiconductor devices, the interconnect structures and the passive elements in today s high speed ICs are often comparable to, or larger than, the smallest wavelengths of the propagating modes. The larger electrical lengths of the interconnects, coupled with the complex three dimensional (D) nature of their geometries, the presence of nearby neighbors, and the more complex nature of the propagated signal, make direct circuit mo deling very difficult. Furthermore, the broadband operation of today's ICs and the nonlinear behavior of the devices demand time domain interconnect models for the analysis. Finally, some of the same reasons mentioned above, together with the high accuracy requirements in leading edge semiconductor device design and research, make full wave methods the leading candidates for accurate on-chip interconnect analysis. The finite difference time domain (FDTD) method has been used successfully to characterize signal propagation on IC MIS lines terminated in linear devices []. Good agreement with measurements over a wide frequency range has been obtained. This method can be coupled with the circuit analysis approach of using FDTD techniques []. The result is a very general IC simulation approach that can take into account semiconductor substrate effects as well as model nonlinear devices. In this paper, we introduce FDTD to the problem of Silicon IC analysis. The analysis procedure is illustrated on a few small IC cell layout examples. Results obtained using the FDTD approach are compared with those obtained using conventional modeling. The main limitation of the FDTD analysis approach is in the computation time and memory required to analyze the D interconnect structure using FDTD. As a consequence, only smaller units (cells) of the IC can be analyzed. Analysis of a whole IC using this method is not possible on today's computers. Nevertheless, very useful smaller structures can be analyzed with high accuracy.. Overview of FDTD The first step in the FDTD analysis procedure is to partition the problem into two parts: ) the distributed part of the analyzed structure that is to be solved using FDTD and ) the circuit part of the structure that is to be solved using. The two parts of the problem are connected through a number of FDTD ports. At each time step, FDTD uses its field solution to calculate the elements of the port equivalent circuit and passes the information to. solves the resulting circuit and returns the calculated voltage to FDTD. FDTD then updates the electric field at the port based on the voltage supplied by. The procedure is illustrated in Figure, together with the equivalent circuits of the ports. The calculation of the DC solution for the analyzed structure requires the calculation of the initial field distribution in the FDTD part of the structure. This calculation can be computationally expensive. The problem is avoided by making use of the linearity of the FDTD part of the structure and separating all of the port voltages and currents into constant and time-varying components. FDTD then works with only the time -varying components of the solution while deals with the actual (DC AC) variables. The DC solution is performed only by [].
I N (t) I N (t) FDTD part of the analyzed structure I NM (t) Figure : FDTD calculation procedure. The FDTD structure is on the left. An arbitrary circuit is on the right. The arrows represent interprocess communication.. Application to ICs In order to apply FDTD to a semiconductor IC, the chosen physical design must be partitioned into FDTD and parts. Typically, the design will consist of a large semiconductor substrate populated by islands of differently doped semiconductor material. The resulting inhomogeneous semiconductor is covered by one ore more insulating materials (usually oxides). Layers of metal, polycrystalline semiconductor, and metal vias are contained within the insulating materials making connections between doped islands on the substrate. For analysis purposes, we earmark the large passive elements for FDTD modeling. The resulting FDTD structure consists of conductors, buried in a layered insulator, positioned over an inhomogeneous semiconductor material. All of the remaining smaller structures are modeled together with the active devices using conventional circuit models in. The ports connecting the FDTD and partitions are positioned between conductors that pass through the partition boundaries. The partitioning procedure is illustrated in Fig. as well as in the examples below. F D T D S P I C E FDTD M I Nk (t) V k (t) V (t) V (t) V N (t) Conductor Inhomogeneous Semiconductor part of the analyzed structure Oxide Figure : Partitioning the problem for FDTD analysis. The largest design that can be analyzed on a given computer using FDTD is dictated by the number and size of the cells in the FDTD partition. Therefore, it is essential to keep the number of FDTD cells at a minimum. This can be done by using nonuniform or multigrid FDTD methods.. Examples The FDTD analysis approach is illustrated on a few Silicon IC examples. Although the widely spread complementary metal oxide semiconductor (CMOS) IC technology was chosen for the examples, the approach is not limited to this technology.. CMOS Buffer In CMOS digital designs it is common to cascade logical gates to achieve required performance characteristics. An example of such a procedure is in using an even number of inverter circuits to build a data buffer. The characteristics and the dimensions of the cascaded inverters will change as we proceed down the inverter chain. As a result, the interconnect lengths from device to device can vary considerably. In this example we evaluate the effect of changing interconnect lengths between two digital devices on the output signal. The structure chosen for this example is shown in Fig.. d Figure : Top view of CMOS buffer layout. The length of the interconnect is variable: Metal (V CC and V SS ), Metal (Signal). For simplicity, both inverters are the same. The input to the buffer is at the center of the pad labeled IN and the output is at the center of the pad labeled OUT. An ideal. V voltage source connects between the terminals labeled V CC and V SS. Figure also shows a drawing grid superimposed on the structure. The separation between the nodes of the grid is µm. The length and width of the n-mos transistor gate are L= µm and W= µm, respectively. The corresponding dimensions for the gate of the p-mos transistor are L= µm and W=6. µm. The V CC and V SS interconnects are µm wide and. µm thick. The central signal conductor is µm wide and.6 µm thick. All conductors have a conductivity of.9 7 S/m. The layer stackup is shown in Fig..
. µm. µm. µm.6 µm.7 µm µm. µm nm Oxide, ε r =.97 Metal, σ=.97 7 Metal, σ=.97 7 Polysilicon Si Substrate ε r =.7, σ=9.8 S/m Ideal Ground Plane Figure : Layer stackup for all examples. The input of the structure is driven by a trapezoidal voltage source with % rise and fall times of ps. The amplitude of the driving voltage is. V. We consider two device to device separations: d= µm and d= µm, and we model the structures using two modeling approaches. In the first approach, we extract a conventional circuit model of the structure. Automated model generation software is used to extract the MOSFET models [, ]. This approach is similar to the procedure that most of today s IC fabrication houses use to model CMOS designs. Cascaded, lumped, RLC T sections are used to model the interconnects. The capacitance, C, is computed using D electro -static analysis assuming that the Si substrate behaves as an ideal conductor. The inductance, L, is computed from a magneto-static solution. The DC resistance of the interconnects is used to compute the values of the R elements for the sections. In the second modeling approach, we decompose the structure into FDTD and parts as shown in Figures and 6. The interconnects on layers Metal and Metal are modeled in FDTD, together with the vias from Metal to Metal. The rest of the structure is modeled in. Five ports are used to interface between FDTD and. The driving voltage source is included in the model. Figure 6: part of structure analyzed in Example. We first analyze the example for the case when the device separation shown in Fig. is d= µm. This corresponds to short interconnects between devices as would be the case for two adjacent gates. The voltage responses obtained by the two approaches are compared in Figures 7 and 8. Figure 7 shows the voltage at the output of the first inverter and Fig. 8 shows the output voltage of the second inverter (buffer output). v SIG (t) [V].... FDTD- -... Figure 7: Output of the first inverter with d= µm.. FDTD-. v OUT (t) [V].. -... Figure : FDTD part of the structure analyzed in Example. Figure 8: Output of CMOS buffer with d= µm.
In all of the plots, the solid lines correspond to the results obtained by FDTD and the dashed lines correspond to the conventional results. It is seen that extremely good agreement is obtained between FDTD and the conventional approach for the case of short interconnect lengths. FDTD also calculates the electric and magnetic fields everywhere in the structure. The fields can be useful for examining the circuit behavior in more detail. The distribution of the vertical component of the electric field (z-component) in a plane orthogonal to the field is shown in Fig. 9. The plane is parallel to the semiconductor surface and passes half way between metal layers and. We can observe the effect of current crowding near the edges and corners of the planar conductors as well as the standing waves on the signal conductor. Ez [kv/m] 8 6 - - -6 - y [um] x [um] - - Figure 9: Electric field distribution for the structure with d= µm (on the z=const. plane half way between Metal and Metal at t= ps). As the length of the interconnect increases, we can expect the differences between the two modeling approaches to become larger due to the complex nature of the on-chip wave propagation that is not accounted for in the quasi-static interconnect model. To illustrate this, we analyze the same structure with the device separation increased to d= µm. v SIG (t) [V]... FDTD- The voltage responses of the two inverter outputs are shown in Figures and. Considerable differences in the signal propagated between the two inverters are visible in Fig.. These differences cause considerably different signal delays at the buffer output (Fig. ). It is interesting to note that the quasi-static model overestimates the delay in this example. This is partly due to the fact that the substrate was treated as a conductor for C extraction. Also, single frequency R, L, and C models, corresponding to the low frequency limit, were used to model the interconnect in the conventional model. Better agreement between the FDTD and circuit modeling approaches can be expected if more complex interconnect models are used. However, more sophisticated interconnect models require computationally more expensive parameter extraction techniques (often full wave). v OUT (t) [V].... FDTD- -... Figure : Output of CMOS buffer with d= µm. The field distribution for this structure obtained by FDTD is shown in Fig.. The figure also shows the nonuniform grid that was used to analyze the structure efficiently. The sizes of the grid cells are increasing in a geometric progression from neighbor to neighbor in order to maintain FDTD errors within reasonable limits. Ez [kv/m] 8 6 - - -6. - y [um] 6 x [um] 8 - - -... Figure : Output of first inverter with d= µm. Figure : Electric field distribution for the structure with d= µm (on the z=const. plane half way between Metal and Metal at t= ps).
. Analog CMOS Voltage Reference Circuit In this example we examine an analog CMOS circuit. In analog circuit design one often needs voltage or current sources that are independent of the supply voltage or temperature. Figure shows a CMOS based diode referenced self-biasing circuit. The purpose of the circuit is to maintain a constant voltage between the V DD and V PBIAS terminals. This voltage can then be used to bias other analog circuits. V DD V PBIAS trapezoidal fashion. The rise and fall times of the trapezoidal pulse are ps, the hold time is 7 ps, and the period is ps. The structure shown in Fig. is analyzed using two separate approaches. In the first approach we use the conventional circuit modeling procedure and in the second approach we employ FDTD. The top view of the FDTD part of the analyzed structure is shown in Fig.. The same figure also shows the location of the ideal voltage source used as the excitation for the structure. It should be noted that the resistor that is laid out in the form of a U shaped n-well in the lower left part of Fig. is modeled by a resistor element in the FDTD case. This is done in order to simp lify the interface ports between the FDTD and partitions, which are selected in a similar manner as in Example. V DD (t) Figure : Diode referenced biasing circuit. The IC layout of the circuit is shown in Fig.. The nodes of the drawing grid shown in Fig. are µm apart. The layer stackup is the same as in the previous example. Figure : Top view of FDTD partition used in Example. The results of the two approaches are shown in Fig. 6. It is seen that the conventional model predicts smaller voltage variations of the biasing circuit than FDTD. 6 V DD FDTD- v(t) [V] Figure : IC layout of biasing circuit from Fig.. We evaluate the effectiveness of the biasing circuit by varying the supply voltage V DD and observing the output voltage V PBIAS. The supply voltage is varied from to V in a t [ps] Figure 6: Voltage response of Example.
. Concluding Remarks A hybrid full wave circuit simulator method based on FDTD was applied to the problem of IC analysis. The method fully takes into account semiconductor substrate effects on MIS line propagation. It also allows for the treatment of nonlinear devices. The analysis procedure was illustrated on a few simple CMOS IC cell examples. Good agreement with the conventional modeling approach was observed for the case of short interconnect lengths. For longer interconnect lengths, the full wave hybrid approach gives more accurate propagation delays and signal amplitudes than the traditional quasi-static approach. Due to its time domain nature, FDTD can be applied directly to digital IC design problems resulting in both conventional voltage and current results as well as field, voltage, and current distributions within the analyzed MIS structure. This provides the IC designer with more insight in to the analyzed problem. The method can be useful for analyzing critical nets or important small cells in IC designs. It can also be useful in evaluating faster, less accurate, IC analysis methods. References. H. Hasegawa, M. Furukawa, and H. Yanai, Properties of microstrip line on Si-Si system, IEEE Trans. Microwave Theory Tech., vol. 9, no., pp. 869 88, Nov. 97.. T. Shibata and E. Sano, Characterization of MIS structure coplanar transmission lines for investigation of signal propagation in integrated circuits, IEEE Trans. Microwave Theory Tech., vol. 8, no. 7, pp. 88 889, July 99.. N. Orhanovic, R. Raghuram, and N. Matsui, Full wave analysis of planar interconnect structures using FDTD, st ECTC Proceedings, May.. David Boyce, LASI, Layout System for Individuals, http://www.mrc.uidaho.edu/vlsi/cad_free.html.. R. J. Baker, H. W. Li, D. Boyce, CMOS Circuit Design, Layout, and Simulation, IEEE Press, New York, 998.