EE 501 Lab9 Widlar Biasing Circuit and Bandgap Reference Circuit

Similar documents
EE 501 Lab7 Bandgap Reference Circuit

EE 501 Lab 11 Common mode feedback (CMFB) circuit

EE 501 Lab 4 Design of two stage op amp with miller compensation

0.85V. 2. vs. I W / L

An Improved Bandgap Reference (BGR) Circuit with Constant Voltage and Current Outputs

Short Channel Bandgap Voltage Reference

Lecture 4: Voltage References

Lab 4: Supply Independent Current Source Design

ECEN 474/704 Lab 5: Frequency Response of Inverting Amplifiers

Analog Integrated Circuit Configurations

Design for MOSIS Education Program

High-Speed Serial Interface Circuits and Systems

Revision History. Contents

Analog CMOS Interface Circuits for UMSI Chip of Environmental Monitoring Microsystem

Chapter #3: Diodes. from Microelectronic Circuits Text by Sedra and Smith Oxford Publishing

3 ppm Ultra Wide Range Curvature Compensated Bandgap Reference

Design and Implementation of less quiescent current, less dropout LDO Regulator in 90nm Technology Madhukumar A S #1, M.

Tuesday, February 1st, 9:15 12:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo

Low-voltage, High-precision Bandgap Current Reference Circuit

Microelectronic Circuits, Kyung Hee Univ. Spring, Chapter 3. Diodes

EE 501 Lab 10 Output Amplifier Due: December 10th, 2015

A Compact Folded-cascode Operational Amplifier with Class-AB Output Stage

Federal Urdu University of Arts, Science & Technology Islamabad Pakistan THIRD SEMESTER ELECTRONICS - II BASIC ELECTRICAL & ELECTRONICS LAB

What is the typical voltage gain of the basic two stage CMOS opamp we studied? (i) 20dB (ii) 40dB (iii) 80dB (iv) 100dB

High Voltage Operational Amplifiers in SOI Technology

Chapter 12 Opertational Amplifier Circuits

VCO Design Project ECE218B Winter 2011

EE 140 HW7 SOLUTION 1. OPA334. a. From the data sheet, we see that. Vss 0.1V Vcm Vdd 1.5V

ECE 4430 Project 1: Design of BMR and BGR Student 1: Moez Karim Aziz Student 2: Hanbin (Victor) Ying 10/13/2016

ECEN 5008: Analog IC Design. Final Exam

EECS3611 Analog Integrated Circuit Design. Lecture 3. Current Source and Current Mirror

You will be asked to make the following statement and provide your signature on the top of your solutions.

[Kumar, 2(9): September, 2013] ISSN: Impact Factor: 1.852

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design.

Chapter 10 Feedback ECE 3120 Microelectronics II Dr. Suketu Naik

Beta Multiplier and Bandgap Reference Design

ECE315 / ECE515 Lecture 9 Date:

Nonlinear Macromodeling of Amplifiers and Applications to Filter Design.

UNIT 4 BIASING AND STABILIZATION

Design and Layout of Two Stage High Bandwidth Operational Amplifier

EE140: Lab 5, Project Week 2

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Phy 335, Unit 4 Transistors and transistor circuits (part one)

Design of Low-Dropout Regulator

Electronics 1 Lab (CME 2410) School of Informatics & Computing German Jordanian University Laboratory Experiment (10) Junction FETs

Georgia Institute of Technology School of Electrical and Computer Engineering. Midterm Exam

Analog Integrated Circuits. Lecture 7: OpampDesign

EE 501 Lab 1 Exploring Transistor Characteristics

Lab 2: Discrete BJT Op-Amps (Part I)

An Analog Phase-Locked Loop

30 ma flash LDO voltage regulator (output voltage 1.8 ± 0.2 V)

Lecture #3: Voltage Regulator

Chapter 7 Building Blocks of Integrated Circuit Amplifiers: Part D: Advanced Current Mirrors

EE140: Lab 5, Project Week 2

Design Analysis and Performance Comparison of Low Power High Gain 2nd Stage Differential Amplifier Along with 1st Stage

EE 330 Laboratory 8 Discrete Semiconductor Amplifiers

ECE315 / ECE515 Lecture 7 Date:

Sensors & Transducers Published by IFSA Publishing, S. L.,

Sub-1V Curvature Compensated Bandgap Reference. Kevin Tom

Design of Rail-to-Rail Op-Amp in 90nm Technology

James Lunsford HW2 2/7/2017 ECEN 607

EE 230 Lab Lab 9. Prior to Lab

Exam Below are two schematics of current sources implemented with MOSFETs. Which current source has the best compliance voltage?

Transistor Biasing and Operational amplifier fundamentals. OP-amp Fundamentals and its DC characteristics. BJT biasing schemes

APPLICATION NOTE AN-009. GaN Essentials. AN-009: Bias Sequencing and Temperature Compensation for GaN HEMTs

EE 330 Laboratory 8 Discrete Semiconductor Amplifiers

DIGITAL VLSI LAB ASSIGNMENT 1

Design of High-Speed Op-Amps for Signal Processing

d. Can you find intrinsic gain more easily by examining the equation for current? Explain.

Homework 2 Solutions. Perform.op analysis, the small-signal parameters of M1 and M2 are shown below.

EE301 Electronics I , Fall

Design of a Sample and Hold Circuit using Rail to Rail Low Voltage Compact Operational Amplifier and bootstrap Switching

EE501 Lab 7 Opamp Measurement

Index. Small-Signal Models, 14 saturation current, 3, 5 Transistor Cutoff Frequency, 18 transconductance, 16, 22 transit time, 10

OPERATIONAL AMPLIFIERS

Low Quiescent Power CMOS Op-Amp in 0.5µm Technology

UNIT I - TRANSISTOR BIAS STABILITY

Operational Amplifier with Two-Stage Gain-Boost

Current Mirrors. Basic BJT Current Mirror. Current mirrors are basic building blocks of analog design. Figure shows the basic NPN current mirror.

DUAL CHANNEL LDO REGULATORS WITH ENABLE

INTEGRATED CIRCUITS. AN109 Microprocessor-compatible DACs Dec

ENGR 201 Homework, Fall 2018

EE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits

.dc Vcc Ib 0 50uA 5uA

Inverting input R 2. R 1 Output

Operational Amplifiers: Theory and Design

Field Effect Transistors

ISSN:

ECEN 474/704 Lab 8: Two-Stage Miller Operational Amplifier

Isolated Industrial Current Loop Using the IL300 Linear

Analysis and Design of Analog Integrated Circuits Lecture 20. Advanced Opamp Topologies (Part II)

1.2 V Precision Low Noise Shunt Voltage Reference ADR512

Design Of Two Stage CMOS Op-Amp With Low Power And High Slew Rate.

Lecture 4 ECEN 4517/5517

Electronics Prof. D. C. Dube Department of Physics Indian Institute of Technology, Delhi

CONVERTING 1524 SWITCHING POWER SUPPLY DESIGNS TO THE SG1524B

EE351 Laboratory Exercise 4 Field Effect Transistors

Solid State Devices & Circuits. 18. Advanced Techniques

CSE 577 Spring Insoo Kim, Kyusun Choi Mixed Signal CHIP Design Lab. Department of Computer Science & Engineering The Penn State University

Lecture 33: Context. Prof. J. S. Smith

Transcription:

EE 501 Lab9 Widlar Biasing Circuit and Bandgap Reference Circuit Due Nov. 19, 2015 Objective: 1. Understand the Widlar current source circuit. 2. Built a Self-biasing current source circuit. 3. Understand the bandgap reference circuit principle. 4. Investigate how to build bandgap reference circuit. Pre-lab: 1. Investigate how the specifications of your amplifier (designed in Lab5) vary with temperature and supply voltage. 2. Plot gm (input pair), GBW, phase margin and UGF vs. temperature (-25 о C to 85 о C). 3. Plot total current vs. temperature (-25 о C to 85 о C). 4. Plot all specs above vs. supply voltage (Vdd-Vss: from 2V to 6V) 5. Tabulate the variance (in percent) of all specifications mentioned above over temperature and supply voltage. 6. Try to explain why. Task A: Procedures From pre-lab section, you should notice that all the specs vary with temperature. Therefore, in order to make our amplifier PVT robust, we need to generate a biasing circuit to keep input gm constant with temperature. In EE501 lecture, we introduced the Widlar current source and design strategy. Here we design a Self-biased current source based on Widlar current source which could generate constant gm for us. 1. Design a self-biased Widlar current source circuit using design strategy mentioned in EE501 lecture (References.pptx page 33). And you can choose the desired biasing current as 10uA. The circuit is given by following. VCVS is used as a feedback opamp, as shown in References page 43 which improved sensitivity.

2. Using this biasing circuit to bias your amplifier you designed in Lab5. Redo pre-lab step2, 3, and 4. Biasing Circuit Amplifier By sizing your biasing circuit properly, achieve gm, GBW, PM and UGF constancy within 5% variation through temperature and supply voltage. One example for gm constancy is given by following.

3. Replace the VCVS with the amplifier you designed in Lab5, then repeat step2. (By replacing the VCVS, your amplifier also should be biased from this circuit, and the compensation capacitance may change, you could choose 200fF in this one). Cc in this amplifier is 200fF 4. Add start-up circuit as shown as following. (You may choose different type startup circuits as shown in lecture)

Start-up circuit Task B: In previous section, you may notice that although we could achieve gm, GBW and UGF constant within 5% over temperature, the current variation is much larger. How could we get a constant current or voltage reference through temperature? In the lecture, we introduced bandgap reference which could achieve constant Vref and Iref. 1. Build a bandgap circuit following Fig. 2. (VCVS is used as a feedback opamp by assuming an opamp has been properly designed for generating supply independent reference. In a real design, the stability of the feedback loop should be assured.) 2. Choose the value of R0 and N. The resistor s value is always in the range of kilo ohms. 3. Estimate R1 with equation R 1 ln(n) 24. 4. Tune R1 to achieve zero temperature coefficient (TC) at the required temperature (such as 27 C). 5. Then sweep VDD from 2 to 6 V and observe the independence with VDD. 6. Add the start-up circuit as shown in Fig. 5. 7. Replace the VSVS with designed opamp then repeat step 4. Report: 1. Show the simulation results in pre-lab section.

2. Briefly describe sizing steps for Self-biasing current source. 3. Show the complete schematic and simulation results of Task A. 4. Briefly explain sizing steps for Bandgap reference. 5. Show the complete schematic and simulation results of Task B. 6. Briefly state what you have learned. 7. Additional comments, problems and doubts.

Appendix: The bandgap reference voltage generator is designed to provide a stable reference voltage across the device operating temperature and voltage. The design uses a known BGR circuit, but replaces the PN junction diodes with MOSFET connection diodes. The proposed bandgap voltage reference consists three circuit blocks: an opamp (VCVS), a bandgap core, and a startup circuit. The bandgap reference circuit is used to generate a temperature independent voltage and is shown below. A key element in a bandgap circuit core is the diode. Unfortunately, AMI 0.5um technology does not have diode models in its library. In this work a PMOS diode connected elements have been used. The drain, gate, and source of the PMOS tied together to form the Anode and the body of the PMOS forms the Cathode. Figure 1 shows the PMOS diode used in proposed design. Figure 1 Generate a diode from a PMOS transistor. The PMOS diode has the characteristic below: 1. Exponential relationship of current to voltage across holds. 2. PMOS diode exhibits a negative temperature coefficient similar to regular diodes. 3. The number of parallel components N affects the cut-in voltage (knee voltage). The bandgap core provides the negative and positive temperature coefficients through the diode elements ( V be, V V T ). For a diode, I = I be V T T s(e T 1), where V be 2mV/C at T room temperature, and V T = kt q, V T T 0.085V/C.

Figure 2 Bandgap reference circuit Fig 2 presents the BGR circuit. The PMOS transistors P0-P2 are assumed to have the same current, I1+I2 (The channel length should be large and the transistors should operate in saturation region). The op-amp is so controlled that the voltages of V a and V b are equalized V a = V b = V be1 The current follow through resistor R5 and R6 with resistance of R1 is given by I 1 = V be1 R 1 The current flow through the diodes and the resistor R0 is given by V be1 V be2 I 2 = I s0 e V T = N I s0 e V T = V be1 V be2 I 2 = V T ln(n) Therefore, the output voltage of the proposed BGR, V ref becomes V ref = R 3 ( V be1 R 1 Assuming R3 is temperature independent, + V Tln (N) )

V ref T = V be1 1 + V T ln(n) T R 1 T To obtain temperature independent reference voltage, R0, R1, and N should meet the following relationship R 1 ln(n) 2 0.085 24 A sample V ref vs. Temperature plot is given as below. The V ref is around 1.177 V at room temperature. (Vdd=5V, Vss=gnd) Figure 3 V ref vs. Temperature The temperature coefficient (TC) was calculated using equation TC = 1 V ref ( V ref T ) = 1 V ref ( V refmax V refmin T max T min ) 10 6 = 1 10 3 (1.138 1.177 85 ( 25) ) 106 8.79 ppm/ Then sweep VDD from 2 to 6 V and observe the independence with VDD.

Figure 4 V ref vs. VDD In simulation, you circuit may be able to start up. However, it doesn t guarantee that your circuit can start up after fabrication. So you should consider startup as a potential problem during the preliminary design phase. Build startup circuit as below or you can use other startup structure. Figure 5 Bandgap reference circuit with startup circuit