INFORMATION & OMMUNIATIONS Development of Low-Power-onsumption I hipset for SFP+ Keiji TANAKA*, Akihiro MOTO, Hayato FUJITA, Shunsuke SATO, Hiroyasu OOMORI, Hiromi TANAKA, Hiroto ISHIBASHI and Katsumi UESAKA For small form-factor pluggable plus (SFP+), the authors have successfully developed chipset composed of transceiver I equipped with Vertical-avity Surface-Emitting Laser (VSEL) driver and shunt-driver I. This paper describes the concept of low-power consumption designs and details of circuit designs. This combination of the shunt-driver and VSEL driver with an asymmetric pre-emphasis has enabled to reduce the total power consumption of SFP+ without any degradation of optical performance. Both the transceiver I and the shunt-driver I can operate at 2.5V supply voltage. onsequently, the development of such I has effectively reduced the total power consumption of SFP+ for 1GBASE-LR to 75 mw or less at operating temperature ranging from Tc = -5 to 85, in accordance with the requirements of SFF-8472. Keywords: shunt driving, VSEL driver, SiGe-BiMOS process, SFP+, IEEE82.3ae 1. Introduction As one of the world s leading companies in optical transceiver business, Sumitomo Electric Industries had developed various types of optical transceiver (1), which were widely used in optical communication networks. We had developed LD (Laser Diode) and PD (Photo Diode) as key devices for optical communication. In addition, optical communication Is such as LDD (Laser Diode Driver), TIA (Trans-Impedance Amplifier) and LA (Limiting Amplifier) were used in their optical transceivers such as SFF (Small Form Factor) and SFP (Small Form factor Pluggable). In particular, SFP is well-known as one of optical transceivers suitable for hot pluggable operation. These optical transceivers are mainly composed of an optical transmitter, a receiver and a controller. In the transmitter, the LD is directly modulated by the output current of the LDD. Then optical signal is transmitted into optical fiber. For the receiver, the PD detects the optical signal and converts it into a PD current. Then the PD current is amplified by the TIA and transformed into a voltage signal. The LA amplifies the output voltage signal from the TIA and limits the signal amplitude. In addition, recent optical transceiver such as SFP has a DDM (Digital Diagnostic Monitoring) function which can monitor and manage the statuses of the transceiver. For example, LD bias current, module temperature, power supply voltage and so on. In order to achieve these functions in the small package, the authors had developed a transceiver I which was composed of an LDD, an LIA and a DDM function, and a multi-rate TIA up to 4.25 Gbit/s operation (2), (3). As the demand on data communication increased, 1 Gbit/s optical transceivers such as Transponder, XEN- PAK, X2 and XFP were developed. However, since these transceivers had high power consumption and large outline, the port numbers per a blade enclosure was limited. Therefore, SFP+ had been proposed by MSA (Multi Source Agreement) (4) so as to solve these issues. This paper describes the design of I chipset for SFP+ which is necessary to provide a low power solution. The chipset is composed of the shunt-driver I and the transceiver I in which VSEL driver, LA, LB (Linear Buffer) and DDM are integrated. For 1GBASE-LR application, these two chips are integrated in SFP+ (5), and lowpower consumption up to 75mW from -5 to 85 as module case temperature can be achieved. 2. Development of I chipset for SFP+ Photo 1 shows the internal view of a newly developed SFP+ in which the transceiver I and the shunt driver I are mounted. Figure 1 shows the block diagram of the SFP+. The main components of the SFP+ are (A) a printed circuit () TOSA (B) ROSA Shunt Driver I Transceiver-I (A) PB Photo 1. Internal view of a newly developed SFP+ 86 Development of Low-Power-onsumption I hipset for SFP+
SFP+ Optical I/F shunt- Driver TOSA with shunt-driver I PD 5Ω TIA ROSA 5Ω Transceiver I DDM D/A LDD AP A/D Monitor ontroller LB Block SFP+ Electrical I/F Rate Select I2 Interface TxDisable board including transceiver I and a PU, (B) a ROSA (Receiver Optical Sub Assembly) and () a TOSA (Transmitter Optical Sub Assembly) in which the shunt-driver I is mounted. The printed circuit board can be used for all applications covered by MSA. 2-1 Design concept of I chipset For conventional optical transceivers such as XFP or X2, the anode and cathode terminals of the edge-emitting laser diode are connected to LDD differential outputs through two coupling capacitors as shown in Fig. 2. In this differential driving, back termination resistance is matched with transmission line impedance. Although the low resistance (~5Ω) of the LD causes reflection from the LD, it can be entirely absorbed by the back termination resistance. As a consequence, multiple reflections between the LD and the LDD can be avoided. Additionally, the back termination resistance brings wider bandwidth with resistive loss. Using this driving technology, good eyeopening can be easily obtained but the resistive loss causes the increase in power consumption. Positive Negative 5Ω LA PU w/rom Fig. 1. Block diagram of a newly developed SFP+ V IMOD 5Ω Zo=5Ω Zo=5Ω I BIAS L L Rs LD Rs TD+ RD+ I LD = I BIAS ± αi MOD2 2RL=2Rs+Rd Rd Vf<1.6V α = 5/(5+RL) Fig. 2. Simplified circuit schematic for differential driving Since SFP+ has good mechanical compatibility with SFP, it is considered that 48 modules can be pluged into one blade. The maximum power consumption of 1W as level-1 category is defined by MSA. Although a DR (lock and Data Recovery) unit is removed so as to reduce the power consumption, reducing it to 1W or less is problematic as long as the differential driving is used. Figure 3 shows the comparison graph of power budget for each transceiver such as X2, XFP, SFP+ using differential driving and SFP+ using shunt-driving. For differential driving, the total power consumption of SFP+ is greater than 1W at Tc=85. In order to reduce total power consumption to 1W or less, it is necessary to reduce the power consumption of the transmitter side to 75 mw or less. Therefore, the low power solution of SFP+ has been developed, using the following technology brought by the development of I chipset. (1) Shunt-driver I under 2.5V power supply (2) VSEL driver I under 2.5V power supply (3) D/D convertor having high efficiency Power consumption [W] 4.5 4 3.5 3 2.5 2 1.5 1.5 Maximum Spec. defined MSA SERDES DR ROSA LDD TOSA RD- TD- X2 XFP SFP+ SFP+ Diffrentaldriving shuntdriving Fig. 3. omparison graph of power budget for each transceiver 2-2 Shunt-driver I Shunt-driver I, which can drive LD directly under low supply voltage, has been widely used in low speed optical communication up to 1 Mbit/s using LED (Light Emitting Diode). However, recent progress of semiconductor process technologies has changed this situation. Therefore, the shunt-driver I to drive the LD at 1 Gbit/s has been able to be developed, using the process technologies of high speed LD and I. The shunt-driver I is composed of single transistor in parallel with the LD and can output modulated current to the LD. Then the LD biasing current can be subtracted from the modulated current. Eventually, the LD current can be modulated and converted to the optical signal. Figure 4 shows the simplified circuit schematic of the optical transmitter using shunt-driving, which is composed of VSEL driver and the shunt-driver I. In order to enable 1 Gbit/s operations, the shunt-driver I is mounted in TOSA and driven from the VSEL driver I through a 5Ω transmission line. SEI TEHNIAL REVIEW NUMBER 69 OTOBER 29 87
Since the switching transistor M1 in parallel with the LD requires high linearity, high input impedance and high speed operation, N-channel MOS-FET (Metal Oxide Semiconductor Field Effect Transistor) with.18µm gate length is suitable for 1 Gbit/s operations. The gate width of M1 is decided by taking the tradeoff between speed and trans-conductance gain into account. A 5Ω termination resistor R1 is integrated in shunt-driver I and matched with the 5Ω transmission line. The gate voltage for M1 is supplied from outside of the shunt-driver I through a bias-t composed of L2 and 3. In order to avoid idle current due to gate voltage, the 5Ω termination is composed of R1 and 1 as A termination. R2 is a weak pull-down resistor to prevent floating. A ferrite bead inductor L1 to prevent the leakage of high speed current is connected to the LD anode and the drain of M1. The shunt-driver I is tied with LD chip and TOSA package using bonding wires. As for TOSA package design, the wire length of each pin and the position of each part are optimized by electromagnetic field analysis (6). As a consequence, the shunt-driving for 1 Gbit/s operations has been successfully developed. Ta=-1 Ta=25 Ta=9 Pulse Mask Margin=29% 44µm Pulse Mask Margin=47% 63µm Pulse Mask Margin=29% Fig.6. Optical eye-diagrams when shunt-driving TOSA is directly driven by a pulse pattern generator VSEL driver I TDINP TDINN IMOD<25mA E/O Response (db) 1 V V -1-2 -3 L3 L4 R3 2 3 Gate Biasing L2 shunt-driving I M1 R1 R2 1 V>2.5V I BIAS IFET LD Vcs>.5V L1 ILD=I BIAS I FET Vf<2V shunt-driving TOSA Fig. 4. Simplified circuit schematic of the optical transmitter using shuntdriving -4 5 1 15 2 frequency (GHz) Fig. 5. E/O response of shunt-driving TOSA using in-house edge-emitting LD Photo 2. hip photography of shunt-driver I Figure 5 shows E/O response of shunt-driving TOSA using in-house edge-emitting LD. The bandwidth of around 1GHz is enough for 1 Gbit/s operations. Figure 6 shows the optical eye-diagram when shunt-driving TOSA is directly driven by a pulse pattern generator. Suitable mask margins of more than 2% can be achieved from -1 to 9 of ambient temperature. Shunt-driving can reduce output current from VSEL driver because M1 has trans-conductance gain gm. The output current of VSEL driver is 2 IFET/(gm R1), where IFET is LD modulation current, and the output impedance of VSEL driver is perfectly matched with R1. In other words, the output current of VSEL driver is multiplied by (gm R1)/2. Generally, the total power consumption except for the output current tends to be higher for LDD with large drivability for edge-emitting LD, while it becomes lower for VSEL driver with small drivability. In addition, the shunt-driving can operate under low supply voltage because it doesn t require series resistors to improve matching between driver output and LD chip. If the forward voltage of LD is less than 2.V, 2.5V supply operation can be achieved if the current source for LD biasing can be used within.5v. As a consequence, low power operation can be achieved. Photo 2 shows the chip photography of shunt-driver I. The size of the shunt-driver I is 44 x 63 µm, which was fabricated by a.18µm MOS process with 4 metal layers. 2-3 Development of transceiver I Newly developed 1Gbit/s transceiver I is composed of VSEL driver, LA (Limiting Amplifier) to amplify the output signal from TIA, and LB (Linear Buffer) 88 Development of Low-Power-onsumption I hipset for SFP+
to buffer the output signal from linear TIA. These high speed blocks occupy most of the power consumption of the transceiver I. In order to achieve low power consumption, these high speed blocks have been designed even with a power supply under 2.5V. The DDM block in the transceiver I can monitor transceiver statuses and alarm flag of SFP+. The analog block such as the LDD, the LA and the LB is controlled and optimized by programming internal registers. The DDM block consists of an A/D convertor and digital circuits managed by hardware state-machine. These digital circuits can operate with a 1.8V supply which is generated inside of the transceiver I. Therefore, digital circuit size and power consumption can be efficiently reduced. Photo 3 shows the chip photography of the transceiver I. It is fabricated by.18µm SiGe-BiMOS process (ft=8ghz, BVE=3.6V). This chip (2.34 2.34 mm) is mounted in 4 pin QFN package of external dimensions 5 5 mm 2. VSEL driver DDM (AP, Monitor) Digital ircuit LA/LB (1)Development of low voltage VSEL driver Figure 7 shows the block diagram of VSEL driver in the transceiver I. The VSEL driver is composed of an input termination circuit, an input buffer stage, a duty control stage, a pre-driver stage and a main-driver stage. The differential input signals from a host board are terminated by the input termination circuit, and then the input buffer amplifies these terminated signals. The dutycontrol stage can move the crossing point of the optical output by adjusting a duty control current source. Low output impedance to drive the main-driver stage can be provided by the pre-driver stage. The main-driver stage composed of ML (urrent-mode Logic) circuit can drive either the VSEL or the shunt-driver I in the TOSA. The output impedance of the main-driver stage is 5Ω. Pull-up inductors L3 and L4, which are connected to 2.5V supply, are needed so as to maintain voltage headroom at the output of the main-driver stage. For the direct modulation of LD, since LD has intrinsic relaxation oscillation, the rise time of the optical signal tends to be faster than the fall time of that even if the modulation current has same rise and fall time. Therefore, it is substantially easier to create asymmetric eye-diagrams for 1Gbit/s. An asymmetrical pre-emphasis has been developed so that asymmetrical optical waveforms can be compensated for. Generally, when a LD modulation current is directly emphasized by the pre-emphasis, the pre-emphasis consumes a lot of current because its output current is proportional to the LD modulation current. However, the combined LD driving with the shunt-driving and the VSEL driver with asymmetric pre-emphasis can reduce total power consumption of SFP+ module without any degradation of optical performance. Because the shuntdriver with linear gain can amplify the emphasized input signal by VSEL driver without any current consumption. Figure 8 shows the electrical eye-diagram of VSEL driver output. Figure 8 (a) and 8 (b) show the optical eyediagrams with and without pre-emphasis, respectively. The rise/fall time without pre-emphasis is 27/22 psec, while it is 24/26 psec with pre-emphasis. (2)Development of receiver As the application required for SFP+, a developed receiver is necessary not only for 1GBASE-LR/SR but also for 1GBSE-LRM. For 1GBASE-LRM, the output signal from the receiver must operate in linear region so that ED (Electric Dispersion ompensation) in the host board can compensate for the distorted signal, which is caused by the fiber dispersion that MMF (Multi-Mode Fiber) has. Although linear TIA is necessary for 1GBASE- LRM, the transceiver I can be used for either 1GBASE- LR or -LRM, because both LA and LB are integrated in the transceiver I and either LA or LB can be selected by programming an internal register. Photo 3. hip photography of transceiver I INP 1Ω INN Input buffer Input temination Duty Pre-driver Main-driver 5Ω 5Ω Duty current source I MOD Sub-driver K-I MOD 2.5V 2.5V OUTP OUTN Fig. 7. Block diagram of VSEL driver in transceiver I (a) w/o pre-emphasis Fig. 8. Electrical eye-diagrams of VSEL driver output L3 L4 2 TO TOSA 3 (b) w/ pre-emphasis SEI TEHNIAL REVIEW NUMBER 69 OTOBER 29 89
LA consists of two-stage high gain blocks, a ML output buffer, an AO (Auto Offset ontroller), and a LOS (Loss Of Signal) to detect whether the signal exists or not. Figure 9 shows the frequency dependency of the gain for both LA and LB. The bandwidth of LA is more than 1 GHz with 36 db gain. The low cut off frequency of 1 khz or less is decided so as to pass the stressed eye testing. The large time constant for AO is generated by internal MIM (Metal-Insulator-Metal) capacitors. The bandwidth of LB is around 14 GHz with 2. db gain. The peaking around 1 GHz is intentionally designed to compensate dielectric and resistive losses of printed circuit boards. The output resistance of ML buffer is shared with both LA and LB. Therefore, the linearity of the ML buffer is controlled by changing the trans-conductance stage for each mode. Tc = -5deg PMM = 23% Fig. 11. Temperature dependency of optical eye-diagrams from Tc = - 5 to 85. 1-3 Ta = 25deg PMM = 39% w/o x-talk w/ x-talk Tc = 85deg PMM = 29% 1-4 SDD21 (db) 4 3 2 1 LA LB BIT ERROR RATIO 1-5 1-6 1-7 1-8 1-9 1-1 1-12 1-14 -23-21 -21-2 -19-18 -17-16 -15-1 5 1 15 2 freq (GHz) OMA (dbm) Fig. 12. Bit error ratio with and without cross-talk noise Fig. 9. Frequency dependency of the gain for LA and LB 1 3. Evaluation Results SFP+ using a newly developed chipset has been developed and evaluated for 1GBASE-LR. Figure 1 shows optical output waveforms for 1GBASE-LR. Figure 1 (a) and Power Dissipation (mw) 9 8 7 6 5 4 3 2 1GBASE-LR 1GBASE-SR 1 w/o B-T filter w/ B-T filter (a) w/o pre-emphasis (b) w/ pre-emphasis Fig. 1. Optical eye-diagrams for 1GBASE-LR -25 25 5 75 1 Temperature () Fig. 13. Temperature dependency of power dissipation for 1GBASE-LR and -SR cases. Figure 1 (b) show the optical waveform with and without pre-emphasis, respectively. The asymmetrical pre-emphasis can effectively compensate asymmetrical optical waveforms. Figure 11 shows the temperature dependency of optical output waveforms from Tc= - 5 to 85. Figure 12 shows bit error ratio with and without cross-talk noise. The penalty due to the cross talk noise is around.5 db. The shunt-driving 9 Development of Low-Power-onsumption I hipset for SFP+
can reduce cross-talk noise so that the switching noise by LD modulation can be shielded by TOSA with a metal shield. The transceiver I can be also used for 1GBASE-SR application. Figure 13 shows the temperature dependency of power consumption for both 1GBASE-LR and -SR. The power consumption for LR and SR at Tc=85 is 7 mw and 55 mw, respectively. These can satisfy type-i requirement of MSA, which is 1W or less. Figure 14 shows the temperature dependency of optical output waveforms for 1GBASE-SR. Tc = -5deg PMM = 21% Ta = -25deg PMM = 21% 4. onclusion Tc = -85deg PMM = 2% Fig. 14. Temperature dependency of optical eye-diagrams for 1GBASE-SR. We have developed the chipset for SFP+, which is intended for 1GBASE-SR/LR/LRM applications, and confirmed excellent performance. In particular, as the strongest feature of the chipset, excellent low power design can greatly contribute to the power reduction of IT equipment. References (1) M. Nishie, Research and Development of Optical Data Link Modules, SEI Technical Review, No.173, p1-14, July, 28. (2) K. Tanaka, et al, Development of Multi-rate Small Form Factor Pluggable Optical Transceiver, SEI Technical Review, No.172, p133-139, January, 28. (3) Tanaka. K, et al, SDH/SONET Multi-rate SFP Module with Gain Selectable Trans-impedance Amplifier and Extinction Ratio ontrol ircuit, 27 Electric omponents and Technology onference. (4) SFF ommittee, SFF-8431 Specifications for Enhanced 8.5G and 1 Gigabit Small Form Factor Pluggable Module SFP+, Rev 2.2, December, 27. (5) A. Moto, et al A low power consumption DFB-LD driver I for a 1Gb/s optical communication, IEIE General onference, -12-36, March, 29. (6) S. Sato, et al Shunt-drive type TOSA with low power consumption for SFP+, IEIE General onference, -3-14, March, 29. ontributors (The lead author is indicated by an asterisk (*)). K. TANAKA* Manager, Advanced ircuit Design R&D Department, Transmission Devices R&D Laboratories He is engaged in the research and the development of high speed Is for optical communication and optical sub-assemblies. A. MOTO Advanced ircuit Design R&D Department, H. FUJITA Advanced ircuit Design R&D Department, S. SATO Packaging Technologies R&D Department, H. OOMORI Assistant Manager, Packaging Technologies R&D Department, Transmission Devices R&D Laboratories H. TANAKA Manager, Lightwave Development Department, Optical omponents Division, Sumitomo Electric Device Innovation, Inc. H. ISHIBASHI Manager of Firmware & Digital ontrol Design Group, Lightwave Development Department, Optical omponents Division, Sumitomo Electric Device Innovation, Inc. K. UESAKA Manager, Integrated Device Process R&D Department, SEI TEHNIAL REVIEW NUMBER 69 OTOBER 29 91