2.5V/3.3V Differential :4 Clock/Data Fanout Buffer/ Translator with CML Outputs and Internal Termination Description The NB7L4M is a differential to 4 clock/data distribution chip with internal source terminated CML output structures, optimized for minimal skew and jitter. Device produces four identical output copies of clock or data operating up to 8 GHz or 2 Gb/s, respectively. As such, NB7L4M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications. Inputs incorporate internal termination resistors and accept LVPECL, CML, LVCMOS, LVTTL, or LVDS (See Table 6). Differential 6 ma CML outputs provide matching internal terminations, and 400 mv output swings when externally terminated with to (See Figure 4). The device is offered in a low profile 3x3 mm 6 pin FN package. Application notes, models, and support documentation are available at www.onsemi.com. Features Maximum Input Clock Frequency up to 8 GHz Typical Maximum Input Data Rate up to 2 Gb/s Typical < ps of RMS Clock Jitter < ps of Data Dependent Jitter 30 ps Typical Rise and Fall Times ps Typical Propagation Delay 6 ps Typical Within Device Skew Operating Range: = 2.375 V to 3.465 V with = 0 V CML Output Level (400 mv Peak to Peak Output) Differential Output Only Internal Input and Output Termination Resistors Functionally Compatible with Existing 2.5 V/3.3 V LVEL, LVEP, EP and SG Devices These are Pb Free Devices V T 0 0 FN 6 MN SUFFIX CASE 485G A L Y W MARKING DIAGRAM* *For additional marking information, refer to Application Note AND8002/D. 6 NB7L 4M ALYW = Assembly Location = Wafer Lot = Year = Work Week = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. 2 V T Figure. Logic Diagram 2 3 3 Semiconductor Components Industries, LLC, 202 June, 202 Rev. 6 Publication Order Number: NB7L4M/D
0 0 6 5 4 3 Exposed Pad (EP) V T 2 2 3 NB7L4M 2 V T 4 9 2 5 6 7 8 3 3 Figure 2. FN 6 Pinout (Top View) Table. PIN DESCRIPTION Pin Name I/O Description V T Internal Termination Pin for. 2 LVPECL, CML, LVCMOS, LVTTL, LVDS 3 LVPECL, CML, LVCMOS, LVTTL, LVDS Inverted Differential Clock/Data Input. (Note ) Non inverted Differential Clock/Data Input. (Note ) 4 V T Internal Termination Pin for. 5,6 Power Supply Negative Supply Voltage. All pins must be externally connected to a Power Supply to guarantee proper operation. 6 3 CML Output Inverted Differential Output 3 with Internal Source Termination Resistor. (Note 2) 7 3 CML Output Non inverted Differential Output 3 with Internal Source Termination Resistor. (Note 2) 8,3 Power Supply Positive Supply Voltage. All pins must be externally connected to a Power Supply to guarantee proper operation. 9 2 CML Output Inverted Differential Output 2 with Internal Source Termination Resistor. (Note 2) 2 CML Output Non inverted Differential Output 2 with Internal Source Termination Resistor. (Note 2) CML Output Inverted Differential Output with Internal Source Termination Resistor. (Note 2) 2 CML Output Non inverted Differential Output with Internal Source Termination Resistor. (Note 2) 4 0 CML Output Inverted Differential Output 0 with Internal Source Termination Resistor. (Note 2) 5 0 CML Output Non inverted Differential Output 0 with Internal Source Termination Resistor. (Note 2) EP Exposed Pad. Thermal pad on the package bottom must be attached to a heatsinking conduit to improve heat transfer. It is recommended to connect the EP to the lower potential ( ).. In the differential configuration when the input termination pins (V T, V T ) are connected to a common termination voltage or left open, and if no signal is applied on and, then the device will be susceptible to self oscillation. 2. CML outputs require receiver termination resistors to for proper operation. 2
Table 2. ATTRIBUTES ESD Protection Characteristics Human Body Model Machine Model Charged Device Model Value > 500 V > 50 V > 500 V Moisture Sensitivity (Note 3) Pb Pkg Pb Free Pkg FN 6 Level Level Flammability Rating Oxygen Index: 28 to 34 UL 94 V 0 @ 0.25 in Transistor Count 387 Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 3. For additional information, see Application Note AND8003/D. Table 3. MAXIMUM RATINGS Symbol Parameter Condition Condition 2 Rating Units Positive Power Supply = 0 V 3.6 V V I Input Voltage = 0 V V I 3.6 V V INPP Differential Input Voltage 2.8 V < 2.8 V I IN Input Current Through R T ( Resistor) Static Surge I out Output Current Continuous Surge 2.8 T A Operating Temperature Range FN 6 40 to +85 C T stg Storage Temperature Range 65 to +50 C JA Thermal Resistance (Junction to Ambient) (Note 4) 0 lfpm 500 lfpm FN 6 FN 6 JC Thermal Resistance (Junction to Case) 2S2P (Note 4) FN 6 3 to 4 C/W T sol Wave Solder Pb Pb Free Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 4. JEDEC standard multilayer board 2S2P (2 signal, 2 power). 45 80 25 50 42 36 265 265 V V ma ma ma ma C/W C/W C 3
Table 4. DC CHARACTERISTICS, CLOCK Inputs, CML Outputs ( = 2.375 V to 3.465 V, = 0 V, T A = 40 C to +85 C) (Note 5) Symbol Characteristic Min Typ Max Unit I CC Power Supply Current (Inputs and Outputs Open) 40 90 ma V OH Output HIGH Voltage (Note 6) 60 20 mv V OL Output LOW Voltage (Note 6) 530 420 360 mv Differential Input Driven Single Ended (see Figures & 2) (Note 8) V th Input Threshold Reference Voltage Range (Note 7) 800 75 mv V IH Single ended Input HIGH Voltage 200 mv V IL Single ended Input LOW Voltage 50 mv V ISE Single Ended Input Voltage (V IH V IL ) 50 2500 mv Differential Inputs Driven Differentially (see Figures & 3) (Note 9) V IH Differential Input HIGH Voltage 200 mv V IL Differential Input LOW Voltage 75 mv V CMR Input Common Mode Range (Differential Configuration) (Note ) 800 38 mv V ID Differential Input Voltage (V IH V IL ) 75 2500 mv I IH Input HIGH Current / (V T /V T Open) 0 25 0 A I IL Input LOW Current / (V T /V T Open) 0 A R TIN Internal Input Termination Resistor 45 50 55 R TOUT Internal Output Termination Resistor 45 50 55 R Temp Coef Internal I/O Termination Resistor Temperature Coefficient 6.38 m / C NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. Input and output parameters vary : with. 6. CML outputs require receiver termination resistors to for proper operation. 7. V th is applied to the complementary input when operating in single ended mode. V th = (V IH V IL )/2. 8. Vth, V IH, V IL,, and V ISE parameters must be complied with simultaneously. 9. V IHD, V ILD, V ID and V CMR parameters must be complied with simultaneously..v CMR min varies : with, V CMR max varies : with. The V CMR range is referenced to the most positive side of the differential input signal. 4
Table 5. AC CHARACTERISTICS ( = 2.375 V to 3.465 V, = 0 V; Note ) Symbol V OUTPP Characteristic Output Voltage Amplitude (@V INPPmin )f in 6 GHz (See Figure 4) f in 8 GHz 40 C 25 C 85 C Min Typ Max Min Typ Max Min Typ Max 280 25 f data Maximum Operating Data Rate 2 2 2 Gb/s t PLH, Propagation Delay to Output Differential 70 50 70 50 70 50 ps t PHL 400 300 280 25 400 300 280 25 400 300 Unit mv t SKEW Duty Cycle Skew (Note 2) Within Device Skew Device to Device Skew (Note 3) 20 5 50 20 5 50 20 5 50 ps t JITTER RMS Random Clock Jitter (Note 4) f in = 6 GHz f in = 8 GHz Peak/Peak Data Dependent Jitter f in = 2.488 Gb/s (Note 5) f data = 5 Gb/s f data = Gb/s V INPP Input Voltage Swing/Sensitivity (Differential Configuration) (Note 6) t r Output Rise/Fall Times @ GHz, t f (20% 80%) 8.0 8.0 8.0 75 400 2500 75 400 2500 75 400 2500 mv 30 60 30 60 30 60 ps ps NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.. Measured by forcing V INPP (TYP) from a 50% duty cycle clock source. All loading with an external R L = to. Input edge rates 40 ps (20% 80%). 2.Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw and Tpw+ @ GHz. 3. Device to device skew is measured between outputs under identical transition @ GHz. 4.Additive RMS jitter with 50% duty cycle clock signal at GHz. 5.Additive peak to peak data dependent jitter with input NR data at PRBS 2^23. 6.V INPP (MAX) cannot exceed. Input voltage swing is a single ended measurement operating in differential mode. OUTPUT VOLTAGE AMPLITUDE (mv) 450 400 350 300 250 200 50 0 50 = 3.3 V = 2.5 V 0 2 3 4 5 6 7 8 9 2 INPUT FREUENCY (GHz) Figure 3. Output Voltage Amplitude (V OUTPP ) versus Input Clock Frequency (f in ) at Ambient Temperature (Typical) (V INPP = 400 mv) 5
Voltage (50 mv/div) DDJ =.6 ps* Voltage (50 mv/div) DDJ = 2.8 ps** Time (80 ps/div) Time (40 ps/div) Figure 4. Typical Output Waveform at 2.488 Gb/s with PRBS 2^23 (V inpp = 75 mv) Figure 5. Typical Output Waveform at 5 Gb/s with PRBS 2^23 (V inpp = 75 mv) *Input signal DDJ = 6.4 ps **Input signal DDJ = 7.2 ps Voltage (50 mv/div) DDJ = 2 ps*** Voltage (50 mv/div) DDJ = 6 ps*** Time (8 ps/div) Time (8.2 ps/div) Figure 6. Typical Output Waveform at.7 Gb/s with PRBS 2^23 (V inpp = 75 mv) Figure 7. Typical Output Waveform at 2 Gb/s with PRBS 2^23 (V inpp = 75 mv) ***Input signal DDJ = ps ***Input signal DDJ = 3 ps 6
V INPP = V IH () V IL () V OUTPP = V OH () V OL () t PHL t PLH Figure 8. AC Reference Measurement NB7L4M Receiver Device = = Figure 9. Typical Termination for 6 ma Output Driver and Device Evaluation (Refer to Application Notes AND8020/D and AND873/D) V th V th Figure. Differential Input Driven Single Ended Figure. Differential Inputs Driven Differentially Vthmax V th V IHmax V ILmax V IH V th V IL V CMmax V CMR V IHmax V ILmax V () = V IH V IL V IHtyp V ILtyp V thmin GND V IHmin V ILmin V CMmax GND V IHmin V ILmin Figure 2. V th Diagram Figure 3. V CMR Diagram 7
6 ma Figure 4. CML Output Structure Table 6. INTERFACING OPTIONS INTERFACING OPTIONS CML LVDS AC COUPLED RSECL, LVPECL LVTTL, LVCMOS CONNECTIONS Connect V T and V T to Connect V T, V T Together for Input Bias V T, V T Inputs within (VCMR) Common Mode Range Standard ECL Termination Techniques. See AND8020/D. An external voltage should be applied to the unused complementary differential input. Nominal voltage is.5 V for LVTTL and /2 for LVCMOS inputs. 8
Application Information All NB7L4M inputs can accept PECL, CML, LVTTL, LVCMOS and LVDS signal levels. The limitations for differential input signal (LVDS, PECL, or CML) are minimum input swing of 75 mv and the maximum input swing of 2500 mv. Within these conditions, the input voltage can range from to.2 V. Examples interfaces are illustrated below in a environment ( = ). CML Driver V T NB7L4M V T Figure 5. CML to CML Interface Recommended R T Values R T PECL Driver V Bias V Bias V T V T NB7L4M V 290 R T R T 3.3 V 2.5 V 80 Figure 6. PECL to CML Receiver Interface 9
LVDS Driver V T NB7L4M V T Figure 7. LVDS to CML Receiver Interface LVTTL/ LVCMOS Driver No Connect* No Connect V REF *or 60 pf to GND V T V T Figure 8. LVCMOS/LVTTL to CML Receiver Interface NB7L4M Recommended V REF Values LVCMOS LVTTL V REF 2.5 V ORDERING INFORMATION Device Package Shipping NB7L4MMNG FN 6 (Pb Free) 23 Units/Rail NB7L4MMNR2G FN 6 (Pb Free) 3000 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D.
PACKAGE DIMENSIONS FN6 3x3, P CASE 485G ISSUE F 2X PIN LOCATION 2X NOTE 4 0. C 0.05 C 0.05 C 0. C DETAIL A 6X L D ÇÇÇ ÇÇÇ TOP VIEW DETAIL B SIDE VIEW D2 8 (A3) A B E A A C 0. C A B L EXPOSED Cu SEATING PLANE L DETAIL A ALTERNATE TERMINAL CONSTRUCTIONS ÉÉÉ MOLD CMPD A DETAIL B ALTERNATE CONSTRUCTIONS PACKAGE OUTLINE L ÉÉ A3 NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, 994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 5 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS DIM MIN NOM MAX A 0.80 0.90.00 A 0.00 0.03 0.05 A3 0 REF b 0.8 4 0.30 D 3.00 BSC D2.65.75.85 E 3.00 BSC E2.65.75.85 e 0 BSC K 0.8 TYP L 0.30 0.40 0 L 0.00 0.08 RECOMMENDED SOLDERING FOOTPRINT* 6X 8 4 9 6X K 6 e e/2 BOTTOM VIEW E2 6X b 0. C 0.05 C A B NOTE 3 6X 0.30 2X 2X.84 3.30 0 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: 303 675 275 or 800 344 3860 Toll Free USA/Canada Fax: 303 675 276 or 800 344 3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800 282 9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 42 33 790 29 Japan Customer Focus Center Phone: 8 3 587 50 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative NB7L4M/D