9-9; Rev ; /99 68HC/Bidirectional-Compatible General Description The low-power CMOS microprocessor (µp) supervisory circuit is designed to monitor power supplies in µp and digital systems. The s output is bidirectional, allowing it to be directly connected to µps with bidirectional reset inputs, such as the 68HC. It provides excellent circuit reliability and low cost by eliminating external components and adjustments. The also provides a debounced manual reset input. This device performs a single function: it asserts a reset signal whenever the supply voltage falls below a preset threshold or whenever manual reset is asserted. Reset remains asserted for an internally programmed interval (reset timeout period) after has risen above the reset threshold or manual reset is deasserted. The comes with factory-trimmed reset threshold voltages in m increments from 2.5 to 5. Preset timeout periods of ms, 2ms, 4ms, and 2ms (minimum) are also available. The device comes in a SOT43 package. For a µp supervisor with an open-drain reset pin, see the MAX635 data sheet. Applications TOP IEW Computers Controllers Intelligent Instruments Critical µp and µc Power Monitoring Portable/Battery-Powered Equipment * Patents Pending 2 Pin Configuration SOT43 4 3 Features Small SOT43 Package Output Simplifies Interface to Bidirectional Reset I/Os Precision Factory-Set Reset Thresholds: m Increments from 2.5 to 5 ±.8% Reset Threshold Accuracy at T A = +25 C ±2.5% Reset Threshold Accuracy Over Temp. Four Reset Timeout Periods Available: ms, 2ms, 4ms, or 2ms (minimum) Immune to Short Transients 5µA Supply Current Pin-Compatible with MAX8 Ordering and Marking Information appears at end of data sheet. Typical Operating Circuit CIRCUITRY LASER- TRIMMED RESISTORS 4.7k 68HC** µp **OR OTHER µc/µp WITH BIDIRECTIONAL I/O PIN. * Maxim Integrated Products For free samples & the latest literature: http://www.maxim-ic.com, or phone -8-998-88. For small orders, phone -8-835-8769.
ABSOLUTE MAXIMUM RATINGS...-.3 to +6. All Other Pins...-.3 to ( +.3) Input Current ( )...2mA Output Current ()...2mA Rate of Rise ( ).../µs Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Continuous Power Dissipation (T A = +7 C) SOT43 (derate 4mW/ C above +7 C)...32mW Operating Temperature Range...-4 C to +85 C Storage Temperature Range...-65 C to +6 C Lead Temperature (soldering, sec)...+3 C ( = +2.5 to +5.5, T A = -4 C to +85 C, unless otherwise noted. Typical values are at T A = +25 C.) Operating oltage Range Supply Current Reset Threshold (Note ) Input Threshold Minimum Input Pulse Glitch Rejection to Reset Delay PARAMETER Reset Threshold Tempco to Reset Delay Reset Timeout Period MANUAL INPUT Pull-Up Resistance Output oltage INTERNAL PULL-UP Transition Flip-Flop Setup Time (Note 2) Active Pull-Up Enable Threshold Active Pull-Up Current Pull-Up Resistance Output Rise Time (Note 3) SYMBOL I CC TH TH / C t RP IL IH IL IH OL t S t R T A = C to +7 C = 5.5, no load = 3.6, no load T A = +25 C T A = -4 C to +85 C = falling at m/µs US D-T US D2-T US D3-T US D4-T TH > 4. TH < 4. CONDITIONS > 4.25, I SINK = 3.2mA > 2.5, I SINK =.2mA >.2, I SINK =.5mA >., I SINK = 8µA = 5 = 5 = 3 = 5 C LOAD = 2pF C LOAD = 25pF C LOAD = 2pF C LOAD = 4pF MIN TYP MAX. 5.5 5 2 4 TH -.8% TH TH +.8% TH - 2.5% TH + 2.5% 6 35.4 2 2 28 4 4 2 28 2 57 224 32 63 Note : The monitors through an internal, factory-trimmed voltage divider that programs the nominal reset threshold. Factory-trimmed reset thresholds are available in m increments from 2.5 to 5 (see Ordering and Marking Information). Note 2: This is the minimum time must be held low by an external pull-down source to set the active pull-up flip-flop. Note 3: Measured from OL to (.8 x ), R LOAD =..8.3 x 2.4 5.7 x.4.3.3.3 4.4.9 2 4.2 4.7 5.2 333 666 333 666 UNITS µa ppm/ C µs ms µs ns ns kω ns ma kω ns 2
Typical Operating Characteristics (T A = +25 C, unless otherwise noted.) 74HC5 PULL-UP CHARACTERISTICS +5 pf 4.7kΩ 74HC5 pf CC +5-4.7kΩ PULL-UP 2/div PULL-UP 2/div INPUT 5/div SUPPLY CURRENT (µa) 6 5 4 3 2 SUPPLY CURRENT vs. TEMPERATURE = 5 = 3 = -2 2ns/div SUPPLY CURRENT vs. SUPPLY OLTAGE POWER-DOWN DELAY vs. TEMPERATURE NORMALIZED TIMEOUT PERIOD vs. TEMPERATURE ( RISING) SUPPLY CURRENT (µa) 6 5 4 3 2 T A = +25 C T A = +85 C T A = -4 C -3 POWER-DOWN DELAY (µs) 5 4 3 2 FALLING AT m/µs TH = 4.63 TH = 3. -4 NORMALIZED TIMEOUT PERIOD.4.3.2...99.98.97-5 2 3 4 5.96 SUPPLY OLTAGE () NORMALIZED THRESHOLD vs. TEMPERATURE ( FALLING) MAXIMUM TRANSIENT DURATION vs. COMPARATOR OERDRIE PULL-UP TIME vs. TEMPERATURE NORMALIZED THRESHOLD.6.4.2..998.996-6 MAXIMUM TRANSIENT DURATION (µs) 8 6 4 2 TH = 4.63 TH = 3. T A = +25 C OCCURS ABOE CURE -7 PULL-UP-TIME (ns) 6 5 4 3 2 C L = 39pF C L = pf -8.994 COMP. OERDRIE, TH - (m) 3
Pin Description PIN 2 3 4 NAME FUNCTION Ground Active-Low Complementary Output. In addition to the normal N-channel pull-down, has a P-channel pull-up transistor in parallel with a 4.7kΩ resistor to facilitate connection to µps with bidirectional resets. See the Reset Output section. Manual Reset Input. A logic low on asserts reset. Reset remains asserted as long as is low, and for the reset timeout period (t RP ) after the reset conditions are terminated. Connect to if not used. Supply oltage and Reset Threshold Monitor Input LASER- TRIMMED RESISTORS REF GENERATOR 63k 2µs ONE-SHOT TRANSITION FLIP-FLOP R S FF Q 4.7k ACTIE PULL-UP ENABLE COMPARATOR.5 Figure. Functional Diagram 4
Detailed Description The has a reset output consisting of a 4.7kΩ pull-up resistor in parallel with a P-channel transistor and an N-channel pull down (Figure ), allowing this IC to directly interface with microprocessors (µps) that have bidirectional reset pins (see the Reset Output section). Reset Output A µp s reset input starts the µp in a known state. The asserts reset to prevent code-execution errors during power-up, power-down, or brownout conditions. is guaranteed to be a logic low for > (see the Electrical Characteristics). Once exceeds the reset threshold, the internal timer keeps reset asserted for the reset timeout period (t RP ); after this interval goes high. If a brownout condition occurs (monitored voltage dips below its programmed reset threshold), goes low. Any time dips below the reset threshold, the internal timer resets to zero and goes low. The internal timer starts when returns above the reset threshold, and remains low for the reset timeout period. The s output is designed to interface with µps that have bidirectional reset pins, such as the Motorola 68HC. Like an open-drain output, the allows the µp or other devices to pull low and assert a reset condition. However, unlike a standard open-drain output, it includes the commonly specified 4.7kΩ pull-up resistor with a P-channel active pull-up in parallel. This configuration allows the to solve a problem associated with µps that have bidirectional reset pins in systems where several devices connect to. These µps can often determine if a reset was asserted by an external device (i.e., the supervisor IC) or by the µp itself (due to a watchdog fault, clock error, or other source), and then jump to a vector appropriate for the source of the reset. However, if the µp does assert reset, it does not retain the information, but must determine the cause after the reset has occurred. The following procedure describes how this is done with the Motorola 68HC. In all cases of reset, the µp pulls low for about four E-clock cycles. It then releases, waits for two E-clock cycles, then checks s state. If is still low, the µp concludes that the source of the reset was external and, when eventually reaches the high state, jumps to the normal reset vector. In this case, stored state information is erased and processing begins from scratch. If, on the other hand, is high after the two E-clock cycle delay, the processor knows that it caused the reset itself and can jump to a different vector and use stored state information to determine what caused the reset. The problem occurs with faster µps; two E-clock cycles is only 5ns at 4MHz. When there are several devices on the reset line, the input capacitance and stray capacitance can prevent from reaching the logic-high state (.8 x ) in the allowed time if only a passive pull-up resistor is used. In this case, all resets will be interpreted as external. The µp is guaranteed to sink only.6ma, so the rise time cannot be much reduced by decreasing the recommended 4.7kΩ pull-up resistance. The solves this problem by including a pullup transistor in parallel with the recommended 4.7kΩ resistor (Figure ). The pull-up resistor holds the output high until is forced low by the µp reset I/O, or by the itself. Once goes below.5, a comparator sets the transition edge flip-flop, indicating that the next transition for will be low to high. As soon as is released, the 4.7kΩ resistor pulls up toward. When rises above.5, the active P-channel pull-up turns on for the 2µs duration of the one-shot. The parallel combination of the 4.7kΩ pull-up and the P-channel transistor onresistance quickly charges stray capacitance on the reset line, allowing to transition low to high within the required two E-clock period, even with several devices on the reset line (Figure 2). Once the one-shot times out, the P-channel transistor turns off. This process occurs regardless of whether the reset was caused by dipping below the reset threshold, being asserted, or the µp or other device asserting. Because the includes the standard 4.7kΩ pull-up resistor, no external pull-up resistor is required. To minimize current consumption, the internal pull-up resistor is disconnected whenever the asserts. Manual Reset Input Many µp-based products require manual reset capability, allowing the operator, a test technician, or external logic circuitry to initiate a reset. A logic low on asserts reset. Reset remains asserted while is low, and for the reset active timeout period after returns high. To minimize current consumption, the internal 4.7kΩ pull-up resistor on is disconnected whenever is asserted. 5
CIRCUITRY 4.7k C IN C STRAY C IN 68HC CIRCUITRY C IN OTHER DEICES Figure 2. Supports Additional Devices on the Reset Bus has an internal 63kΩ pull-up resistor, so it can be left open if not used. Connect a normally open momentary switch from to to create a manual reset function; external debounce circuitry is not required. If is driven from long cables or if the device is used in a noisy environment, connecting a.µf capacitor from to ground provides additional noise immunity. Applications Information Negative-Going CC Transients In addition to issuing a reset to the µp during power-up, power-down, and brownout conditions, these devices are relatively immune to short-duration negative-going transients (glitches). The Typical Operating Characteristics show the Maximum Transient Duration vs. Reset Threshold Overdrive, for which reset pulses are not generated. The graph was produced using negativegoing pulses, starting at RST max and ending below the programmed reset threshold by the magnitude indicated (reset threshold overdrive). The graph shows the maximum pulse width that a negative-going transient may typically have without causing a reset pulse to be issued. As the amplitude of the transient increases (i.e., goes farther below the reset threshold), the maximum allowable pulse width decreases. A.µF bypass capacitor mounted close to provides additional transient immunity. Ensuring a alid Output Down to CC = When falls below, no longer sinks current it becomes an open circuit. Therefore, highimpedance CMOS-logic inputs connected to can drift to undetermined voltages. This presents no problem in most applications, since most µp and other circuitry is inoperative with below. However, in applications where must be valid down to =, adding a pull-down resistor to will cause any stray leakage currents to flow to ground, holding low (Figure 3). R s value is not critical; kω is large enough not to load and small enough to pull to ground. R Figure 3. alid to = Ground Circuit 6
.5 t S t RP OR µc DELAY t R.8 x PULLED LOW BY µc OR GENERATOR ACTIE PULL-UP TURNS ON Figure 4. Timing Diagram Ordering and Marking Information PART NOMINAL TH () MIN t RP (ms) PKG. TOP MARK PART NOMINAL TH () MIN t RP (ms) PKG. TOP MARK US5D-T 5. AA US49D-T 4.9 AB US48D-T 4.8 AC US47D-T 4.7 AD US46D-T 4.63 AE US45D-T 4.5 AF US44D-T 4.39 AG US43D-T 4.3 AH US42D-T 4.2 AI US4D-T 4. AJ US4D-T 4. AK US39D-T 3.9 AL US38D-T 3.8 CA US37D-T 3.7 CB US36D-T 3.6 CC US35D-T 3.5 CD US34D-T 3.4 CE US33D-T 3.3 CF US32D-T 3.2 CG US3D-T 3.8 CH US3D-T 3. CI US29D-T 2.93 CJ US28D-T 2.8 CK US27D-T 2.7 CL US26D-T 2.63 CM US25D-T 2.5 CN US5D2-T 5. 2 CO US49D2-T 4.9 2 CP US48D2-T 4.8 2 CQ US47D2-T 4.7 2 CR US46D2-T 4.63 2 CS US45D2-T 4.5 2 CT US44D2-T 4.39 2 CU US43D2-T 4.3 2 C US42D2-T 4.2 2 CW US4D2-T 4. 2 CX US4D2-T 4. 2 CY US39D2-T 3.9 2 CZ US38D2-T 3.8 2 DA US37D2-T 3.7 2 DB US36D2-T 3.6 2 DC US35D2-T 3.5 2 DD US34D2-T 3.4 2 DE US33D2-T 3.3 2 DJ The is available in a SOT43 package, -4 C to +85 C temperature range. The first two letters in the package top mark identify the part, while the remaining two letters are the lot tracking code. Sample stocks generally held on the bolded products; also, the bolded products have 2,5 piece minimum-order quantities. Non-bolded products have, piece minimum-order quantities. Contact factory for details. Note: All devices available in tape-and-reel only. Contact factory for availability. 7
Ordering and Marking Information (continued) PART NOMINAL TH () MIN t RP (ms) PKG. TOP MARK PART NOMINAL TH () MIN t RP (ms) PKG. TOP MARK US32D2-T 3.2 2 DK US28D3-T 2.8 4 ET US3D2-T 3.8 2 DL US27D3-T 2.7 4 EU US3D2-T 3. 2 DM US26D3-T 2.63 4 E US29D2-T 2.93 2 DN US25D3-T 2.5 4 EW US28D2-T 2.8 2 DO US5D4-T 5. 2 EX US27D2-T 2.7 2 DP US49D4-T 4.9 2 EY US26D2-T 2.63 2 DQ US48D4-T 4.8 2 EZ US25D2-T 2.5 2 DR US47D4-T 4.7 2 FA US5D3-T 5. 4 DS US46D4-T 4.63 2 FB US49D3-T 4.9 4 DT US45D4-T 4.5 2 FC US48D3-T 4.8 4 DU US44D4-T 4.39 2 FD US47D3-T 4.7 4 D US43D4-T 4.3 2 FE US46D3-T 4.63 4 DW US42D4-T 4.2 2 FF US45D3-T 4.5 4 DX US4D4-T 4. 2 FG US44D3-T 4.39 4 DY US4D4-T 4. 2 FH US43D3-T 4.3 4 DZ US39D4-T 3.9 2 FI US42D3-T 4.2 4 EA US38D4-T 3.8 2 FJ US4D3-T 4. 4 EB US37D4-T 3.7 2 FK US4D3-T 4. 4 EC US36D4-T 3.6 2 FL US39D3-T 3.9 4 EG US35D4-T 3.5 2 FM US38D3-T 3.8 4 EH US34D4-T 3.4 2 FN US37D3-T 3.7 4 EI US33D4-T 3.3 2 FO US36D3-T 3.6 4 EJ US32D4-T 3.2 2 FP US35D3-T 3.5 4 EK US3D4-T 3.8 2 FQ US34D3-T 3.4 4 EL US3D4-T 3. 2 FR US33D3-T 3.3 4 EM US29D4-T 2.93 2 FS US32D3-T 3.2 4 EN US28D4-T 2.8 2 FT US3D3-T 3.8 4 EO US27D4-T 2.7 2 FU US3D3-T 3. 4 EP US26D4-T 2.63 2 F US29D3-T 2.93 4 ES US25D4-T 2.5 2 FW The is available in a SOT43 package, -4 C to +85 C temperature range. The first two letters in the package top mark identify the part, while the remaining two letters are the lot tracking code. Sample stocks generally held on the bolded products; also, the bolded products have 2,5 piece minimum-order quantities. Non-bolded products have, piece minimum-order quantities. Contact factory for details. Note: All devices available in tape-and-reel only. Contact factory for availability. TRANSISTOR COUNT: 59 Chip Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA 9486 48-737-76 999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.