Electronics Lab. (EE21338)

Princess Sumaya University for Technology The King Abdullah II School for Engineering Electrical Engineering Department Electronics Lab. (EE21338) Prepared By: Eng. Eyad Al-Kouz October, 2012

Table of Contents: Exp. No. Experiment Title: 1 The Diode Characteristics. 2 Diode Circuits: I. Small-Signal Diode. II. Large-Signal Diode. 3 BJT Amplifiers: I. Common Base Amplifier. II. Common Collector Amplifier. 4 Common Emitter amplifier Design 5 Op-Amp Amplifiers Design 6 Frequency Response of CE Amplifiers: 7 Multistage Amplifier: I. Multistage Amplifier II. Frequency Response of Multistage Amplifier. 8 Practical Exam 9 Direct Coupled Multistage Amplifier 10 Differential Amplifier.

Experiment (1): 1.1 Reference DIODE CHARACTERISTICS Sections 3.2-3.4, Electronic Devices and Circuits: The Diode as a Nonlinear Device, AC and DC Resistance, Analysis or DC Circuits Containing Diodes. 1.2 Objectives 1. To become familiar with checking diodes using volt-ohm meters. 2. To investigate the forward and reverse-biased characteristics of diodes. 3. To learn how to determine the dc and ac resistance or a diode. 1.3 Discussion A diode is a semiconductor device that conducts current much more readily in one direction than in the other. The voltage across the diode terminals determines whether or not the diode will conduct. If the anode is more positive than the cathode, the diode will conduct current and is said to be forward-biased. If the cathode is more positive than the anode, the diode will conduct only an extremely small leakage current and is said to be reverse-biased. When forward-biased, the voltage drop across a typical silicon diode is about 0.7V (germanium diodes drop about 0.3V). At forward voltages below this threshold, the diode only permits a small current to flow. This threshold is known as the knee of the diode characteristic curve. Since the relationship between voltage across and current through the diode changes in this region, the diode's resistance changes. The following formula is used to calculate the dynamic or ac resistance of the diode: V r D = I Where: V: is the small change in voltage across the diode I: is the corresponding change in current through the diode The static or dc resistance at any point along the characteristic curve is calculated using Ohm's law: Where: V R D = I V: is the voltage across the diode I: is the current through the diode

These relationships can be seen in the following characteristic curve diagram shown in figure 1.1: Figure 1.1 1.4 Procedure 1. To investigate the forward-biased characteristics of the diode, connect the following circuit shown in figure 1.2: Figure 1.2 2. Measure and record in Table 1.1, the diode voltage V D and the voltage V R across the resistor for each increment of E. 3. To investigate the reverse-biased characteristics of the diode, connect the following circuit shown in fig.1.3: 4. Measure and record in Table 1.2 the diode voltage V D for each decrement of E.

Figure 1.3 1.5 Questions 1. Calculate and record the current values in Table 1.1; calculate the voltage V R across the resistor and current values I in Table 1.2. 2. Using the values obtained for I and V D in Table 1.1, graph the forward I-V characteristic curve of the diode. Plot I on the vertical axis and V D on the horizontal axis. 3. Determine the static resistance of the diode at 0.1V, 0.5V, and 0.6V using the values obtained for I and VD from Table 1.1. 4. Graphically determine the dynamic resistance of the diode at 0.1 V, 0.5V, and 0.6V using the I-V characteristic curve obtained in question 2. 5. Using the values obtained for I and V D from Table 1.2, calculate the static resistance of the diode at -10V.

Table 1.1 E (Volts) V D (Volts) V R (Volts) I = V R /R 0.0 0.1 0.2 0.3 0.4 0.7 1.0 1.5 2.6 Table 1.2 E (Volts) V D (Volts) V R = E - V D (Volts) I = V R /R 0.0-6.0-11 -16-21 -27

Experiment (2): Diode Circuits I. SMALL-SIGNAL DIODE CIRCUITS 2. I.1 Reference Section 3.5, Electronic Devices and Circuits: Analysis of Small-Signal Diode Circuits. 2. I.2 Objectives 1. To determine the quiescent (Q) point of a small-signal diode circuit. 2. To analyze a small-signal diode circuit graphically and analytically. 2. I.3 Discussion Small-signals are those whose total peak-to-peak variation is only a fraction of the dc component. In small-signal diode circuits, the changes in current and voltage occur over a very small portion of the characteristic curve of the diode. The diode is operated in its forward-biased region, which is only linear above the knee or the characteristic. (In the linear region, a small change in diode voltage yields a large change in diode current). In order to use the linear portion of the diode's characteristic, the small-signal is added to a dc voltage which shifts the operating region past the knee of the characteristic. The following equation is used to find the current in a diode circuit having a series resistance: E VD I = Where: R E: is the applied dc voltage I: is the current through the diode R: is the series resistance V D : is the voltage across the diode This is the equation of a line, commonly called the dc load line. Every possible combination or current I and voltage V D is a point which lies on this line. The quiescent current and voltage correspond to the point of intersection of the characteristic curve and the load line. The name load line comes from the fact that the slope of the line is inversely proportional to the series resistance, or load, in the circuit. Figure 2.I.1 shows how the load line is altered when the input voltage has a small ac component. When the ac component is zero, the diode current and voltage have their quiescent values, I Q and V Q.

Figure 2.I.1 The ac resistance r D of the diode is the reciprocal of the slope of the characteristic at the Q point. Where: r d V nvt 0.026 = = =, n = 1 I I I V D : is the change in diode voltage I: is the change in diode current The total diode current and diode voltage can be calculated analytically using the following equations (assuming 0.7V voltage drop across the diode): D D Where: i v D ( t) = I D D E 0.7 A + id ( t) = + R R + r rd ( t) = 0.7 + R + r d Asinωt i d (t): is the ac component of the diode current A*( sinωt): is the applied ac source voltage d sinωt

2. I.4 Procedure 1. Connect the following small-signal diode circuit shown in figure 2.I.2: Figure 2.I.2 2. To measure the quiescent values, or dc components, of the diode current and voltage, set e(t) = 0V by replacing the generator with a short circuit to ground. Measure and record the dc diode voltage V D and the dc resistor voltage VR. The quiescent diode current can then be calculated using the relationship I Q = V R /R. 3. Reconnect the signal generator and set e(t) to 500mVp-p@1kHz. Using an oscilloscope set for ac input coupling, observe and accurately sketch the ac component of the voltage V D (t) across the diode. 4. To measure the ac voltage V R (t) across the resistor, it is necessary to interchange the diode and the resistor as shown in figure 2.I.3: Figure 2.I.3

5. Using an oscilloscope set for ac input coupling, observe and accurately sketch the ac component or the voltage V R (t) across the resistor. Having measured V R (t), the ac component i(t) of the total diode current i D (t) can be calculated using the relationship VR ( t) i( t) =. R 2. I.5 Questions 1. Determine the equation for the dc load line of the circuit in figure 2.I.2 and plot it on the I-V characteristic. Note the quiescent point Q where the load line intersects the characteristic curve. Compare this graphically obtained Q point with the measured Q point from procedure step 2. 2. Using the measurements of procedure steps 2 and 5, write an expression for the total diode current i D (t). 3. Using figure 2.I.1 as a guideline, draw the peak (maximum and minimum) ac load lines on the diode characteristic. Now draw the ac component of the diode voltage V D (t) and determine the resulting current i D (t). Compare the graphically obtained i D (t) with the results obtained analytically in question 2.

Experiment (2): Diode Circuits II. LARGE-SIGNAL DIODE CIRCUITS 2. II.1 Reference Section 3.6, Electronic Devices and Circuits: Analysis of large-signal Diode Circuits. 2. II.2 Objectives 1. To investigate the operation of half-wave rectifiers. 2. To demonstrate the function of diodes in basic logic circuits. 2. II.3 Discussion Large-signal diode circuits are those in which the current and voltage variations occur over a large range of the diode's characteristic, extending from the forward-biased region into the reverse-biased region. Thus, in large-signal circuits, diode operation is not confined to the linear region. This means that the diode resistance changes from a very low value to a very high one. Consequently, the diode acts very much like a switch. One or the most important applications of the diode in large-signal circuits is to perform rectification, by which an alternating current is changed to a direct current. Thus, load current will flow in one direction only. It is important to note, however, that the diode will drop about 0.7V of the voltage applied to the circuit containing it. Therefore, the applied voltage must be greater than 0.7V in order for any current to flow through the load. A half-wave rectifier with graphs of applied voltage and resulting current is shown in figure 2.II.1. Figure 2.II.1

Another important application of large signal diode circuits is that of performing digital logic functions. Digital logic gates are circuits which perform logical functions such as AND or OR. In the AND function, the output is true (a high voltage) only if both inputs are true. In the OR function the output is true if either input is true. In a typical logic circuit, an AND gate produces a 5V output only if inputs 1 and 2 are both 5V. The OR gate produces a 5V output if either input 1 or input 2 is 5V. 2. II.4 Procedure 1. To investigate the use of a diode in half-wave rectifier circuits, connect the circuit shown in fig. 2.II.2: Figure 2.II.2 2. With a dual-trace oscilloscope set for dc input coupling, measure the peak-to-peak values of the input voltage e(t) and the output voltage V R (t). Sketch both waveforms. 3. Reverse the diode terminals in figure 2.II.2 and repeat procedure steps 2. 4. Change the input signal e(t) in figure 2.II.2 to a 5Vp-p square wave and repeat procedure step 2. 5. To investigate the use of diodes in simple digital logic gates, connect the following circuit shown in figure 2.II.3: Figure 2.II.3

6. Measure and record the values of V O at each of the combinations of values of V 1 and V 2 in Table 2.II.1. 7. To investigate another useful logic gate, connect the following circuit shown in figure 2.II.4: Figure 2.II.4 8. Repeat procedure step 6 for the values in Table 2.II.2 and the circuit of figure 2.II.4. 2. II.5 Questions 1. Using the results of procedure step 2, calculate the peak-to-peak values of the current i(t) and sketch its waveform. 2. Repeat question 1 for the results of procedure step 3. 3. Calculate the peak-to-peak values of the current waveform i(t) in the circuit of procedure step 4 and sketch its waveform. 4. For each set of voltages V 1 and V 2 in Tables 2.II.1 and 2.II.2 determine whether each of the diodes D 1 and D 2 is forward or reverse-biased. Calculate V O, assuming that each diode has a forward-biased voltage drop of 0.7V. Compare the calculated values of V O with the measured values. 5. What digital logic function is performed by the circuit in figure 2.II.3, and figure 2.II.4?

Table 2.II.1 V 1 (Volts) V 2 (Volts) V O (Volts) 0 0 0 5 5 0 5 5 Table 2.II.2 V 1 (Volts) V 2 (Volts) V O (Volts) 0 0 0 5 5 0 5 5

Experiment (3): BJT Amplifiers 3. I.1 Reference I. COMMON BASE AMPLIFIER Sections 5.1, 5.3, and 5.6, E1ectronic Devices and Circuits: Amplifier Fundamentals, Amplifier Analysis using Small-Signal Models. 3. I.2 Objectives 1. To investigate the common base amplifier using voltage-divider bias. 2. To measure the open-circuit voltage gain, loaded voltage gain, input resistance, and output resistance of the common base amplifier. 3. To evaluate the common base amplifier using the small-signal equivalent model. 3. I.3 Discussion Although it has a small input resistance, the common base amplifier can be used in some applications requiring high voltage gain. As will be demonstrated in a later experiment, the common base amplifier is also used in conjunction with FET amplifiers for high frequency amplification. When used as a small-signal amplifier; the input and output voltages and currents vary over a small range of the transistor's characteristic curves. In this situation, the amplifier is said to be operating in its Linear region, i.e. the gain of the amplifier is the same for all amplitude variations at the input and output. Small-signal amplifiers are often analyzed using ac equivalent circuits. Figure 3.I.1 shows the small-signal ac equivalent circuit of the common base amplifier in figure 3.I.3. Notice that no capacitors or dc voltage sources appear in the equivalent circuit, because they are assumed to be short-circuits to the ac signal. R 1 and R 2 in figure 3.I.3 are similarly shorted to ac ground. The ratio of output voltage to input voltage when the amplifier is not loaded (R L =, or open) is called the open-circuit voltage gain. The open-circuit voltage gain of the common base amplifier can be calculated using the following equation: V R O C rc RC AV = = V R r r Where: R C : is the external collector resistor r c : is the internal collector resistance R E : is the external emitter resistor in E e e

Where: r e : is the internal emitter resistance: I E : is the dc emitter current r e 0.026 = I E Figure 3.I.1 The input resistance r in (stage) of the common base amplifier is the ac resistance looking into the input of the amplifier stage. As can be seen in figure 3.I.1: r in( stage) = R E r e r e The output resistance r o (stage) of the common base amplifier is the ac resistance looking back into the output of the amplifier stage. As can be seen in figure 3.I.1: r O( stage) = R C r c R C When a load resistor R L is connected across the output and a real signal source is connected to the input, voltage divisions take place at both the input and output. Therefore, the voltage gain from source to load is calculated as follows: V r L in( stage) RL = A V V S rs + rin ( stage) RL + ro ( stage) Where: r S : is the internal resistance of the signal source

3. I.4 Procedure 1. To measure the open-circuit voltage gain, Av, and the output resistance, r O (stage) of a common base amplifier, connect the circuit in figure 3.I.2. Measure the dc voltage across R E. This value will be used to determine the bias current: I E = V E /R E, and the internal emitter resistance: r e 0.026/I E. Figure 3.I.2 2. With the signal generator's frequency set to 10 khz, and V S = 20mVp-p. Measure and record the peak-to-peak output voltage V O (including the phase relationship between V in and V O ). The open-circuit voltage gain A V is V O /V in. 3. To measure the output resistance, r o (stage) of the common base amplifier, connect a 10kΩ potentiometer connected as a rheostat between the output coupling capacitor and ground. Adjust this potentiometer until V O is (one-half of the previous output). Remove the potentiometer and measure its resistance. By the voltage divider rule, this resistance equals the output resistance of the common base amplifier. 4. To measure the loaded voltage gain from source-to-load, V L /V S, of the common base amplifier, connect the circuit shown in figure 3.I.3.

Figure 3.I.3 5. With the signal generator's frequency set to 10 khz, and V S = 20mVp-p. Measure and record the peak-to-peak output voltage VL and the phase relationship between V in and V L. The voltage gain from source to load is V L /V S. 6. Reconnect the circuit of figure 3.I.3. Now increase the amplitude of the signal source until the output voltage V L starts to distort. Measure the peak-to-peak value of the output voltage at the point where it just starts to distort. 3. I.5 Questions 1. Using the measurements made in procedure step 1, calculate the quiescent current I E, and the internal emitter resistance r e. 2. Using the values obtained in question 1, and assuming that the internal collector resistance is infinite, draw the small-signal ac equivalent circuit for the amplifier of figure 3.I.3. 3. Using the equivalent circuit from question 2, calculate the theoretical values for A V, V L /V S, r in(stage), and r O(stage). Compare these with the measured values. 4. Explain the distortion observed in procedure step 6. Why does the output waveform distort when the amplitude of the input is increased above a certain value?

Experiment (3): BJT Amplifiers (1) II. COMMON COLLECTOR AMPLIFIER 3. II.1 Reference Sections 5.1, 5.3, and 5.6, Electronic Devices and Circuits: Amplifier Fundamentals, Amplifier Analysis using Small-Signal Models, Improved Bias Methods for Discrete BJT Circuits. 3. II.2 Objectives 1. To measure the open-circuit voltage gain, input resistance, and output resistance of the common collector amplifier. 2. To evaluate the common collector amplifier using the small-signal equivalent model. 3. To demonstrate the effectiveness of the common collector as a buffer between a high impedance source and a low impedance load. 3. II.3 Discussion The last important small-signal amplifier configuration or the BJT is the common collector, or emitter follower amplifier. It is extremely useful because it has very high input resistance, high current gain, very small output resistance, and approximately unity voltage gain. The high input resistance and low output resistance make the emitter follower an ideal buffer between a high impedance source and a low impedance load. A buffer is any circuit that keeps the source from being affected by a load. For example, a common emitter amplifier with a 10kΩ output resistance could not provide very much voltage gain to a 50Ω load resistor. The following small-signal ac equivalent circuit that shown in figure 3.II.1 can be used to calculate the gain, input resistance, and output resistance of the common collector amplifier of figure 3.II.2. Note that the current-controlled current source in figure 3.II.1 is pointing down, like that of the common emitter amplifier. However, the load in this case is in parallel with the emitter resistor, so the output voltage is in phase with the input voltage. The open-circuit voltage gain, A V, of the emitter follower amplifier can be calculated using the following equation (since R E is typically much larger than r e, the equation can be approximated as1): RE A V = 1 re + RE The input resistance, r in(stage) of the emitter follower amplifier can be calculated using the following equation: r = R R β ( r + R R in( stage) 1 2 e E L )

Figure 3.II.1 The output resistance, r O(stage) of the emitter follower amplifier can be calculated using the following equation: r O( stage) = R E r e R + 1 R β 2 r S r e 3. II.4 Procedure 1. Use Digital Multimeter (DMM) to measure the β's of the transistors. 2. To measure the open-circuit voltage gain, A V, of the common collector amplifier, connect the following circuit shown in figure 3.II.2: 3. With the signal generator's frequency set to 10 khz, and V S = 100mVp-p. Measure and record the peak-to-peak output voltage VO and the phase relationship between V in and V O. These values can be used to calculate the open-circuit voltage gain, A V.

Figure 3.II.2 3. II.5 Questions 1. Calculate the dc emitter current I E and the internal emitter resistance r e for the circuit of figure 3.II.2. 2. Using the values obtained in question 1, draw the small-signal ac equivalent circuit for the amplifier or figure 3.II.2. 3. Using the equivalent circuit from question 2, calculate the theoretical values for A V, r in(stage), and r O(stage).

Experiment (4): Common Emitter Amplifier Design Design References: 4.1. Objectives: 1. Electronic Devices and Circuits by Salivahanan: Sections 5.1, 5.3, and 5.6. 2. Microelectronic Circuits by Sedra & Smith: Sections 4.8, and 4.10. 3. Lab website: www.psut.edu.jo/sites/eyad Electronics Lab Theory of Experiments Experiment 3 1. To design a common emitter amplifier using bipolar junction transistor (BJT), and to study the characteristics of the design amplifier. 2. To study the impact of various bypass and coupling capacitors on the overall performance of the common emitter amplifier. 4.2. Introduction: The basic BJT amplifier circuit like the one shown in figure 4.2 can be designed to exhibit various desirable characteristics. An important decision involved in designing this amplifier is the choice of the operating point (Q-point). This operating point refers to the amount of DC bias current that flows through the transistor. It also refers to the resulting DC voltage across its junctions. The Q-point of such a circuit can be placed anywhere on the DC load line, depending on the choice of the DC equivalent circuit component values. The location of the Q-point determines the distortion characteristics of the AC signal. By properly locating the Q-point, the symmetrical peak-to-peak swing of the AC collector current can be maximized. In general, the DC load line must bisect the AC load line in order to allow the maximum amount of symmetrical swing of the collector current as well as the maximum amount of undistorted voltage swing in the load resistor. 4.3. Theory: The most important BJT small-signal configuration is the common emitter amplifier. It is extremely useful because it has high voltage gain, high current gain, moderate input resistance and moderate output resistance. The common emitter amplifier will be used as the example in most general amplifier experiments in this book. In many common emitter amplifiers, the emitter resistor is bypassed, by connecting a capacitor in parallel with it. At high frequencies, the capacitor effectively shorts the emitter resistor to ground, but at dc the capacitor is large impedance that does not affect the dc biasing of the circuit. The purpose of the emitter bypass capacitor is to increase the gain of the amplifier by eliminating ac degeneration. AC degeneration occurs when there is a voltage present across the emitter resistor that is out of phase with the output voltage.

The small-signal ac equivalent circuit in figure 4.1 can be used to calculate the gain, input resistance, and output resistance of the common emitter amplifier of figure 4.2. The equivalent circuit does not show R E because it is assumed to be completely bypassed (shorted to ground) by C E at the frequency of operation. Note that the currentcontrolled current source in figure 4.1 is pointing down, unlike that of the common base amplifier. This means that the output voltage is negative with respect to the input voltage, corresponding to a 180 phase shift. For this reason the common emitter amplifier is referred to as an inverting amplifier. The open-circuit voltage gain A V of the common emitter amplifier can be calculated using the appropriate one of the following equations (the minus sign means that the common emitter amplifier is an inverting amplifier): With R E bypassed: With R E unbypassed: A V V = V A V O in = V = V O in R C r e e r c β R r E e C rc RC β R = r + R R E C Figure 4.1 The input resistance r in(stage) of the common emitter amplifier can be calculated using the appropriate one of the following equations: With R E bypassed: rin ( stage) = βre R1 R2 With R E unbypassed: rin ( stage) = ( β ( re + RE )) R1 R2 The output resistance, r O(stage) of the common emitter amplifier can be calculated using the following equation: rc ro ( stage) = RC RC β

The loaded voltage gain from source-to-load V L /V S can be calcu1ated using the following equation: V r L in( stage) RL = A V V S rs + rin ( stage) RL + ro ( stage) 4.3. Pre-Lab Assignment work: Design Topic: Design a Common Emitter Amplifier circuit by using four discrete resistors (R 1, R 2, R C and R E ), and either 2N3904 or 2N2222 NPN transistors. Design Constraints: Assume the following constraints: 1. DC power Supply is +15 V. 2. V BE for NPN transistor = 0.7 V. 3. β for NPN transistor = 200. 4. Coupling and bypass capacitors are 10µF. Design Specifications: 1. V E = 1.0 V. 2. I C = 1 ma. 3. V C = 0.68*V CC 4. Minimum open voltage gain bypassed is 100 V/V.

4.4. Procedure: 1. Connect the amplifier circuit you designed. Add Capacitors C 1, C 2, and C E each of these capacitors is 10µF. Make sure the positive polarity of these capacitors are connected to the higher positive voltage in the circuit. 2. Measure the DC bias voltages on the base, emitter and collector. Compare the measured voltages with the design and calculation values. Tabulate the measured versus the calculated bias voltages. V B V E V C Measured values Design values 3. With the signal generator's frequency set to 10 khz, and V S = 20mVp-p. Measure and record the peak-to-peak output voltage V O and the phase relationship between V in and V O. The open-circuit voltage gain A V is V O /V in. 4. To measure the voltage gain from source-to-load, V L /V S of the common emitter amplifier, connect R L = 1KΩ from output of the circuit to the ground. 5. With the signal generator's frequency set to 10 khz, and V S = 30mVp-p. Measure and record the peak-to-peak output voltage VL and the phase relationship between V in and V L. The voltage gain from source to load is V L /V S. 6. Disconnect the emitter bypass capacitor C E from the circuit designed, and repeat procedure steps 3 and 5.

Experiment (5): OP-Amp Amplifiers Design 5.1 Reference 1. Microelectronic Circuits by Sedra & Smith: Chapter 2. 2. Analog Electronics: Devices, Circuits, and Techniques by Williams, Gerald E, Chapter 8. Minneapolis/St. Paul. West Publishing Company, 1996. 3. Electronic Devices and Circuits: Sections 14.1 and 14.3. 5.2 Objectives 1. To design and measure the ac characteristics of the non-inverting op amp configuration. 2. To design and measure the ac characteristics of the inverting op-amp configuration and to observe the 180 phase shift. 3. To design and demonstrate the use of operational amplifiers for performing mathematical operations-summation. 5.3 Discussion The basic non-inverting op amp configuration is shown in figure 5.1. The operational amplifier itself, within the triangle, has a very large open loop voltage gain, a reasonably high R in and a fairly low R O. These are all desirable characteristics. Resistors R l and R 2 are feedback resistors which generally improve the amplifier's characteristics at the expensive of voltage gain. At the same time, the voltage gain is stabilized to a particular value, which is also a desirable characteristic. The op amp with feedback will have characteristics determined mostly by the two external resistors. The characteristics of the non-inverting op amp are given in equations 5.1, 5.2 and 5.3. R = Ω... Eq.5.1 R A in O V = 0Ω... Eq.5.2 R = 1+ R 2 1... Eq.5.3 Sometimes an additional resistor is connected from (+) to ground in order to set the input resistance to a specific value. A very common configuration of the noninverting op amp is the "buffer" amplifier used to isolate stages. The buffer is made by replacing R 2 in figure 5.1 with a short circuit, and replacing R l with an open circuit. Equation 5.3 will show that this will provide a voltage gain of exactly one.

Again, the characteristics are determined largely by the external biasing resistors. The characteristics of the inverting op amp are given in Equations 5.4, 5.5 and 5.6. R R in O = R... Eq.5.4 1 = 0Ω... Eq.5.5 R2 AV =... Eq.5.6 R1 When the first operational amplifiers were constructed, their primary function was to perform mathematical operations in analog computers. These included summation, subtraction, multiplication, division, integration, and differentiation. Figure 5.3 shows an example of how an operational amplifier is connected to perform voltage summation. (In this figure, an ac and a dc voltage are summed). In general: R F RF V = V + V + etc O in1 in2... Rin 1 Rin2

5.4 Design and simulation Part: 1. Design the Non-Inverting Amplifier shown in figure 5.1. The voltage gain needed for your design is 69V/V. R 1 R 2 2. Design the Inverting Amplifier shown in figure 5.2. The voltage gain needed for your design is -25V/V. R 1 R 2 3. Design the summer amplifier shown in figure 5.3. The designed will be achieved this equation: V O = - (2.12*V S + 1*5V DC ) Where: V S =2Vp-p @ 1 KHz. R in1 R in2 R F

5.5 Procedure Design the Non-Inverting Amplifier: 1. Connect your designed circuit of figure 5.1 using an 8-pin LM741 opamp. 2. Using a 180kΩ sensing resistor, complete the amplifier measurements required for Table 5.1. Use a generator frequency of 1 khz. Figure 5.1 Table 5.1 Amplifier Measurements V G V in V OC V O =V L Phase shift 200mVp-p @1 KHz Design the Inverting Amplifier: 3. Connect your designed circuit of figure 5.2. Using an 8-pin LM741 opamp. 4. Using a 39kΩ sensing resistor, complete the amplifier measurements required for Table 5.2. Use a generator frequency of 1 khz.

Figure 5.2 Table 5.2 Amplifier Measurements V G V in V OC V O =V L Phase shift 200mVp-p @1 KHz Design the Summing Amplifier: 5. Connect your designed circuit shown in figure 5.3. Figure 5.3 6. With V S adjusted to produce a 2Vp-p sine wave at 1 khz, observe the output voltage V O on an oscilloscope set to dc input coupling. Sketch the output waveform. Be sure to note the dc level in the output. 7. Interchange the 5V dc power supply and the 2Vp-p signal generator. Repeat procedure step 6.

Experiment (6): FREQENCY RESPONCE OF AMPLIFER 6. 1 Reference Sections 10.1-10.3, 10.6, Electronic Devices and Circuits: Definitions and Basic Concepts, Decibels and Logarithmic Plots, Series Capacitance and Low Frequency Response, Frequency Response or BJT Amplifiers. 6. 2 Objectives 1. To measure the lower cutoff frequency of a common emitter amplifier. 2. To measure the lower cutoff frequencies due to each coupling and bypass capacitor. 3. To measure the upper cutoff frequency of a common emitter amplifier. 4. To measure the upper cutoff frequencies due to shunt capacitances. 6. 3 Discussion Since the impedance of coupling capacitors increase as frequency decreases, the voltage gain or a BJT amplifier decreases as frequency decreases. At very low frequencies, the capacitive reactance of the coupling capacitors may become large enough to drop some of the input voltage or output voltage. Also, the emitter bypass capacitor may become large enough that it no longer shorts the emitter resistor to ground. The following equation can be used to determine the lower cutoff frequency, where the voltage gain drops 3dB from its mid-band value (0.707 times the mid-band A V ): Where: f1( C1) = 2 π ( r 1 in ( stage) + f 1 (C 1 ) = lower cutoff frequency due to C 1 C 1 = input coupling capacitance r in(stage) = input resistance of the amplifier r S = source resistance f ( C 1 2 ) = 2 π ( r 1 O ( stage) + r ) C S R ) C Where: f 1 (C 2 ) = lower cutoff frequency due to C 2 C 2 = output coupling capacitance r O (stage) = output resistance of the amplifier R L = load resistance L 2 1

1 f1( CE ) = 2π ( rth ) CE Where: f 1 (C E ) = lower cutoff frequency due to C E C E = emitter bypass capacitance r TH = Thevenin resistance parallel to the capacitor: RB rs r = TH RE re + β Where: R B = parallel combination of all the input bias resistors Provided that f 1 (C 1 ), f 1 (C 2 ), and f 1 (C E ) are not close in value, the actual lower cutoff frequency is approximately equal to the largest of the three. The capacitive reactance of a capacitor decreases as frequency increases. This fact can lead to problems when an amplifier is used for high-frequency amplification. A transistor has inherent shunt capacitances between each pair of its terminals. At high frequencies, these capacitances effectively short (shunt) the ac signal voltage. Therefore, in high-frequency amplifiers, shunt capacitance must be extremely small. In this experiment, artificial shunt capacitors will be installed in the amplifier circuit because it is extremely difficult to measure the actual interelectrode capacitances of the transistor. It is equally difficult to measure stray shunt-capacitance due to the wiring of the circuit. Since the artificial capacitors are much larger than the real capacitance already present, the parallel combination of real capacitance and artificial capacitors is approximately equal to the value of the artificial capacitors. The objective is to investigate the high frequency response of the amplifier to gain insight into the problems associated with shunt capacitance, and to obtain practice measuring the upper cutoff frequency of an amplifier. The upper cutoff frequency is the larger of the two frequencies where the voltage gain of the amplifier is -3dB or 0.707 times the mid-band value (the lower cutoff frequency is the other frequency where this occurs). 6. I.4 Procedure 1. Use the DMM to measure the β of the transistor. 2. To measure the low frequency response of the common emitter amplifier, connect the following circuit shown in figure 6.1:

The plus (+) signs show the polarities or the electrolytic capacitors used in proceduresteps 5-8): Figure 6.1 3. With V S = 50mV p-p@10khz, measure and record V L. This value can be used to determine the mid-band voltage gain V L / V S. 4. Now decrease the frequency of the signal generator to each frequency in Table 6.1 measuring the value of V L at each frequency. Make sure the output voltage from the signal generator is constant. These values will be used to plot the low frequency response of the amplifier. 5. By making two capacitors very large, the effects of those capacitors on the lower cutoff frequency can be made negligible. The cutoff frequency due to the third capacitor can then be measured. With this in mind, reconnect the circuit of figure 6.I.1 with the following capacitor values (observe polarities as shown in figure 6.1): C 1 = 0.1µf, C 2 = 100µf, C E 100µf. 6. Making certain that V S remains at 50mVp-p, adjust the frequency of the signal generator until the output voltage (and therefore the voltage gain) equals 0.707 times that measured in procedure step 3. The frequency where this occurs is f 1 (C 1 ). 7. Repeat procedure steps 5 and 6 to determine f 1 (C 2 ), using the following capacitor values: C 1 = 100µf, C 2 =0.22µf, C E = 100µf

8. Repeat procedure steps 5 and 6 to determine f 1 (C E ), using the following capacitor values: C 1 =100µf, C 2 =100µf, C E =4.7µf 6. 5 Questions 1. Using the results obtained of step 1, of the β of the transistor. Determine r e. Then use these values to calculate the mid-band ac parameters of the circuit in figure 6.1 ( r in(stage), r O(stage), V L /V S ). 2. Calculate the values for V L /V S at each frequency in Table 6.1. Then plot these values on log-log graph paper. Include asymptotic lines which show the break frequency due to each capacitor. From this graph of frequency response, obtain the lower cutoff frequency (-3dB point) and label the graph accordingly. 3. Ca1culate f 1 (C 1 ), f 1 (C 2 ), and f 1 (C E ) for the common emitter amplifier. Compare these with the 1ower cutoff frequencies measured in procedure steps 5-8. 4. Which capacitor had the most effect on the lower cutoff frequency? Compare the lower cutoff frequency due to this capacitor with the overall cutoff frequency determined in question 2. Comment and explain.

Table 6.1 Frequency (Hz) 50 100 200 250 500 750 900 1k 1.5k 2k 5k 7.5k 10k 20k 50k 75k 100k 250k 500k 600k 700k 750k 800k 850k 900k 950k 1M 5M 7.5M 10M 12M V L (Vp-p) A V =V L /V S V/V A V (db) =20log(A V )

Experiment (7): Multistage Amplifier 7. I.1 Reference I. MULTISTAGE AMPLIFIER Sections 11.1-11.3, Electronic Devices and Circuits: Gain Relations in Multistage Amplifiers, Methods of Coupling, RC Coupled BJT Amplifiers. 7. I.2 Objectives 1. To determine the overall voltage gain of cascaded common-emitter amplifiers. 2. To demonstrate the loading effect of cascading common-emitter amplifiers. 7. I.3 Discussion Often in electronic amplifier systems, several amplifiers are cascaded in order to furnish adequate gain. It is easy to see that the resulting gain of two cascaded ideal amplifiers would be the product of the individual gains. However, since voltage sources and amplifiers have output resistance, and amplifiers and loads have input resistance, there are voltage divisions taking place between these stages or amplification. Figure 7. I.1 shows a two-stage amplifier. A O1 and A O2 are the open-circuit (unloaded) voltage gains of each stage: Figure 7.I.1 To calculate the overall gain of the multistage amplifiers, the product of the individual open-circuit gains of each stage is reduced by the voltage divider at the input

and the output of each stage. The following equation can be used to calculate the overall gain of a two-stage amplifier. V V L S ri 1 = rs + r i1 A O1 r O1 r i 2 + r i2 A O2 r O2 RL + R L 7. I.4 Procedure 1. Use DMM to measure the β's of two transistors. 2. To measure the open-circuit voltage gain of a single stage, connect the following common emitter amplifier circuit shown in figure 7.I.2: Figure 7.I.2 3. With the signal generator set at 50mVp-p@1kHz, measure the no-load ac output voltage V O as well as the phase shift of the output with respect to the input. This can be used to determine the open-circuit unloaded voltage gain A O. 4. To demonstrate the effects on overall voltage gain of cascading two common emitter amplifiers, make the following interconnection of two identical amplifiers (stages) shown in figure 7.I.3: 5. With the signal generator set at 50mV p-p at 1 khz, measure the output voltage V L across the load resistor, as well as the phase shift with respect to the input voltage V S.

Figure 7.I.3 7. I.5 Questions 1. Using the results of step 1, calculate the input resistance r in (stage), the output resistance r O(stage), and the unloaded voltage gain (A O ) of the two individual common emitter amplifier stages. Compare the calculated voltage gain with the actual measured voltage gain obtained in procedure step 3. 2. Using the results of question 1, calculate the overall gain from source-to-load V L /V S. Compare the calculated gain with that measured in procedure step 5. 3. Explain the phase relationship of the output voltage V L with respect to the input voltage V S as observed in procedure step 5.

Experiment (7): Multistage Amplifier 7. II.1 Reference II. FREQUENCY RESPONSE OF MULTISTAGE AMPLIFIERS Sections 11.1-11.3, Electronic Devices and Circuits: Gain Relations in Multistage Amplifiers, Methods of Coupling, RC Coupled BJT Amplifiers. 7. II.2 Objectives 1. To measure the low frequency response of a two-stage common emitter amplifier. 2. To measure the lower cutoff frequency due to each coupling capacitor of the two-stage common emitter amplifier. 7. II.3 Discussion Whenever several amplifiers are RC coupled in order to furnish adequate gain, there will be additional coupling capacitors affecting the lower frequency response. As was the case with the single-stage amplifier, there is a lower cutoff frequency associated with each coupling and bypass capacitor. The calculations for lower cutoff frequency are the same as for the single-stage amplifier, except there are additional capacitors that must be taken into account. In this experiment, no emitter-bypass capacitors will be used. This will simplify the calculations for r in(stage) and V L /V S at mid-band, and it will reduce the number of lower cutoff frequencies to be calculated. Figure 7.II.1 shows the Thevenin equivalent of a two-stage amplifier. A O1 and A O2 are the open-circuit (un-loaded) voltage gains of each stage. The capacitors C 1, C 2, and C 3 are coupling capacitors. The following equations are used to calcu1ate the lower cutoff frequency due to each coupling capacitor C 1, C 2, and C 3. The lower cutoff frequency of a single-stage amplifier: 1 f1( C1) = 2π ( r + r ) C f ( C 1 1 2 f ( C 3 S ) = 2π ( r ) = 2π ( r O1 O2 i1 1 + r i2 1 + R 1 ) C L 2 ) C 3

Where: f 1 (C 1 ): is the cutoff frequency due to the input coupling capacitor f 1 (C 2 ): is the cutoff frequency due to the coupling capacitor between the amplifier-stages f 1 (C 3 ): is the cutoff frequency due to the output coupling capacitor Figure 7.II.1 7. II.4 Procedure 1. Use DMM to measure the β's of two transistors. 2. To measure the low frequency response of a two-stage RC coupled amplifier, connect the following circuit shown in figure 7.II.2 (the plus (+) signs show the polarities of the electrolytic capacitors used in procedure steps 5-to-8): 3. With the signal generator set to 50mVp-p@15kHz, measure the ac output voltage V L. This value can be used to determine the mid-band voltage gain from source-to-load, V L /V S. 4. Now decrease the frequency of the signal generator until the output voltage V L is 0.707 times the level measured in procedure step 3. The frequency where this occurs is the lower cutoff frequency of the amplifier. Make a sufficient number of measurements from 15 khz down to 50Hz as shown in Table 7.II.1 to use for graphing the low frequency response of the amplifier.

Figure 7.II.2 5. By making two capacitors very large, the effects of those capacitors on the lower cutoff frequency can be made negligible. The cutoff frequency due to the third capacitor can then be measured. With this in mind, reconnect the circuit of figure 7.II.2 with the following capacitor values (observe polarities as shown in figure 7.II.2): C 1 = 0.1µf C 2 = 100µf C 3 = 100µf 6. Adjust the frequency of the signal generator until the output voltage (and therefore the voltage gain) equals 0.707 times that measured in procedure step 3. The frequency where this occurs is f 1 (C 1 ). 7. Repeat procedure steps 5 and 6 for f 1 (C 2 ), using the following capacitor values: C 1 = 100µf C 2 = 0.0022µf C 3 = 100µf 8. Repeat procedure steps 5 and 6 for f 1 (C 3 ), using the following capacitor values: C 1 = 100µF C 2 = 100µF C 3 = 0.01µF

7. II.5 Questions 1. Use the values of β to calculate the ac parameters of the amplifier (r in(stage1), r o(stage1), r in(stage2), r o(stage2). and (V L /V S ) of the entire two-stage common emitter amplifier. 2. Calculate the value of V L /V S for each measurement made in procedure step 4. Plot these values on log-log paper. Add asymptotic lines to this graph and show the break frequency due to each coupling capacitor. Use the asymptotes to verify that the gain falls off 6dB/octave after the first break, 12dB/octave after the second, and 18dB/octave after the third. 3. Calculate the theoretical values of f l (C 1 ), f 1 (C 2 ), and f 1 (C 3 ) for the two-stage common emitter amplifier of figure 7.II.2. Compare these with the lower cutoff frequencies measured in procedure steps 5-8. Table 7.II.1 Frequency (Hz) V L (Vp-p) A V =V L /V S A V (db) 100 250 500 750 1k 5k 10k 50k 75k 100k 250k 500k 750k 1M 5M 7.5M 10M

Experiment (8): Practical Exam Experiments (1-7)

Experiment (9): 9.1 Reference DIRECT-COUPLED MULTISTAGE AMPLIFIERS Sections 11.1, 11.2, and 11.4, Electronic Devices and Circuits: Gain Relations in Multistage Amplifiers, Methods of Coupling, Direct-Coupled BJT Amplifiers. 9.2 Objectives 1. To measure the open-circuit voltage gain of direct-coupled common emitter amplifiers. 2. To measure the open-circuit voltage gain of direct-coupled complementary commonemitter amplifiers. 3. To demonstrate the use of direct-coupled amplifiers to amplify dc. 9.3 Discussion In many applications a system must amplify either dc or a very low frequency input voltage. For example, a measurement of outside temperature would show a nearly sinusoidal variation with a positive peak in the early afternoon and a negative peak in the early morning. A voltage waveform representing this variation would have a frequency of about 11.6µHz. At a frequency this low, coupling capacitors would prevent any of the waveform from passing through the amplifier. Therefore, direct-coupled amplifiers are used. The circuit shown in figure 9.1 is an example of a direct-coupled amplifier. Notice that the dc collector voltage V C1 of the first stage is also the dc base voltage V B2 of the second stage. Since the collector-to-base junction of an NPN transistor must be reverse-biased to keep the collector voltage in the linear region of the output characteristics, the collector voltage of Q 2 must be more positive than the collector voltage of Q 1, after several stages of amplification, the collector voltage approaches the supply voltage and the voltage swing of the output is limited. To correct the problem of increasing collector voltages from one stage to the next, the second stage can be changed to a complementary (PNP) device, as shown in figure 8.2. Recall that the collector voltage of a PNP transistor must be more negative than its base voltage. Therefore, the collector voltage of Q 2 is less than the collector voltage of Q 1. Typically, direct-coupled amplifiers will consist of an NPN stage followed by a PNP stage, etc. For either the circuit in figure 9.1 or the circuit in figure 9.2, the no-load voltage gain is calculated just as it is with RC coupled amplifiers. In this experiment, the large

value of R E2 in both circuits makes the loading effect of the second stage on the first negligible. Therefore, the following approximation can be used for the circuits in figures 9.1 and 9.2 (the output voltage of the circuit in figure 9.2 will be inverted): A V R R C1 E1 R R C 2 E 2 The following approximation can be used to calculate the loaded voltage gain V L /V S of the circuits in figures 9.1 and 9.2: VL RL A V VS RL + RC 2 9.4 Procedure 1. To demonstrate the direct-coupled common emitter amplifier, connect the following circuit shown in figure 9.1: Figure 9.1 2. Adjust the variable dc power supply connected to the base of Q 1 until the input voltage, V B1, is 1.50V dc. Measure and record all quiescent voltages on both transistors, including V C2. 3. Increase the variable dc power supply until the input voltage V B1 is 1.60V dc. Measure and record the corresponding voltage V C2. Decrease the variable dc power supply until the input voltage V B1 is 1.40V dc. Measure and record the corresponding voltage V C2. The overall voltage gain A V can be found from V C2 / V B1, where means the change in.

4. Connect a 10kΩ load to the circuit in figure 9.1 between the collector of Q 2 and ground and repeat procedure steps 2 and 3. The values obtained from these measurements can be used to calculate the loaded voltage gain V L /V S. 5. To demonstrate the complementary direct-coupled common emitter amplifier, connect the following circuit shown in figure 9.2: Figure 9.2 6. Repeat procedure steps 2-to-4 for the circuit of figure 9.2. 9.5 Questions 1. Calculate the theoretical quiescent values of V C1 and V C2 when V Bl = 1.5V in figure 9.1. Compare these values with those measured in procedure step 2. 2. Using the change in output voltage and the change in input voltage obtained from procedure steps 2 and 3. Calculate the overall no-load voltage gain of the circuit in figure 9.1. Compare this value to the theoretical no-load voltage gain A V, described in the discussion section. 3. Using the results of procedure step 4, calculate the loaded voltage gain of the circuit in figure 9.1. Compare this value to the theoretical loaded voltage gain, V L /V S, described in the discussion section. 4. Repeat questions 1, 2, and 3 for the complementary direct-coupled amplifier in figure 9.2. Be careful to note that the emitter resistor R E2, is at the top or the figure.

Experiment (10): 10.1 Reference DIFFERENTIAL AMPLIFIER Sections 12.2-12.4, Electronic Devices and Circuits, Differential Amplifier, Common Mode Parameters, Practical Differential Amplifiers. 10.2 Objectives 1. To investigate the differential amplifier in the difference and common modes of operation. 2. To determine the common mode rejection ratio (CMRR). 10.3 Discussion Operational amplifiers are the most widely used electronic devices for linear (non-digital) applications. The input stage to an op-amp is a differential amplifier. Most differential amplifiers are constructed as integrated circuit, but to facilitate experimentation, we will investigate a discrete version of the same circuit. Differential amplifiers can be operated in either of two manners: the input signals can be different, or the input signals can be identical. If the input signals are different, the amplifier is said to be operating in its difference mode. This means that the output voltage will be proportional to the difference in the two input signals. If the input signals are the same, or the inputs are tied together, the amplifier is said to be operating in its common mode. Figure 10.1 shows a differential amplifier with small external emitter resistors designed to compensate for any differences in the values of r e of the two transistors. The single and double-ended difference mode gains of the ideal differential amplifier are: VO1 RC Single ended AV = = V V r + R + r + R i1 i2 e1 E1 e2 E 2 Double ended A V V = V O1 i1 V V O2 i2 = r e1 + R 2R E1 C + r e2 + R E 2 The differential input resistance is: r ( ) id = β re 1 + RE1 + re 2 + RE 2 Where:

r id : is the total ac resistance between the input terminals. Figure 10.1 The following equations apply to operation of the differential amplifier in its common mode when the two input signals are equal in magnitude and phase: VO 1 VO 1 Single ended AV = = V V Double ended A V i1 V = The most important benefit of the differential amplifier in common mode operation is the elimination of noise that is present at both inputs. Ideally, any noise voltage that is present at both inputs is cancelled out by the phase inversion of the two sides of the amplifier. The common mode rejection ratio (CMRR) is a ratio of signal gain to noise gain that is, how well the amplifier amplifies the wanted signal and cancels the unwanted noise. The single ended. CMRR is a ratio of the single-ended difference mode voltage gain to the single-ended common-mode voltage gain. The double-ended CMRR is a ratio of the double-ended difference mode voltage gain to the double-ended commonmode voltage gain. Typically, the CMRR is extremely high (75 to 100dB is not uncommon). O1 V V i1 i2 O2 V = O1 V V i2 O2