Ampere Low-Side Ultrafast MOSFET and IGBTDrivers Features Built using the advantages and compatibility of CMOS and IXYS HDMOS TM processes Latch-Up Protected Over Entire Operating Range High Peak Output Current: A Peak Wide Operating Range:.5V to 35V -55 o C to 25 o C Extended Operating Temperature Standard High Capacitive Load Drive Capability: 5nF in <3ns Matched Rise And Fall Times Low Propagation Delay Time Low Output Impedance Low Supply Current Applications Driving MOSFETs and IGBTs Motor Controls Line Drivers Pulse Generators Local Power ON/OFF Switch Switch Mode Power Supplies (SMPS) DC to DC Converters General Description The IXDI/IXDN are high speed high current gate drivers specifically designed to drive the largest MOSFETs and IGBTs to their minimum switching time and maximum practical frequency limits. The IXDI/N can source and sink A of peak current, while producing voltage rise and fall times of less than 3ns, to drive the latest IXYS MOSFETs & IGBTs. The input of the driver is compatible with TTL or CMOS and is fully immune to latch up over the entire operating range. Designed with small internal delays, a patent-pending circuit virtually eliminates transistor cross conduction and current shootthrough. Improved speed and drive capabilities are further enhanced by very low, matched rise and fall times. The IXDN is configured as a non-inverting gate driver and the IXDI is an inverting gate driver. The IXDN/IXDI family are available in standard pin P-DIP (PI), 5-pin TO-22 (CI), TO-263 (YI) and thermally enhanced -pin SOIC (SI) surface-mount packages. Figure - IXDN A Non-Inverting Gate Driver Functional Block Diagram IN ANTI-CROSS CONDUCTION CIRCUIT * P N OUT * Patent Pending Copyright IXYS CORPORATION 2 DS992B(/) First Release
Figure 2 - IXDI Inverting A Gate Driver Functional Block Diagram IN ANTI-CROSS CONDUCTION CIRCUIT * P N OUT Pin Description And Configuration SYMBOL FUNCTION DESCRIPTION VCC Supply Voltage Positive power-supply voltage input. This pin provides power to the entire chip. The range for this voltage is from.5v to 35V. IN Input Input signal-ttl or CMOS compatible. OUT Output Driver Output. For application purposes, this pin is connected via an external resistor to a Gate of a MOSFET/IGBT. Ground The system ground pin. Internally connected to all circuitry, this pin provides ground reference for the entire chip. This pin should be connected to a low noise analog ground plane for optimum performance. VCC 2 3 IN NC I X D () P I PIN DIP (PI) VCC OUT OUT 7 6 5 TO22 (CI) TO263 (YI) () () ORDERING INFORMATION Part Number Package Type Temp. Range Configuration IXDNPI -Pin PDIP IXDNSI -Pin SOIC -55 C to 25 C IXDNCI 5-Pin TO-22-55 C to 25 C Non Inverting IXDNYI 5-Pin TO-263-55 C to 25 C IXDIPI -Pin PDIP IXDISI -Pin SOIC -55 C to 25 C IXDICI 5-Pin TO-22-55 C to 25 C Inverting IXDIYI 5-Pin TO-263-55 C to 25 C NOTES : Either "I" or "N"; 2: Mounting or solder tabs on all packages are connected to ground NC I NC 2 NC 3 VCC IN 5 NC X D () NC 3 VCC 2 OUT OUT 6 7 NC S I NC 9 PIN SOIC * Patent Pending 2
Absolute Maximum Ratings (Note ) Parameter Supply Voltage All Other Pins Value V -.3V to V CC +.3V Power Dissipation T CASE 25 o C: TO22 (CI), TO263 (YI)* 2.5W Power Dissipation, T AMBIENT 25 o C Pin PDIP (PI), Pin SOIC TO22 (CI) TO263 (YI) Storage Temperature Soldering Lead Temperature (s) Tab Temperature (s) 33mW 2W -55 o C to 5 o C 3 o C 26 o C Operating Ratings Parameter Value Maximum Junction Temperature 5 o C Operating Temperature Range -55 o C to 25 o C Thermal Resistance (Junction To Case) TO22 (CI) TO263 (YI), Pin SOIC (SI) K/W Thermal Resistance (Junction to Ambient) -Pin PDIP (PI) 5 K/W -Pin SOIC 2 K/W TO-22 (CI), TO-263 (YI) 62.5 K/W * Subject to internal lead current limit I DC Electrical Characteristics Unless otherwise noted, T A = 25 o C,.5V V CC 35V. All voltage measurements with respect to. Device configured as described in Test Conditions. Symbol Parameter Test Conditions Min Typ Max Units V IH High input voltage.5v V CC V 3.5 V V IL Low input voltage.5v V CC V. V V IN Input voltage range -5 V CC +.3 V I IN Input current V V IN V CC - µa V OH High output voltage V CC -.25 V V OL Low output voltage.25 V R OH Output resistance I OUT = ma, V CC = V 6 mω @ Output high R OL Output resistance I OUT = ma, V CC = V 6 mω @ Output Low I PEAK Peak output current V CC is V A I DC Continuous output current Pin Dip (PI) (Limited by pkg power dissipation) TO22 (CI), TO263 (YI) 3 A A t R Rise time () C L =5nF =V 22 27 ns t F Fall time () C L =5nF =V 2 25 ns t ONDLY On-time propagation C L =5nF =V 3 33 ns delay () t OFFDLY Off-time propagation C L =5nF =V 3 3 ns delay () V CC Power supply voltage.5 35 V I CC Power supply current V IN = 3.5V V IN = V V IN = + V CC () See Figures 3a and 3b Note : Operating the device beyond parameters with listed Absolute Maximum Ratings may cause permanent damage to the device. Typical values indicate conditions for which the device is intended to be functional, but do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD procedures when handling and assembling this component. Specifications subject to change without notice 3 3 ma µa µa
Figure 3a - Characteristics Test Diagram IXDNPI / NCI / NYI / NSI 5.V V uf 25V V IXDI 5nF V IXDN Agilent 7A Current Probe Figure 3b - Timing Diagrams Non-Inverting (IXDN) Timing Diagram 5V 9% INPUT 2.5V % V PWMIN tondly tr toffdly tf OUTPUT 9% % V Inverting (IXDI) Timing Diagram 5V 9% INPUT 2.5V % V PWMIN VCC 9% tondly tf toffdly tr OUTPUT % V
Typical Performance Characteristics Fig. Rise Time vs. Supply Voltage Fig. 5 Fall Time vs. Supply Voltage 3 3 Rise Time (ns) 2 CL=5, pf 7,5 pf Fall Time (ns) 2 CL=5, pf 7,5 pf 3,6 pf 3,6 pf 2 6 Fig. 6 Rise And Fall Times vs. Case Temperature C L = 5 nf, V cc = V 2 6 5 Fig. 7 Rise Time vs. Load Capacitance 35 3 t R V V 2V Time (ns) 25 2 5 t F Rise Time (ns) 3 2 V V 6V 5 - -2 2 6 2 Temperature ( C) Fig. Fall Time vs. Load Capacitance k 5k k 5k 2k Load Capacitance (pf) Fig. 9 Max / Min Input vs. Case Temperature V CC =V C L =5nF 3.2 Fall Time (ns) 3 2 V V 2V V 6VV Max / Min Input (V) 3. 2. 2.6 2. 2.2 2.. Minimum Input High Maximum Input Low k 5k k 5k 2k Load Capacitance (pf).6-6 - -2 2 6 Temperature ( o C) 5
Fig. Supply Current vs. Load Capacitance Fig. 2 =V Supply Current vs. Frequency =V CL= 3 nf 2 MHz MHz 5 khz khz 5 nf 5 pf 2 pf 5 khz Fig. 3 k k k Load Capacitance (pf) Supply Current vs. Load Capacitance =2V. Fig. Frequency (khz) Supply Current vs. Frequency =2V 2 MHz MHz 5 khz CL = 3 nf 5 nf 5 pf 2 pf khz 5 khz k k k Load Capacitance (pf) Fig. 5 Supply Current vs. Load Capacitance =V. Fig. 6 Frequency (khz) Supply Current vs. Frequency =V 2 MHz MHz 5 khz CL= 3 nf 5 nf 5 pf 2 pf khz 5 khz k k k Load Capacitance (pf). Frequency (khz) 6
Fig. 7 5 Propagation Delay vs. Supply Voltage C L =5nF V IN =5V@kHz 5 Fig. Propagation Delay vs. Input Voltage C L =5nF V CC =5V Propagation Delay (ns) 3 2 t OFFDLY t ONDLY Propagation Delay (ns) 3 2 t ONDLY t OFFDLY 2 6 2 6 2 Input Voltage (V) Fig. 9 5 Propagation Delay vs. Case Temperature C L = 25pF, V CC = V Fig. 2.6 Quiescent Supply Current vs. Case Temperature V CC =V V IN =5V@kHz Time (ns) 5 35 3 25 2 5 t ONDLY t OFFDLY Quiescent.5.56.5.52 - -2 2 6 2 Temperature ( C).5 - -2 2 6 Temperature ( o C) Fig. 2 P Channel Output Current vs. Case Temperature V CC =V C L =.uf Fig. 22 N Channel Output Current vs. Case Temperature V CC =V C L =.uf 6 7 P Channel Output Current (A) 5 3 N Channel Output Current (A) 6 5 2 - -2 2 6 Temperature ( o C) - -2 2 6 Temperature ( o C) 7
Fig. 23 Enable Threshold vs. Supply Voltage. Fig. 2 High State Output Resistance vs. Supply Voltage Enable Threshold (V) 2 6 2 High State Output Resistance (Ohm)..6..2 2 6 2 22 2 26. 5 2 25 Fig. 25 Low-State Output Resistance Fig. 26 vs. Supply Voltage Low-State Output Resistance (Ohms)...6..2. 5 2 25 P Channel Output Current (A) -2 - -6 - - -2 - -6 - -2-22 -2 V CC vs. P Channel Output Current C L =.uf V IN =-5V@kHz 5 2 25 Fig. 27 vs. N Channel Output Current C L =.uf V IN =-5V@kHz 2 N Channel Output Current (A) 22 2 6 2 6 2 5 2 25
Supply Bypassing, Grounding Practices and Output Lead inductance When designing a circuit to drive a high speed MOSFET utilizing the IXDN/IXDI, it is very important to observe certain design criteria in order to optimize performance of the driver. Particular attention needs to be paid to Supply Bypassing, Grounding, and minimizing the Output Lead Inductance. Say, for example, we are using the IXDN to charge a 5pF capacitive load from to 25 volts in 25ns. Using the formula: I= V C / t, where V=25V C=5pF & t=25ns we can determine that to charge 5pF to 25 volts in 25ns will take a constant current of 5A. (In reality, the charging current won t be constant, and will peak somewhere around A). SUPPLY BYPASSING In order for our design to turn the load on properly, the IXDN must be able to draw this 5A of current from the power supply in the 25ns. This means that there must be very low impedance between the driver and the power supply. The most common method of achieving this low impedance is to bypass the power supply at the driver with a capacitance value that is a magnitude larger than the load capacitance. Usually, this would be achieved by placing two different types of bypassing capacitors, with complementary impedance curves, very close to the driver itself. (These capacitors should be carefully selected, low inductance, low resistance, high-pulse currentservice capacitors). Lead lengths may radiate at high frequency due to inductance, so care should be taken to keep the lengths of the leads between these bypass capacitors and the IXDN to an absolute minimum. GROUNDING In order for the design to turn the load off properly, the IXDN must be able to drain this 5A of current into an adequate grounding system. There are three paths for returning current that need to be considered: Path # is between the IXDN and its load. Path #2 is between the IXDN and its power supply. Path #3 is between the IXDN and whatever logic is driving it. All three of these paths should be as low in resistance and inductance as possible, and thus as short as practical. In addition, every effort should be made to keep these three ground paths distinctly separate. Otherwise, the returning ground current from the load may develop a voltage that would have a detrimental effect on the logic line driving the IXDN. OUTPUT LEAD INDUCTANCE Of equal importance to Supply Bypassing and Grounding are issues related to the Output Lead Inductance. Every effort should be made to keep the leads between the driver and it s load as short and wide as possible. If the driver must be placed farther than 2 (5mm) from the load, then the output leads should be treated as transmission lines. In this case, a twisted-pair should be considered, and the return line of each twisted pair should be placed as close as possible to the ground pin of the driver, and connected directly to the ground terminal of the load. 9
-PIN DIP Case Outline (IXD_PI) -PIN SOIC Case Outline (IXD_SI) 5-Leaded TO-22 Case Outline (IXD_CI) 5-Leaded TO-263 Case Outline (IXD_YI) IXYS Corporation 35 Bassett St; Santa Clara, CA 955 Tel: -92-7; Fax: -96-67 e-mail: sales@ixys.net www.ixys.com IXYS Semiconductor GmbH Edisonstrasse5 ; D-6623; Lampertheim Tel: +9-626-53-; Fax: +9-626-53627 e-mail: marcom@ixys.de