TEGRATED CIRCUITS DIVISION 30-Ampere Low-Side Ultrafast MOSFET Drivers Features 30A Peak Source/Sink Drive Current High Operating Voltage Capability: 35V - C to +25 C Extended Operating Temperature Range Under-Voltage Lockout Protection Logic Input Withstands Negative Swing of up to 5V Fast Rise and Fall Times: < ns Low Propagation Delay Time Low A Supply Current Low Output Impedance Applications Efficient Power MOSFET and IGBT Switching Switch Mode Power Supplies Motor Controls DC to DC Converters Class-D Switching Amplifiers Pulse Transformer Driver Description The IXDD630/IXDI630/IXDN630 high-speed gate drivers are especially well suited for driving the latest IXYS power MOSFETs and IGBTs. The output can source and sink 30A of peak current while producing voltage rise and fall times of less than ns. Internal circuitry eliminates cross conduction and current "shoot-through," and the driver is virtually immune to latch up. Under-voltage lockout (UVLO) circuitry holds the output LOW until sufficient supply voltage is applied (2.5V for the versions, and 9V for the M versions). Low propagation delays and fast, matched rise and fall times make the family ideal for very high frequency and high-power applications. The IXDD630 is configured as a non-inverting driver with an enable. The IXDN630 is configured as a non-inverting driver, and the IXDI630 is configured as an inverting driver. The family is available in a 5-pin TO-2 (CI), and a 5-pin TO-263 (YI) package. Ordering Information Part Number Logic Configuration UVLO Package Type Packing Method Quantity IXDD630CI 2.5V 5-Pin TO-2 Tube 50 IXDD630MCI 9V 5-Pin TO-2 Tube 50 IXDD630YI 2.5V 5-Pin TO-263 Tube 50 IXDD630MYI EN 9V 5-Pin TO-263 Tube 50 IXDI630CI 2.5V 5-Pin TO-2 Tube 50 IXDI630MCI 9V 5-Pin TO-2 Tube 50 IXDI630YI 2.5V 5-Pin TO-263 Tube 50 IXDI630MYI 9V 5-Pin TO-263 Tube 50 IXDN630CI 2.5V 5-Pin TO-2 Tube 50 IXDN630MCI 9V 5-Pin TO-2 Tube 50 IXDN630YI 2.5V 5-Pin TO-263 Tube 50 IXDN630MYI 9V 5-Pin TO-263 Tube 50 DS--R04 www.ixysic.com
TEGRATED CIRCUITS DIVISION. Specifications.............................................................................................. 3. Lead Configurations...................................................................................... 3.2 Lead Definitions......................................................................................... 3.3 Absolute Maximum Ratings................................................................................ 3.4 Recommended Operating Conditions........................................................................ 4.5 Electrical Characteristics: T A = 25 C......................................................................... 4.6 Electrical Characteristics: T A = - C to +25 C............................................................... 5.7 Thermal Characteristics................................................................................... 5 2. Functional Description....................................................................................... 6 2. IXDD630 Block Diagram & Truth Table....................................................................... 6 2.2 IXDI630 Block Diagram & Truth Table........................................................................ 6 2.3 IXDN630 Block Diagram & Truth Table....................................................................... 6 3. Typical Performance Characteristics........................................................................... 7 4. Manufacturing Information................................................................................... 4. Moisture Sensitivity..................................................................................... 4.2 ESD Sensitivity........................................................................................ 4.3 Reflow Profile.......................................................................................... 4.4 Board Wash........................................................................................... 4.5 Mechanical Dimensions.................................................................................. 2 www.ixysic.com R04
TEGRATED CIRCUITS DIVISION Specifications. Lead Configurations.2 Lead Definitions IXDD630 CI / YI Lead Name Description EN 2 3 4 5 EN Logic Input Output Enable - Drive lead low to disable output, and force output to a high impedance state IXDI630 CI / YI Output - Sources or sinks current to turn-on or turn-off a discrete MOSFET or IGBT Inverted Output - Sources or sinks current to turn-on or turn-off a discrete MOSFET or IGBT 2 Supply Voltage - Provides power to the device NC 3 4 5 NC Ground - Common ground reference for the device Not connected IXDN630 CI / YI 2 3 4 NC 5.3 Absolute Maximum Ratings Parameter Symbol Minimum Maximum Units Supply Voltage -0.3 V Input Voltage Range V, V EN -5 +0.3 V Output Current I - ±30 A Junction Temperature T J -55 +50 C Storage Temperature T STG -65 +50 C Unless stated otherwise, absolute maximum electrical ratings are at 25 C Absolute maximum ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at conditions beyond those indicated in the operational sections of this data sheet is not implied. R04 www.ixysic.com 3
TEGRATED CIRCUITS DIVISION.4 Recommended Operating Conditions Parameter Symbol Range Units Supply Voltage UVLO to 35 V Operating Temperature Range T A - to +25 C.5 Electrical Characteristics: T A = 25 C Test Conditions: UVLO < < 35V (unless otherwise noted). Parameter Conditions Symbol Minimum Typical Maximum Units Input Voltage, High UVLO < < 8V V IH 3.5 - - Input Voltage, Low UVLO < < 8V V IL - - 0.8 V Input Current 0V < V < I - - ± A EN Input Voltage, High IXDD630 only V ENH 2/3 - - EN Input Voltage, Low IXDD630 only V ENL - - /3 Output Voltage, High - V OH -0.025 - - Output Voltage, Low - V OL - - 0.025 V V Output Resistance, High State =8V, I = -ma R OH - 0.7 0.4 Output Resistance, Low State =8V, I =ma R OL - 0.6 0.3 Output Current, Continuous Limited by package power dissipation I DC - - ±8 A Rise Time =5.6nF, =8V t r - Fall Time =5.6nF, =8V t f - 8 On-Time Propagation Delay =5.6nF, =8V t ondly - 46 65 Off-Time Propagation Delay =5.6nF, =8V t offdly - 46 65 ns Output Enable Time IXDD630 only t PZL, t PZH - 34 65 Output Disable Time IXDD630 only t PLZ, t PHZ - 65 25 Enable Pull-Up Resistor IXDD630 only R EN - 0 - k =8V, V =3.5V - 2.5 4 ma Power Supply Current =8V, V =0V I CC - - 0.75 ma =8V, V = - - 0.75 Under-Voltage Lockout Threshold Rising, M 7 9 9.9 UVLO Rising, 2.5 3.5 V Under-Voltage Lockout Hysteresis M - - - -.5 - V 4 www.ixysic.com R04
TEGRATED CIRCUITS DIVISION.6 Electrical Characteristics: T A = - C to +25 C Test Conditions: UVLO < < 35V, T J <50 C. Parameter Conditions Symbol Minimum Maximum Units Input Voltage, High UVLO < < 8V V IH 4 - Input Voltage, Low UVLO < < 8V V IL - 0.8 Output Resistance, High State =8V, I = -ma R OH - 0.6 Output Resistance, Low State =8V, I =ma R OL - 0.45 V Rise Time =5.6nF, =8V t r - 35 Fall Time =5.6nF, =8V t f - 35 On-Time Propagation Delay =5.6nF, =8V t ondly - ns Off-Time Propagation Delay =5.6nF, =8V t offdly -.7 Thermal Characteristics Package Parameter Symbol Rating Units CI (5-Lead TO-2) 36 Thermal Impedance, Junction-to-Ambient JA YI (5-Lead TO-263) 46 C/W CI (5-Lead TO-2) 3 Thermal Impedance, Junction-to-Case JC YI (5-Lead TO-263) 2 C/W R04 www.ixysic.com 5
TEGRATED CIRCUITS DIVISION 2 Functional Description 2. IXDD630 Block Diagram & Truth Table IXDD630 2.3 IXDN630 Block Diagram & Truth Table IXDN630 UVLO UVLO EN EN 0 or open 0 or open 0 0 0 0 Z 0 Z 2.2 IXDI630 Block Diagram & Truth Table IXDI630 UVLO 0 0 6 www.ixysic.com R04
TEGRATED CIRCUITS DIVISION 3 Typical Performance Characteristics Rise Time (ns) 90 80 70 50 30 0 Rise Time vs. Supply Voltage (V =0-5V, f=khz, T A =25ºC) =0nF =nf =50nF =25nF =nf 5 25 30 35 Fall Time (ns) 90 80 70 50 30 0 Fall Time vs. Supply Voltage (V =0-5V, f=khz, T A =25ºC) =0nF =nf =50nF =25nF =nf 5 25 30 35 Time (ns) 28 27 26 25 24 23 22 2 Rise & Fall Times vs. Temperature (V =0-5V, =8V, =25nF) t f t r -50-30 - 30 50 70 90 30 Rise Time (ns) 80 Rise Time vs. Load Capacitance =2V,8V,25V,30V,35V =V Fall Time (ns) 80 Fall Time vs. Load Capacitance =V =2V =8V =25V =30V =35V 0 0 50 50 0 Load Capacitance (nf) 0 0 50 50 0 Load Capacitance (nf) Propagation Delay (ns) 90 80 70 50 30 Propagation Delay vs. Supply Voltage (V =0-5V, =5.6nF, f=khz) t ondly t offdly 5 5 25 30 35 Propagation Delay (ns) 80 0 Propagation Delay vs. Input Voltage ( =25V, =5.6nF, f=khz) t offdly t ondly 0 5 5 25 30 Input Voltage (V) Propagation Delay (ns) Propagation Delay vs. Junction Temperature (V =0-5V, = 5.6nF, =8V, f=khz) 70 50 30 t ondly t offdly -50-30 - 30 50 70 90 30 Input Threshold (V) 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 Input Threshold vs. Temperature ( =8V, =5.6nF) Min V IH Max V IL.8-50 -30-30 50 70 90 30 Input Threshold (V) 4.0 3.5 3.0 2.5 Input Threshold vs. Supply Voltage Min V IH Max V IL 2.0 5 25 30 35 Enable Threshold (V) 22 8 6 4 2 8 6 Enable Thresholds vs. Supply Voltage V ENH V ENL 4 2 4 6 8 22 24 26 28 30 32 34 36 R04 www.ixysic.com 7
TEGRATED CIRCUITS DIVISION 0 Supply Current vs. Load Capacitance ( =35V) f=mhz f=500khz f=khz f=50khz f=khz 5.0 7.5.0 2.5 5.0 7.5.0 22.5 25.0 27.5 Load Capacitance (nf) 0 Supply Current vs. Load Capacitance ( =8V) f=mhz f=500khz f=khz f=50khz f=khz 5.0 7.5.0 2.5 5.0 7.5.0 22.5 25.0 27.5 Load Capacitance (nf) 0 Supply Current vs. Load Capacitance ( =2V) f=mhz f=500khz f=khz f=50khz f=khz 5000 00 5000 000 25000 Load Capacitance (pf) 0 Supply Current vs. Load Capacitance ( =V) f=mhz f=500khz f=khz f=50khz f=khz 0 0. Supply Current vs. Frequency ( =35V) =25nF =nf =5.6nF 0 0. Supply Current vs. Frequency ( =8V) =25nF =nf =5.6nF 5000 00 5000 000 25000 Load Capacitance (pf) 0.0 0 Frequency (khz) 0.0 0 Frequency (khz) 0 0. Supply Current vs. Frequency ( =2V) =25nF =nf =5.6nF 0 0. Supply Current vs. Frequency ( =V) =25nF =nf =5.6nF 3.0 2.5 2.0.5.0 0.5 Quiesent Supply Current vs. Temperature ( =8V) V =3.5V V =5V V =V V =0V & 8V 0.0 0 Frequency (khz) 0.0 0 Frequency (khz) 0.0-50 -30-30 50 70 90 30 Dynamic Supply Current vs. Temperature ( =8V, V =0-5V, f =khz, =5.6nF).4.2.0 0.8 0.6 0.4 0.2 0.0-50 -30-30 50 70 90 30 Output Source Current (A) -65 - -55-50 -45 - -35-30 -25 - -5 - Output Source Current vs. Supply Voltage (V =7V, =μf) 5 25 30 35 Output Sink Current (A) 65 55 50 45 35 30 25 5 Output Sink Current vs. Supply Voltage (V =7V, =μf) 5 25 30 35 8 www.ixysic.com R04
TEGRATED CIRCUITS DIVISION -36 Output Source Current vs. Temperature ( =8V, =μf) 36 Output Sink Current vs. Temperature ( =8V, =μf) 0.22 High-State Output Resistance vs. Supply Voltage Output Source Current (A) -34-32 -30-28 -26 Output Sink Current (A) 34 32 30 28 Output Resistance (Ω) 0. 0.8 0.6 0.4 0.2 R OH @ -ma -24-50 -30-30 50 70 90 30 26-50 -30-30 50 70 90 30 0. 5 5 25 30 35 Output Resistance (Ω) 0.22 0. 0.8 0.6 0.4 0.2 Low-State Output Resistance vs. Supply Voltage R OL @ +ma UVLO Threshold (V) 9.0 8.5 8.0 7.5 Under Voltage Lockout Threshold vs. Temperature - M Rising Falling UVLO Threshold (V) 3.0 2.5 2.0.5.0.5 Under-Voltage Lockout Threshold vs. Temperature - Rising Falling 0. 5 5 25 30 35 7.0-50 -30-30 50 70 90 30.0-50 -30-30 50 70 90 30 R04 www.ixysic.com 9
TEGRATED CIRCUITS DIVISION 4 Manufacturing Information 4. Moisture Sensitivity All plastic encapsulated semiconductor packages are susceptible to moisture ingression. IXYS Integrated Circuits Division classifies its plastic encapsulated devices for moisture sensitivity according to the latest version of the joint industry standard, IPC/JEDEC J-STD-0, in force at the time of product evaluation. We test all of our products to the maximum conditions set forth in the standard, and guarantee proper operation of our devices when handled according to the limitations and information in that standard as well as to any limitations set forth in the information or standards referenced below. Failure to adhere to the warnings or limitations as established by the listed specifications could result in reduced product performance, reduction of operable life, and/or reduction of overall reliability. This product carries a Moisture Sensitivity Level (MSL) classification as shown below, and should be handled according to the requirements of the latest version of the joint industry standard IPC/JEDEC J-STD-033. Device Moisture Sensitivity Level (MSL) Classification YI / MYI MSL 3 CI / MCI MSL 4.2 ESD Sensitivity This product is ESD Sensitive, and should be handled according to the industry standard JESD-625. 4.3 Reflow Profile Provided in the table below is the Classification Temperature (T C ) of this product and the maximum dwell time the body temperature of this device may be (T C - 5)ºC or greater. The classification temperature sets the Maximum Body Temperature allowed for this device during lead-free reflow processes. For through-hole devices, and any other processes, the guidelines of J-STD-0 must be observed. Device Classification Temperature (T C ) Dwell Time (t p ) Max Reflow Cycles YI / MYI 245 C 30 seconds 3 CI / MCI 245 C 30 seconds 4.4 Board Wash IXYS Integrated Circuits Division recommends the use of no-clean flux formulations. Board washing to reduce or remove flux residue following the solder reflow process is acceptable provided proper precautions are taken to prevent damage to the device. These precautions include but are not limited to: using a low pressure wash and providing a follow up bake cycle sufficient to remove any moisture trapped within the device due to the washing process. Due to the variability of the wash parameters used to clean the board, determination of the bake temperature and duration necessary to remove the moisture trapped within the package is the responsibility of the user (assembler). Cleaning or drying methods that employ ultrasonic energy may damage the device and should not be used. Additionally, the device must not be exposed to flux or solvents that are Chlorine- or Fluorine-based. www.ixysic.com R04
TEGRATED CIRCUITS DIVISION 4.5 Mechanical Dimensions 4.5. YI & MYI (5-Lead TO-263) H D (Note 2) Pin Indicator e ~4x A c2 E (Note 2) E E3 * C C L D2 * b ~5x D Circular feature will be present on devices with the Optional Tip Lead Form. SYMBOL A A b b c c c2 D D D2 E E E3 e H L L L3 R R θ MM CH M MAX M MAX 4.064 4.826 0. 0.90 0.000 0.254 0.000 0.0 0.508 0.99 0.0 0.039 0.508 0.889 0.0 0.035 0.38 0.737 0.05 0.029 0.38 0.584 0.05 0.023.43.65 0.045 0.065 8.382 9.652 0.330 0.380 6.858 7.700 0.270 0.303.358.562 0.053 0.062 9.652.668 0.380 0.4 6.223 8.000 0.245 0.35 5.092 6.869 0.0 0.270.702 BSC 0.067 BSC 4.5 5.875 0.575 0.625.778 2.794 0.070 0..000.676 0.039 0.066 0.254 BSC 0.0 BSC 0.4 TYP 0.08 TYP 0.506 TYP 0.02 TYP - 8º - 8º Recommended PCB Pattern 2. (0.087) 8. (0.33) 3.80 (0.50).05 (0.04).75 (0.423) 8.05 (0.37).50 (0.43) Dimensions mm (inches).702 (0.067) JEDEC TO-263 Optional Tip Lead Form PLATG (Note 3) SECTION: C-C b c BASE METAL c R R L3 θ A L R R L3 θ A L b NOTES:. Reference JEDEC TO-263 Type BA. 2. Dimension does not include mold flash; mold flash shall not exceed 0.27mm (0.005 inch) per side. 3. Minimum plating: 0 microinches. 4. Controlling dimension: millimeters. 4.5.2 CI & MCI(5-Lead TO-2) 0.27 BSC (0.005 BSC) 9.652 -.668 (0.380-0.4) A 3.8-3.8 (0.50-0.52) 0.355 M B A M B 3.556-4.826 (0. - 0.90) 0.508 -.397 (0.0-0.055) 9.652 -.668 (0.380-0.4) 2.5-3.048 (0. - 0.) 4.826-5.334 (0.90-0.2) 5.842-6.858 (0.230-0.270) 5.842-6.858 (0.230-0.270) 7.550-8. (0.297-0.39) 4.224-6.5 (0.5-0.650) 8.382-9.07 (0.330-0.355) 6.300-6.700 (0.248-0.264) 2.92-2.878 (0.480-0.507) THERMAL PAD 6.858-8.890 (0.270-0.350) 2.032-2.92 (0.080-0.5) 2.700-4.732 (0.500-0.580) C C 0.356-0.6 (0.04-0.024).702 4x BSC (0.067 4x BSC) 0.38 -.06 5x (0.05-0.0 5x) SECTION C-C 0.38 M B A M PLATG 0.38 -.06 (0.05-0.0) LEAD TIP 0.356-0.6 (0.04-0.024) BASE METAL 0.356-0.559 (0.04-0.022) Dimensions mm (inches) 0.38-0.965 (0.05-0.038) R04 www.ixysic.com
TEGRATED CIRCUITS DIVISION For additional information please visit our website at: www.ixysic.com IXYS Integrated Circuits Division makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. Neither circuit patent licenses nor indemnity are expressed or implied. Except as set forth in IXYS Integrated Circuits Division s Standard Terms and Conditions of Sale, IXYS Integrated Circuits Division assumes no liability whatsoever, and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any intellectual property right. The products described in this document are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or where malfunction of IXYS Integrated Circuits Division s product may result in direct physical harm, injury, or death to a person or severe property or environmental damage. IXYS Integrated Circuits Division reserves the right to discontinue or make changes to its products at any time without notice. Specification: DS--R04 Copyright 7, IXYS Integrated Circuits Division All rights reserved. Printed in USA. 4/5/7 2 www.ixysic.com R04