Freesale Semiondutor, n. oument Number: AN557 Appliation Note ev. 0, 0/06 Average Current Mode nterleaved PFC Control heory of operation and the Control oops design By: Petr Frgal. ntrodution Power Fator Corretion (PFC systems are used for AC/C onversion to ompensate the power fator. here are many topologies and ontrol tehniques inorporated in the PFC systems. he boost onverter is the most popular topology due to a simple ontrol of the input urrent while keeping the output voltage onstant. For medium power levels, the -phase PFC operating in the average urrent-ontrol mode is the optional solution. nreasing the output power and looking for improvement of the overall effiieny leads to the use of several onverters in a parallel onnetion. n the presented solution, there are two boost onverters onneted in parallel, feeding one C-bus iruit. he onverters are shifted by 80 to one another to redue the input urrent ripple. his topology is also alled interleaved PFC. he interleaved boost PFC onverter has several advantages over the single boost onverter, suh as inreased power density, redued EM filter due to a smaller input urrent ripple, redued apaitor MS urrent, and inreased overall effiieny. his appliation note desribes the average urrent mode interleaved PFC operation, the ontrol theory, and the Control oops design based on a small-signal system model. Contents. ntrodution.... nterleaved PFC Basis... 3. Control oops esign... 4 3.. Current-ontrol loop design... 4 3.. oltage-ontrol loop design... 8 3.3. oltage feed-forward blok design... 0 4. Conlusion... 5. eferenes... 6. evision History... 06 Freesale Semiondutor, n. All rights reserved.
nterleaved PFC Basis. nterleaved PFC Basis he interleaved PFC onsists of two boost onverters onneted in parallel. he benefit of this approah is a redued input urrent ripple, beause the indutor urrents and are shifted by 80 to one another (see Figure. Figure also shows that when the onverter is operating at 50 % of its duty yle, the input urrent ripple is eroed. he interleaved operation also dereases the output apaitor urrent ripple. hese features optimie the omponents of the design. When ompared to the single boost onverter, the PFC indutors handle half the urrent, and the C-bus apaitor, MOSFEs, and diodes are alulated for half the urrent ripple. All these advantages lead to a higher power density per watt. Furthermore, you an inrease the effiieny by disabling one leg of operation at lower power. Figure. PFC ontrol struture On the other hand, the software ontrol struture of the interleaved PFC is more ompliated (see the following figure. Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 Freesale Semiondutor, n.
nterleaved PFC Basis Figure. Control struture n the -phase interleaved PFC appliation, sense these four quantities: the input voltage in, two boost urrents pf and pf, and the output voltage out. he ontrol struture onsists of two urrent-ontrol loops, one voltage loop, the input voltage feed-forward blok, and the phase management logi. n the outer ontrol loop, ompare the atual C-bus voltage to the desired one. he ontrol error is proessed by the P (proportional-integral ontroller, whih generates the amplitude of the referene urrent. he required amplitude is multiplied (A by the referene sinewave (B, whih is derived from the shape of the input voltage. When both onverter phases run in parallel, the urrent referene for eah phase is half of the voltage ontroller output. When deriving the sinewave referene from the input voltage, add the voltage feed-forward blok (C to eliminate the input voltage variation. his blok onsists of a low-pass filter, whih alulates the average value of the input voltage. For a sinusoidal shape, the average value is realulated to the MS value, and it is used for ompensation. Compare the urrent referene to the atual urrents sensed on the shunt resistors. he urrent differene is proessed by the P ontrollers. he outputs from these ontrollers are the duty yles of the PWM Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 Freesale Semiondutor, n. 3
Control oops esign signals for the PFC MOSFE transistors. Shift the PWM signal for the seond transistor to the PWM signal of the first leg by 80. Control the input urrent to ahieve the desired input-urrent shape and the desired level of C output voltage on the C-bus apaitors. he inner urrent-ontrol loop must be fast enough to trak the urrent hanges. he maximum bandwidth of the urrent ontroller is limited by the ontroller s performane. he outer voltage loop keeps the output voltage at the required level. he MCU load required for the voltage-ontrol loop is low. Set the bandwidth of the voltage-ontrol loop below 0 H to eliminate the seond harmoni of the C-bus voltage. 3. Control oops esign he PFC Control oops design onsists of the inner urrent loop, the outer output-voltage loop, and the voltage feed-forward blok design. he design inludes a derivation of the small-signal models for the inner and outer ontrol loops, the design of onstants for the P ontrollers, and the design of a seond-order filter for the voltage feed-forward blok. his appliation note uses the so-alled analog approah for the Control oops design, where the whole design is made in the ontinuous-time domain. Finally, the ontroller parameters are saled into the disrete domain to be used by the disretied ontrollers. 3.. Current-ontrol loop design 3... Boost onverter small-signal model he design of the inner urrent-ontrol loop starts with the derivation of the transfer funtion of the inner urrent loop iruit. he inner urrent loop is represented by the boost onverter, as shown in the following figure. Using the averaging method over the swithing yle followed by a small-signal perturbation, the nonlinear iruit shown in the following figure an be simplified into the small-signal model that desribes the operation of the onverter around the steady-state operation point. he resulting transfer funtion is used as a model of the boost onverter for the design of the inner urrent-ontrol loop. Figure 3. Boost onverter shemati Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 4 Freesale Semiondutor, n.
Control oops esign he averaging over the swithing period is based on the fat that the urrent hange in an indutor or the voltage hange in a apaitor is ero over the swithing period in the steady state. herefore, the equations for the indutor urrent i and the apaitor voltage v an be written for both the ON and the OFF states of the MOSFE transistor. he subsequent summation of equations for the ON and OFF states gives these equations for the indutor urrent i and the apaitor voltage v: Eq. di dt dv dt v ( d v N Eq. C ( d i v Assuming that all variables (i, vn, v, and d onsist of steady-state values in the seleted operational point (, N,, C, and and small-signal AC variation ( î, vˆ N, and vˆ, Eq. and Eq. an be rewritten into this form: Eq. 3 i iˆ ; v vˆ ; v vˆ ; d dˆ N N d( ˆ i Eq. 4 ( ˆ ( ˆ ( ˆ N vn d v dt N d vˆ Eq. 5 C ( dˆ ( v iˆ ( ˆ ( dt Considering that the produt of two small AC signals results in an even smaller signal, these small AC signal produts are eliminated, and Eq. 4 and Eq. 5 an be rewritten as Eq. 6 and Eq. 7. Eq. 6 diˆ dt dvˆ dt vˆ N ( vˆ Eq. 7 C ( iˆ vˆ dˆ earranging the equations using aplae transformation leads to the small-signal model equations Eq. 8 and Eq. 9, and the matrix in Eq. 0. dˆ Eq. 8 s iˆ vˆ ( vˆ dˆ( s N ˆ ˆ ˆ( Eq. 9 sc v ( i d s s iˆ Eq. 0 ˆ( ˆ sc d s vn vˆ 0 Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 Freesale Semiondutor, n. 5
Control oops esign he ontrol to the input-urrent transfer funtions is obtained as: Eq. id sc ( ( s s C his transfer funtion an be further simplified using the high-frequeny approximation, in whih the apaitor is replaed by a shortut for high frequenies, and the transfer funtion in Eq. is simplified as: Eq. id s 3... nner urrent loop ontroller design his appliation note uses the so-alled analog approah to design the digital ontrol loop. his method is based on a design in a ontinuous-time domain. his method is adopted by analog engineers, but it has some drawbaks when used to design a digital ontrol loop. he digital implementation of a ontrol loop introdues transport delay, whih is not refleted in the analog design approah. t results in a ontrol loop that has worse performane than expeted. However, this issue is eliminated by onsidering this delay during the analog design of the ontrol loop. he digital implementation introdues two signifiant delays. he first delay relates to the sampling and proessing time. he seond delay relates to a digital implementation of the PWM modulator. he total transport delay is approximated by a first-order Pade polynomial: Eq. 3 s s his equation shows an example of a total delay alulation, where the indutor urrent is sampled in the middle of the PWM period, and a enter-aligned PWM is used: Eq. 4 PWM PWM he ontroller used for the ontrol loops ompensation is a well-known P ontroller desribed by Eq. 5. he P ontroller is implemented in Embedded Software ibraries (FSES and desribed in FB User s uide (doument CM4FBU. he disadvantage of the P ontroller in the AC system is the permanent traking error, whih an be eliminated by the fast urrent loop. Eq. 5 P P Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 6 Freesale Semiondutor, n. s PWM s s he whole ontrol loop is shown in Figure 4. Considering the transport delay aused by digital implementation, the performane of the analog design approah is very lose to the diret digital approah.
Control oops esign Figure 4. Current ontrol loop he first step in the urrent ontrol loop design is to write a transfer funtion for the open ontrol loop. t onsists of the transfer funtion of the P ontroller, the transfer funtion of the system, and the transport delay: Eq. 6 Open P id s s s s s he performane of the ontrol loop is defined by the ross-over frequeny and the phase margin ϕpm. Beause the ross-over frequeny diretly impats the total harmoni distortion (H of the PFC, it must be as high as possible. On the other hand, the ross-over frequeny must not be higher than 0-0 % of the ontrol-loop sampling frequeny. he phase margin impats the overshoot during the step hange at the input of the P ontroller. A good ompromise is the phase margin between 45-60. he parameters of the P ontroller are alulated using the known transfer funtion of the open loop and the rules for a stable ontrol loop. he position/frequeny of the ontroller ero is alulated as: Eq. 7 tan( ϕ pm artan( When is known, the integral gain of the P ontroller is obtained as: Eq. 8 Finally, the proportional gain of the ontroller is alulated as: Eq. 9 P he P ontroller onstants are alulated using real quantities. n a digital implementation, all quantities are saled into the range whih an be represented by the MCU. Sale the P ontroller onstants into the internal MCU representation aording to Eq. 0 and Eq.. For more details, see the FB_CtrlPpAW( funtion in FB User s uide (doument CM4FBU. Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 Freesale Semiondutor, n. 7
Control oops esign Eq. 0 P _ saled P e u max max Eq. _ saled e S u max max 3.. oltage-ontrol loop design 3... oltage-ontrol loop transfer funtion he outer voltage-ontrol loop is derived in a similar way as the urrent-ontrol loop. Figure 3 leads to these four equations: Eq. v in d Eq. 3 d N sin( t Eq. 4 i sin( t Eq. 5 i ( d i where N and are amplitudes of the input voltage and the indutor urrent. After the rearranging and mathematial manipulation, the output urrent i is expressed as: i N N os(t Eq. 6 he first term orresponds to the C part and the seond term to the AC part of i. Applying averaging and small-signal perturbation results in: Eq. 7 iˆ in iˆ vˆ Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 8 Freesale Semiondutor, n.
Control oops esign he diode urrent î is expressed aording to the type of load as: for onstant output power, or Eq. 8 Eq. 9 iˆ vˆ vˆ Cs v iˆ ˆ vˆ Cs for resistive load. For further alulation, onsider the onstant output power load. After substituting Eq. 8 into Eq. 7, Eq. 7 an be rewritten as: Eq. 30 vi vˆ iˆ whih is the final transfer funtion of the outer voltage-ontrol loop. N Cs 3... oltage loop ontroller design he voltage ontroller design proedure is very similar to the urrent ontroller design. he proessing delay in the system is not onsidered, beause the voltage loop is oversampled when ompared to the required bandwidth of the ontrol loop. he proessing delay is therefore very small and an be negleted. he voltage-ontrol loop blok diagram is shown in this figure: Figure 5. oltage loop blok diagram hen open-loop transfer funtion for Figure 5 an be written as: Eq. 3 Open P vi s s Cs he transfer funtion of the voltage open loop is expressed in Eq. 3. he performane of the ontrol loop is again defined by the ontrol loop bandwidth and phase margin ϕpm. One of the requirements for the voltage-ontrol loop is to attenuate the voltage ripple at s. herefore, the bandwidth of the ontrol loop must be very small, usually set from 0. to 0. of s. he phase margin is set lose to 90, beause the voltage overshoot of the C-bus voltage is not desired. N Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 Freesale Semiondutor, n. 9
Control oops esign When and ϕpm are defined, the P ontroller onstants are alulated as: Eq. 3 tan( ϕ pm π artan( C Eq. 33 4 Finally, the proportional gain of the ontroller is alulated as: Eq. 34 N P ( C ( he P ontroller onstants must be again saled into the internal digital representation (see Eq. 0 and Eq.. 3.3. oltage feed-forward blok design he purpose of the voltage feed-forward blok is to ompensate for the variation of input voltage in the voltage-ontrol loop. he feed-forward blok is desribed by Eq. 35, where A is the voltage ontroller output (required urrent amplitude, B is the input voltage, and C is the MS value of the input voltage. Eq. 35 he MS value of the input voltage is obtained by filtering the input voltage using Butterworth seond-order filter (n from the FSES library. he transfer funtion for the seond-order filter is expressed as: Eq. 36 H s x s AB C he filter stop frequeny SOP is set to s, where s is the main frequeny in rad/s. he filter attenuation S is hosen from the required H, for example.5 %. he ut-off frequeny is then alulated as: Eq. 37 n 0 SOP /0 s Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 0 Freesale Semiondutor, n.
eferenes Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 Freesale Semiondutor, n. he filter transfer funtion is transformed into the digital domain using bilinear transformation. he general form of a seond-order filter in the digital domain is expressed as: Eq. 38 0 ( a a b b b H For the seond-order Butterworth filter, all filter oeffiients (a, a, b0, b, and b are expressed as: Eq. 39 0 4 b Eq. 40 4 b Eq. 4 4 b Eq. 4 4 a Eq. 43 4 a Beause the filter provides an average value of filter s output, the filtered value must be multiplied by π to get the MS value of the input voltage. For more details about filter onstants alulation, see FB User's uide (doument CM4FBU. 4. Conlusion his appliation note provides guidane on designing a stable PFC ontrol system based on the boost onverter topology. his doument is aompanied by another appliation note that desribes the implementation of interleaved PFC for a speifi hardware platform (see Setion 5, eferenes. 5. eferenes FB User's uide (doument CM4FBU FB User's uide (doument CM4FBU AN PFC implementation (doument ANxxxx
evision History 6. evision History his table summaries the hanges done to this doument sine the initial release: able. evision history evision number ate Substantive hanges 0 0/06 nitial release. Average Current Mode nterleaved PFC Control, Appliation Note, ev. 0, 0/06 Freesale Semiondutor, n.
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