VLSI Testing Yield Analysis & Fault Modeling Virendra Singh Indian Institute of Science Bangalore virendra@computer.org E0 286: Test & Verification of SoC Design Lecture - 2
VLSI Chip Yield A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. Cost of a chip: Cost of fabricating and testing a wafer -------------------------------------------------------------------- Yield x Number of chip sites on the wafer Jan 18, 2008 E0-286@SERC 2
Clustered VLSI Defects Good chips Faulty chips Unclustered defects Wafer yield = 12/22 = 0.55 Defects Wafer Clustered defects (VLSI) Wafer yield = 17/22 = 0.77 Jan 18, 2008 E0-286@SERC 3
Yield Parameters Defect density (d ) = Average number of defects per unit of chip area Chip area (A) Clustering parameter (α) Negative binomial distribution of defects, p (x ) = Prob (number of defects on a chip = x ) Γ (α+x ) (Ad /α) x = -------------. ---------------------- x! Γ (α) (1+Ad /α) α+x where Γ is the gamma function α = 0, p (x ) is a delta function (maximum clustering) α =, p (x ) is Poisson distribution (no clustering) Jan 18, 2008 E0-286@SERC 4
Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / α ) α Example: Ad = 1.0, α = 0.5, Y = 0.58 Unclustered defects: α =, Y = e - Ad Example: Ad = 1.0, α =, Y = 0.37 too pessimistic! Jan 18, 2008 E0-286@SERC 5
Defect Level or Reject Ratio Defect level (DL) is the ratio of faulty chips among the chips that pass tests. DL is measured as parts per million (ppm). DL is a measure of the effectiveness of tests. DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable. Jan 18, 2008 E0-286@SERC 6
Determination of DL From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL. Jan 18, 2008 E0-286@SERC 7
Modified Yield Equation Three parameters: Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter, β Stuck-at fault coverage, T The modified yield equation: Y (T ) = (1 + TAf / β) - β Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af / β) - β Jan 18, 2008 E0-286@SERC 8
Defect Level Y (T ) - Y (1) DL (T ) = -------------------- Y (T ) ( β + TAf ) β = 1 - -------------------- ( β + Af ) β Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, β is the fault clustering parameter. Af and β are determined by test data analysis. Jan 18, 2008 E0-286@SERC 9
Yield and Fault Coverage Defect Level 30 25 20 15 10 5 0 0 10 20 30 40 50 60 70 80 90 100 Fault Coverage Jan 18, 2008 E0-286@SERC 10
Computed DL 237,700 ppm (Y = 76.23%) Defect level in ppm Stuck-at fault coverage (%) SEMATECH Chip (Courtesy: IBM) Jan 18, 2008 E0-286@SERC 11
Time to Market Revenues Loss of Revenues Time to Market ΔT Time in Months Jan 18, 2008 E0-286@SERC 12
Failure Rate Vs Product Lifetime Infant Mortality Working Life Span Wearout Failure Rate 1-20 weeks 10-20 years Product Life Time Jan 18, 2008 E0-286@SERC 13
Definitions Defect: A defect in an electronic system is the unintended difference between the implemented hardware and its intended design Error: A wrong output signal produced by defective system is called error. An error is an effect whose cause is some defect Fault: A representation of a defect at the abstracted function level is called a fault Jan 18, 2008 E0-286@SERC 14
Why Model Faults? I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) Real defects (often mechanical) too numerous and often not analyzable A fault model identifies targets for testing A fault model makes analysis possible Effectiveness measurable by experiments Jan 18, 2008 E0-286@SERC 15
Some Real Defects in Chips Processing defects Missing contact windows Parasitic transistors Oxide breakdown... Material defects Bulk defects (cracks, crystal imperfections) Surface impurities (ion migration)... Time-dependent failures Dielectric breakdown Electromigration... Packaging failures Contact degradation Seal leaks... Ref.: M. J. Howes and D. V. Morgan, Reliability and Degradation - Semiconductor Devices and Circuits, Wiley, 1981. Jan 18, 2008 E0-286@SERC 16
Electromigration (a) (b) (c) (a) Open in a line (b) Short between two lines (whisker) (c) Short between lines on different layers (hillock) Jan 18, 2008 E0-286@SERC 17
Mapping Physical Defect into Faults 1 A (a) R2 R1 RL B A Z Z B A (b) A Z Z Both the defective resistance in bipolar and a the oxide breakdown in oxide between the source and drain of the NMOS transistor form a short failure mode Both cases are mapped into a stuck-at fault Jan 18, 2008 E0-286@SERC 18
Mapping Physical Defect into Faults 2 A A Z A Z Z Poly Metal Diffusion Physical defect: A missing metal o NMOS is missing the gate Failure mode: an open Fault: open A possible circuit representation is shown Jan 18, 2008 E0-286@SERC 19
Mapping Physical Defect into Faults 3 L1 L2 L1 L2 (a) (b) Stuck-at 1 Vdd (c) GND Stuck-at 0 Bridging Fault (d) Jan 18, 2008 E0-286@SERC 20
Observed PCB Defects Defect classes Shorts Opens Missing components Wrong components Reversed components Bent leads Analog specifications Digital logic Performance (timing) Occurrence frequency (%) 51 1 6 13 6 8 5 5 5 Ref.: J. Bateson, In-Circuit Testing, Van Nostrand Reinhold, 1985. Jan 18, 2008 E0-286@SERC 21
Failure Classification IC Failures Incorrect Design Mode Duration Permanant Hard Parameter Degradation Temporaty Soft Transient Intermittent Jan 18, 2008 E0-286@SERC 22
Common Fault Models Single stuck-at faults Transistor open and short faults Memory faults PLA faults (stuck-at, cross-point, bridging) Functional faults (processors) Delay faults (transition, path) Analog faults Jan 18, 2008 E0-286@SERC 23
Single Stuck-at Fault Three properties define a single stuck-at fault Only one line is faulty The faulty line is permanently set to 0 or 1 The fault can be at an input or output of a gate Example: XOR circuit has 12 fault sites ( ) and 24 single stuck-at faults 1 0 a b c d e s-a-0 g 1 h i f k Test vector for h s-a-0 fault Faulty circuit value Good circuit value j 0(1) 1(0) Jan 18, 2008 E0-286@SERC 24 1 z