Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author
Outline Fabrication steps Transistor structures Transistor behavior NMOS PMOS Latch up Modern VLSI Design: Chap2 2 of 35
Foundry & Fab Foundry : fabrication line for hire Foundries are major sources of fab capacity today Fab : Design and fabricate Modern VLSI Design: Chap2 3 of 35
licon Lattice Semiconductor Conductivity changed by adding impurities Impurities, called dopants, create either n-type or p-type regions Transistors are built on a silicon substrate licon is a Group IV material Forms crystal lattice with bonds to four neighbors Modern VLSI Design: Chap2 4 of 35
Dopants licon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V (Arsenic, Phosphorus): h extra electron (n-type) Group III (Boron): missing electron, called hole (p-type) - + + As B - Modern VLSI Design: Chap2 5 of 35
p-n Junctions A junction between p-type and n-type semiconductor forms a diode Current flows only in one direction N-Diff P-Diff cathode anode Modern VLSI Design: Chap2 6 of 35
Fabrication processes IC built on silicon substrate: some structures diffused into substrate other structures built on top of substrate Substrate regions are doped with n-type and p-type impurities (n+ = heavily doped) Wires made of polycrystalline silicon (poly), multiple layers of aluminum (metal) licon dioxide (O 2 ) is insulator Modern VLSI Design: Chap2 7 of 35
mple cross section O 2 metal3 metal2 transistor metal1 via poly n+ p+ n+ substrate substrate Modern VLSI Design: Chap2 8 of 35
Photolithography Mask patterns are put on wafer using photosensitive material: Modern VLSI Design: Chap2 9 of 35
Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: p-tub n-tub substrate Pattern polysilicon before diffusion regions: poly p-tub gate oxide poly n-tub Modern VLSI Design: Chap2 10 of 35
Process steps, cont d Add diffusions, performing self-masking: poly poly n+ p-tub n+ p+ n-tub p+ Modern VLSI Design: Chap2 11 of 35
Process steps, cont d Start adding metal layers: metal 1 metal 1 poly vias poly n+ p-tub n+ p+ n-tub p+ Modern VLSI Design: Chap2 12 of 35
Outline Fabrication steps Transistor structures Transistor behavior NMOS PMOS Latch up Modern VLSI Design: Chap2 13 of 35
Transistor structure n-type transistor: Modern VLSI Design: Chap2 14 of 35
0.25 micron transistor (Bell Labs) gate oxide silicide source/drain poly Modern VLSI Design: Chap2 15 of 35
Transistor layout n-type (tubs may vary): L w Modern VLSI Design: Chap2 16 of 35
Basic transistor parasitics Gate to substrate, also gate to source/drain Source/drain capacitance, resistance Modern VLSI Design: Chap2 17 of 35
Basic transistor parasitics (Cont d) Gate capacitance C g Determined by active area Source/drain overlap capacitances C gs, C gd Determined by source/gate and drain/gate overlaps Independent of transistor L C gs = C ol W Drain/bulk & source/bulk capacitance Modern VLSI Design: Chap2 18 of 35
Outline Fabrication steps Transistor structures Transistor behavior NMOS PMOS Latch up Modern VLSI Design: Chap2 19 of 35
NMOS Transistor Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors O 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is no longer made of metal Source Gate Drain Polysilicon O 2 n+ n+ p bulk Modern VLSI Design: Chap2 20 of 35
NMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF Source Gate Drain Polysilicon O 2 n+ p n+ bulk S 0 D Modern VLSI Design: Chap2 21 of 35
NMOS Operation (Cont d) When the gate is at a high voltage Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON This induced channel forms a resistor (more carriers in the channel, lower the resistance) Source Gate Drain Polysilicon O 2 n+ p n+ bulk S 1 D Modern VLSI Design: Chap2 22 of 35
NMOS Operation (Cont d) Poly-oxide-silicon sandwich under the gate is a capacitor To increase voltage, need to add positive charge to poly and negative charge to silicon Initially, negative charge comes from pushing away holes After threshold voltage is reached, channel of mobile electrons formed Modern VLSI Design: Chap2 23 of 35
PMOS Transistor Channel carriers have positive charge milar, but doping and voltages reversed Body tied to high voltage (V DD ) Gate low: transistor ON Attracts holes to form a thin p-region allows holes to flow from p+ to p+ Gate high: h transistor t OFF When channel not formed, p+ regions are isolated by back-to-back diodes Bubble indicates inverted behavior Polysilicon Source Gate Drain O 2 p+ p+ n bulk Modern VLSI Design: Chap2 24 of 35
Drain current characteristics Modern VLSI Design: Chap2 25 of 35
Drain current Linear region (V ds < V gs - V t ) I d = k (W/L)[(V gs - V t )V ds - 0.5 V ds2 ] Saturation region (V ds EV gs - V t ) I d = 0.5k (W/L)(V gs - V t ) 2 Modern VLSI Design: Chap2 26 of 35
Power Supply Voltage GND = 0 V In 1980 s, VDD = 5V VDD has decreased in modern processes High VDD would damage modern tiny transistors Lower VDD saves power VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, Modern VLSI Design: Chap2 27 of 35
0.5 µm transconductances From a MOSIS process: n-type: k 2 n = 73 µa/v V tn = 0.7 V p-type: k p = 21 µa/v 2 V tp = -0.8 V Modern VLSI Design: Chap2 28 of 35
Current through a transistor 0.5 µm parameters W/L = 3/2 Measure at boundary between linear and saturation regions: V gs = 2V I d = 0.5k (W/L)(V gs -V t ) 2 = 93 µa V gs = 5V I d = 1 ma Modern VLSI Design: Chap2 29 of 35
Outline Fabrication steps Transistor structures Transistor behavior NMOS PMOS Latch up Modern VLSI Design: Chap2 30 of 35
Latch-up CMOS ICs have parastic silicon-controlled rectifiers (SCRs) When powered up SCRs can turn on Creating low-resistance path from power to ground Current can destroy chip Early CMOS problem Can be solved with proper circuit/layout structures Modern VLSI Design: Chap2 31 of 35
Parasitic SCR structure Parasitic bipolar transistors (pnp and npn) in a CMOS structure The well and substrate have resistances R W and R S, respectively Not completely isolated tubs Twin tub n tub R well V well GND A Y V DD p+ n+ n+ p+ p+ n+ V sub R sub R sub p substrate n well V well R well substrate tap V sub well tap Modern VLSI Design: Chap2 32 of 35
Parasitic SCR Two modes of operation: Both BJTs off Both BJTs saturated short circuit power supply circuit I-V behavior Modern VLSI Design: Chap2 33 of 35
Solution to latch-up Use tub ties with small resistance to connect tub to power rail n+ (heavily doped): low resistance Use enough to create low-voltage connection Modern VLSI Design: Chap2 34 of 35
Tub tie layout p+ metal (V DD ) p-tub Modern VLSI Design: Chap2 35 of 35