In this lecture: Lecture 8: ROM Programmable Logic Devices Dr Pete Sedcole Department of EE Engineering Imperial College London http://caseeicacuk/~nps/ (Floyd, 3 5, 3) (Tocci 2, 24, 25, 27, 28, 3 34) Read-only memory Implementing logic with ROM Programmable Logic Devices Implementing logic with PLDs Static hazards E2 Digital Electronics 8 7 November 28 E2 Digital Electronics 82 7 November 28 Memory terminology Memory cell: circuit that stores one bit of information yte: a group of 8 bits Word: a group of n bits (usually 8 64) Capacity: 496 2-bit words = 892 bits (written 496x2 or 4k x 2) kilo (k) = 24 = 2 Mega (M) = 2 2 Giga (G) = 2 3 Address Read operation Write operation E2 Digital Electronics 83 7 November 28 E2 Digital Electronics 84 7 November 28
Read-only Memory (ROM) A ROM cell can store one bit of information Data can be read but not changed (written) although some ROMs can be erased unlike RAM, which can be read and written ROM is non-volatile the data is kept even when the power supply to the circuit is turned off the data can be read again after the power is turned back on unlike RAM, which is volatile Applications: permanent storage of programmes for microprocessors look-up tables of data implementing combinational logic 64x bit ROM row select decoder A A A2 A3 A4 A5 A ROM device example +5 Volts IN/ of 8 8 6 24 32 4 48 56 9 7 25 33 4 49 57 2 8 26 34 42 5 58 3 9 27 35 43 5 59 4 2 2 28 36 44 52 6 5 3 2 29 37 45 53 6 6 4 22 3 38 46 54 62 7 5 23 3 39 47 55 63 MUX 7 _ } G 2 7 OUT E2 Digital Electronics 85 7 November 28 E2 Digital Electronics 86 7 November 28 64 x bit ROM example: 6 address inputs: half are used for selecting the row, and half for selecting the column the row-select decoder energises all 8 cells in one row the column-select MUX chooses just one column signal to pass through to the output column lines are normally pulled high by resistors a ROM cell programmed with a pulls the line low Storage A ROM cell or A voltage level is stored to represent a or If the row-line is addressed, the switch closes and the stored voltage appears on the column-line The switch is implemented with a transistor (typically a MOSFET) Row Column E2 Digital Electronics 87 7 November 28 E2 Digital Electronics 88 7 November 28
Mask Programmed ROM In a Mask Programmed ROM (MROM): The data to be stored in the ROM is fixed at the time of manufacture The presence or absence of a wire determines whether a cell is programmed with a or a row line 5V Programmable ROMs MROM are inflexible the data are fixed when the chips are fabricated Programmable ROMs (PROMs) can be programmed after manufacture A fuse is used instead of a wire link Certain types of fuses can be reset under UV light Electrical Erasable PROMs (EEPROMs) use another transistor instead of a fuse row line PROM cell EEPROM cell data stored in a gate capacitance stores stores column line column line E2 Digital Electronics 89 7 November 28 E2 Digital Electronics 8 7 November 28 Implementing logic with ROM Different ROM technologies A 2 n x m ROM has n inputs (the address) and m outputs Eg: 2 4 x 6 Addr[3:] 6x6 ROM Data[5:] E2 Digital Electronics 8 7 November 28 This can be used to implement logic functions directly connect the input signals to the address lines programme the ROM data with the truth table A C Z Addr (hex) Data (hex) 2 Truth ROM 3 table: contents: 4 5 6 7 E2 Digital Electronics 82 7 November 28
Programmable Logic Devices (PLDs) Several different architectures available, but we will only look at the PAL architecture PAL: Programmable Array Logic These implement SOP expressions in canonical form Typically, the SOP expressions can have between 7 to 6 product terms Construction: a programmable AND section and a fixed OR section CPLD: Complex Programmable Logic Device Larger devices containing several PALs PALs use programmable fuses or transistors similar to PROM Original devices in the 97s used fuses which could not be reset: such devices were called one-time programmable (OTP) PALs and CPLDs available today usually use reprogrammable fuses E2 Digital Electronics 83 7 November 28 E2 Digital Electronics 84 7 November 28 PAL architecture A A A2 A3 A4 A5 A6 A7 Detail of AND gates in PALs All inputs and their complements are provided To simplify the diagram, only one input line is drawn for each AND gate > f f = A A A3 + f A dot indicates an active connection A A A2 A3 A4 A5 A6 A7 f = A A A2 A4 A6+ A A3 A4 A A A2 A3 the other input connections are not shown E2 Digital Electronics 85 7 November 28 E2 Digital Electronics 86 7 November 28
Summary of combinational logic building blocks Combinational: logic output is a function of the inputs it has no memory or storage Gates seven fundamental gates from which all other circuits are made NOT, AND / NAND, OR / NOR, XOR / XNOR Multiplexers act as switches to connect one output to one of a number of input signals can also be used to implement logic functions Decoders inverted multiplexers a demultiplexer connects one input to one of a number of outputs also includes circuits such as binary to 7 segment decoders Arithmetic circuits binary adders, comparators, multipliers need to cope with negative numbers using signed number representations Programmable Logic Devices (PLDs) ROMs can implement arbitrary logic functions efficient for large combinational logic circuits PLAs (and CPLDs) implement canonical SOP oolean expressions Advantages of PLDs reduction in chip count easy to fix bugs and upgrade by reprogramming Disadvantages requires programming equipment E2 Digital Electronics 87 7 November 28 E2 Digital Electronics 88 7 November 28 Timing and glitches It takes a finite amount of time for a signal to travel through a logic gate - this is called the propagation delay of the gate This delay can cause glitches in signals Example consider this circuit which contains an inverter with a propagation delay of 2ns There will be a 2ns window where and are both A low - causing a glitch C E2 Digital Electronics 89 7 November 28 2ns Avoiding static hazards The case on the previous slide is an example of a static hazard the output of the circuit glitches when it shouldn t change in some circuits static hazards can cause malfunctions To avoid static hazards, use a Karnaugh map and add redundant groups such that all groups have some overlap A \ C Groups A and AC do not overlap, so are potential hazards Add the group C so that all groups overlap f = A + AC + C E2 Digital Electronics 82 7 November 28 f = A + AC