High Performance Lateral Schottky Collector Bipolar Transistors on SOI for VLSI Applications

High Performance Lateral Schottky Collector Bipolar Transistors on SOI for VLSI Applications A dissertation submitted in partial fulfillment of the requirement for the degree of Master of Science (Research) by Venkatesh Rao Entry No. 2000EEM004 Under the Supervision of Dr. M. Jagadesh Kumar Department of Electrical Engineering, Indian Institute of Technology, Delhi July, 2003

Certificate This is to certify that the thesis entitled "High Performance Lateral Schottky Collector Bipolar Transistors on SOI for VLSI Applications" being submitted by Venkatesh Rao (2000EEM004), for the award of degree of Master of Science (Research) in Electrical Engineering to the Indian Institute of Technology, Delhi, is a record of bonafide work done by him under my guidance and supervision. It is further certified that this work has not been submitted anywhere else for the award of degree or diploma. Date: Dr. M. Jagadesh Kumar Associate Professor Dept. of Electrical Engineering Indian Institute of Technology, Delhi

Acknowledgment I wish to express my heartfelt gratitude to my supervisor Dr. M. Jagadesh Kumar for his invaluable guidance and advice during every stage of this endeavour. I am greatly indebted to him for his continuing encouragement and support without which, it would not have been possible for me to complete this undertaking successfully. I am grateful to Prof. G. S. Visweswaran for allowing me to use the laboratory facilities at all points of time. I am thankful to Mr. K. C. Sharma and Mr. Ritesh Kumar Sharma for their valuable assistance during my project work. Sincere thanks to research scholars Alok Kanti Deb, S. D. Roy, and Y. Singh and also to research student C. Linga Reddy and M.Tech. students Dinesh Kumar Sharma and Bikash Ghose for their valuable suggestions and discussion s during the project work. Finally, I am very thankful to those who directly or indirectly assisted me in completion of this work.

Abstract Advanced bipolar transistors play a vital role in RF/Microwave applications. But they need to satisfy stringent demands on device performance parameters such as β, g m, and f T. Many of the bipolar technologies developed to meet these demands are vertical structures and suffer from many non ideal effects at high collector current densities. In the present work, to enhance the performance limits of bipolar transistors, we have proposed three types of lateral Schottky collector transistors in Silicon On Insulator (SOI) technology namely, 1) Lateral PNM Schottky Collector BJT, 2) SiGe base lateral PNM Schottky collector HBT and 3) SiC emitter lateral NPM Schottky collector transistor. To study the novel characteristics of these lateral Schottky collector bipolar transistors, we have used a state of the art two dimensional simulator. The collector base junction of the proposed lateral PNM (NPM) transistor consists of a Schottky junction between N base (P base) and metal (M). The device parameters are chosen based on experimental results for the lateral bipolar transistors. The simulated characteristics of the proposed lateral Schottky collector transistors are compared with their equivalent SOI lateral PNP (NPN) transistors. It is demonstrated that the proposed structures have superior performance in terms of reduced collector resistance, high current gain, suppressed base widening and negligible reverse recovery time compared to the compatible lateral PNP (NPN) transistors in SOI. A simple fabrication procedure is also suggested providing the incentive for experimental verification. Our simulation results suggest that the proposed structures are expected to be very useful in many of the VLSI circuit design applications such as RF/Microwave circuits, low voltage circuits, and high current driving switches because of their improved performance and compatibility with the BiCMOS technology.

Contents 1 Introduction... 1 1.1 The context... 1 1.2 Need for SOI Lateral bipolar transistors... 1 1.3 Preceding efforts... 3 1.4 Objectives of the project... 4 1.5 Organization of the thesis... 4 2 A New Lateral PNM Schottky Collector Bipolar Transistor (SCBT) on SOI for Non saturating VLSI Logic Design... 6 2.1 Introduction... 6 2.2 Device Structure and Parameters... 8 2.3 SCBT Fabrication Process...10 2.4 Base current components... 14 2.5 Static characteristics... 16 2.6 Dynamic analysis... 20 2.7 Conclusions... 24 3 Ge Implanted SiGe Base Lateral PNM Schottky Collector Bipolar Transistor on SOI for High frequency and Low voltage VLSI Applications... 25 3.1 Introduction... 25 3.2 Previous efforts... 27 3.3 Basic theory... 28 3.4 Device structure and fabrication steps... 28 3.5 Simulation results and discussion... 34

3.5.1 DC analysis... 34 3.5.2 AC analysis... 39 3.6 Conclusions... 42 4 Design and Analysis of SiC Emitter Lateral NPM Schottky Collector Bipolar Transistor on SOI for high frequency and high temperature VLSI Applications... 45 4.1 Introduction... 45 4.2 Device structure and parameters... 46 4.3 Energy Band diagram... 48 4.4 Fabrication of SiC emitter lateral NPM HBT... 50 4.5 Simulation results and discussion... 52 4.5.1 DC Characteristics... 53 4.5.2 Dynamic characteristics... 56 4.5.3 Temperature analysis... 59 4.6 Conclusions... 63 5 Conclusions... 64 Appendices... 69 References... 84 Publications from this work... 88

Chapter 1 Introduction 1.1 The Context To satisfy the continuously growing demands in the areas of RF/microwave circuits and mixed signal circuits, transistors with high current gain, high cut off frequency, and high transconductance are essential. The RF/microwave performance of high frequency transistors is limited by the parasitic RC time constants arising from the series resistances and shunting capacitances of the transistors. Control of parasitics is an important issue in the development of advanced transistors. In this context, the SOI technology has emerged as a best technology to alleviate the above problem and support the needs of VLSI applications. 1.2 Need for SOI Lateral bipolar transistors In the recent past, lateral bipolar transistors [1 8] have been implemented on SOI technology to take the full advantages related to SOI technology. Conventional vertical BJTs on bulk substrate will meet most of the performance specifications for VLSI and radio frequency applications. But 1

they require complicated fabrication processes in the case of BiCMOS integration, and the cost of technological development and manufacturing may be high. This process may be further complicated when CMOS is built on the SOI substrate. On the contrary, the present SOI lateral BJT is easily integrated with SOI CMOS. In the most simplified process, SOI BiCMOS integration would be possible by adding few masks and ion implants with minor modification of standard CMOS process. SOI BiCMOS technology for mixed signal applications has been a very attractive alternative to its bulk counterpart, since it offers the advantages such as (i) Reduced analog to digital crosstalk noise, (ii) Diminution of sensitivity to alpha particles, (iii) Reduction of substrate capacitance, (iv) Better device isolation, and (v) Gain performance in passive elements. Hence, the use of lateral BJTs in SOI BiCMOS should lead to realization of the above advantages with no added process complexity. However, the major drawbacks associated with these devices are (i) significant base widening at high collector current, (ii) large base charge storage time, (iii) lower cut off frequency, and (iv) lower current gain. The situation becomes worse in the case of PNP BJTs because of the poor hole mobility and large collector resistance. But often, it is essential to have the performance of PNP BJTs identical to that of NPN BJTs in BiCMOS applications such as push pull amplifier design and also in ECL and complementary (npn/pnp) logic design. 2

1.3 Preceding Efforts There are various techniques to improve the performance of bipolar transistors such as the application of Schottky collector [9 10], SiGe base [11 14], and SiC emitter [15 16]. The main problem associated with the above techniques is that, in most cases, they are based on the bulk technology and are vertical in structure. Though, the SiGe base HBT is playing a vital role in RF/microwave and VLSI applications, it cannot be operated at high collector current because of base widening at which the current gain and cut off frequency falls rapidly. And also it fails to provide a high performance PNP HBT because of the charge storage at base collector junction [17]. SiC emitter bipolar transistors play a significant role in high temperature and hostile environment but they also suffer from the same drawbacks at high collector current densities since the collector region is a semiconductor with finite doping. Considering the above, we propose a novel family of transistors on SOI technology to realize bipolar transistors with enhanced performance. The proposed devices integrate the advantages of lateral bipolar transistor, well established Ge implantation process, lateral epitaxial overgrowth of SiC and properties related to SOI technology. 3

1.4 Objectives of the Project The main objective of the project is therefore to propose a new family of lateral Schottky collector BJTs, namely (i) Lateral PNM Schottky collector bipolar transistor, (ii) SiGe base lateral PNM Schottky collector heterojunction bipolar transistor (HBT), and (iii) SiC emitter NPM Schottky collector bipolar transistor for RF/microwave and non saturating VLSI applications. By studying the steady state and transient characteristics over its equivalent conventional transistors, we have demonstrated the superior performance of the proposed structures over the conventional structures. Further, we have presented a simple fabrication procedure compatible with BiCMOS process with minimum number of masks. Based on the simulation results, we have shown that the proposed Schottky collector bipolar transistors are attractive for low power and high frequency BiCMOS VLSI applications. 1.5 Organisation of the thesis Chapter One: Introduction. Performance limitations of advanced BJTs, the need for lateral SOI BJTs and objectives of the project. 4

Chapter Two: A new lateral PNM Schottky collector bipolar transistor (SCBT) on SOI for non saturating VLSI logic design. This chapter explains the performance of a lateral PNM SCBT in terms of suppression of Kirk effect, reduction in collector resistance, negligible storage time and improvements in current gain and cut off frequency, compared to its equivalent lateral PNP BJT. Chapter Three: Ge implanted SiGe base lateral PNM SCBT on SOI for high frequency and low voltage VLSI applications. This chapter outlines the performance of SiGe base lateral PNM HBT in comparison to its equivalent lateral PNP HBT. It explains the advantages of using SiGe base in VLSI lateral devices and also illustrates the superiority of the PNM HBT in terms of enhanced current gain and higher cut off frequency. Chapter Four: Design and analysis of SiC emitter lateral NPM SCBT on SOI for high frequency and high temperature VLSI applications. This chapter describes the design and analysis of SiC wide band gap emitter lateral NPM SCBT and compares its performance with an equivalent lateral NPN transistor. Chapter Five: Conclusions. 5

Chapter 2 A New Lateral PNM Schottky Collector Bipolar Transistor (SCBT) on SOI for Non saturating VLSI Logic Design 2.1 Introduction Because of their well controllable characteristics, the bipolar transistors exhibit significant advantages over those of CMOS transistors in various critical applications such as the bandgap voltage references, accurate current mirrors, variable gain amplifiers and other high speed analog and mixed signal circuit designs [1]. This advantage of the BJT coupled with the inherent isolation available for the SOI devices led to the emergence of SOI based BiCMOS technologies where both BJTs and MOSFETs are fabricated on the same chip. However, to reduce the complexity of BiCMOS process, which employs expensive double polysilicon complementary technologies, and also to minimize the disadvantages associated with the conventional vertical current concept [2], lateral bipolar transistors are being studied extensively [3 8]. In many BiCMOS applications such as the push pull amplifiers, a PNP transistor with performance identical to that of an NPN transistor is 6

frequently required. But, due to the low hole mobility, PNP transistors are known for their poor speed and high collector resistance. However, it has been shown experimentally that if a metal is used for the collector, not only is the collector resistance less but also are the majority carriers collected more efficiently without the back injection of the minority carriers from the Schottky collector junction [9]. This is highly useful because it permits the design of high performance non saturating inverter logic circuits. Such Schottky collector junction transistors, based on the vertical current concept, have been demonstrated earlier for the VLSI applications [10]. However, a fascinating question that so far has not received any critical attention is the study of lateral PNM Schottky collector bipolar transistors on SOI. To the best of our knowledge such an investigation has not been reported in the literature. The objective of this chapter is therefore to present for the first time the design and characteristics of lateral PNM Schottky collector bipolar transistor (SCBT) on SOI using two dimensional simulation. The proposed lateral PNM SCBT is superior in performance compared to an equivalent lateral PNP BJT in terms of high current gain, high switching speed and the ability to operate at high collector current densities with suppressed base widening. 7

2.2 Device Structure and Parameters The top layout and the schematic cross section of the lateral PNM SCBT is shown in the Fig. 2.1 as implemented in the two dimensional device simulator ATLAS [18]. The epitaxial silicon film thickness is chosen to be 0.2 µm and the buried oxide thickness is 0.38 µm. The emitter is p + region doped at 5 x 10 19 /cm 3, the metallurgical n base width is 0.4 µm and is doped at 5 x 10 17 /cm 3. These parameters are same as those used in the lateral NPN experimental structure of [6]. The dopants of NPN transistors are complemented to make PNP transistor. Further the collector p region doping is raised to 5 x 10 17 /cm 3 so that the collector breakdown voltage (BV CEO ) of the PNP transistor is same as that of the proposed device at zero base current. The lateral PNM SCBT transistor with which we have compared our results has precisely the same parameters as that of PNP transistor except that the p type silicon region is replaced by metal. The collector region of the SCBT structure is chosen to be platinum silicide due to its pertinent barrier height of 0.85 ev with n type silicon, high conductivity and process selectivity [9]. 8

Base Emitter Collector 1µm (a) E B C 0.20µm 0.38µm P + P + 3.8µm Oxide N N 0.4µm N substrate (b) Fig. 2.1. Top layout and schematic cross section of the SCBT structure. 9

Table 1. Simulation parameters used for the PNP and PNM SCBT device. Parameters Value SOI thickness t si 0.20 µm Buried oxide thickness t box 0.38 µm Field oxide thickness t ox 0.18 µm Emitter length 3.80 µm Base length 0.40 µm Emitter region doping concentration 5x10 19 cm 3 Base region doping concentration 5x10 17 cm 3 Minority carrier lifetime (in emitter region) 2.44x10 9 s Minority carrier lifetime (in base region) 2.29x10 6 s Barrier height lowering coefficient 2.0x10 7 cm SRH concentration parameter for electrons and 1x10 22 cm 3 holes NSRHN and NSRHP 2.3 SCBT fabrication process Fig. 2.2 shows the fabrication sequence for the proposed lateral PNM SCBT [2], [6]. After mesa isolation by etching the epitaxial silicon, a thick Chemical Vapor Deposition (CVD) oxide (Low Temperature Oxidation) is deposited and patterned as shown in Fig. 2.2(a). A CVD nitride film is deposited (Fig. 2.2(b)) and an unmasked Reactive Ion Etching (RIE) is performed to retain a silicon nitride spacer at the edge of the CVD oxide (Fig. 2.2 (c)) [6]. To form the emitter region, p type dopant is implanted with a tilt angle of 15 o. If proper tilt angle is not chosen, the p + emitter will be too close 10

N Substrate Si 3 N 4 N Substrate (a) (b) P + P + N Substrate N Substrate N+ poly (e) (f) P + N Substrate (c) P + N Substrate (g) LTO P + N Substrate (d) P + N Substrate (h) Fig. 2.2. Process steps for the SCBT structure. 11

to the n + poly base contact resulting in a more recombination current between emitter and base. To avoid this problem, a proper tilt angle is chosen by performing simulations using the process simulator ATHENA [19]. Fig 2.3 shows the formation of emitter base junction for different tilt angles, keeping implantation energy (30 KeV) and implantation dose (7 x 10 14 / cm 2 ) constant. It is clear from Fig. 2.3 that as the tilt angle increases, the distance between the junction and the n + poly base contact increases. A tilt angle of about 15 o ensures that the emitter base junction is sufficiently away from the n + poly base contact. Following the p + emitter formation, a thick CVD oxide is deposited (Fig. 2.2(d)) and planarized by CMP (Chemical Mechanical Polishing) process as shown in Fig. 2.2(e). After etching the nitride film, an n + polysilicon film is deposited and the wafer is again planarized using CMP leaving n + poly in the place where the nitride film was present (Fig. 2.2(f)). Using a mask, the field oxide and the silicon are etched in the window as shown in Fig. 2.2(g). Similarly, a contact window (Fig. 2.2(h)) is now opened on top of the p + emitter using a mask. Following this, platinum silicide is deposited and patterned to form the Schottky collector contact and the emitter ohmic contact. The final structure is as shown Fig. 2.1. 12

θ θ P + N Substrate (a) P + N Substrate (c) θ θ P + N Substrate (b) P + N Substrate (d) Fig. 2.3. Formation of emitter base junction for different tilt angles. (a) Tilt angle=10 o (b) tilt angle=15 o (c) tilt angle=20 o and (d) tilt angle=25 o. 13

2.4 Base current components The general expression for the base current is given by [22] I B =I ne + I R + I BR I G I nm (2.1) where I ne = Current due to injection of minority electrons from base into the emitter I R = Current due to recombination of electrons and holes in the emitter base depletion region I BR = Current due to flow of holes in the base to replace electrons lost by recombination in the neutral base region I G = Generation current due to reverse biased collector base junction I nm =Electron current from metal into the n base due to Schottky junction. The first three terms of equation (2.1) on right hand side have the same effect as that of conventional bipolar transistors. Due to the Schottky contact at the collector base junction, there is finite electron current from metal to n base for a fixed collector reverse bias, which is flowing opposite to the base current. Hence it reduces the total base current. The behaviour of these currents can be justified from Fig. 2.4. It shows base current versus collector voltage for a constant forward bias of emitter base junction voltage of V EB =0.7 V for both PNP and SCBT structures. From the figure, it is clear that in the case of SCBT, total base current is less, indicating a finite electron current caused by the electron flow from metal to n base. 14

V EB =0.7 V Base current, I B [A] PNP BJT PNM SCBT Collector voltage, V C [V] Fig. 2.4. Base current versus collector voltage of lateral PNM SCBT and lateral PNP structures. 15

2.5 Static characteristics The Gummel plots shown in Fig. 2.5 indicate that the base current in the SCBT device is smaller than that of the PNP transistor. This is because in the case of PNM transistor, when the base collector (n M) junction is reverse biased, there is a finite electron current I nm caused by the electron flow from metal into the n base [22]. Since the electron current from emitter to base is fixed by the emitter base forward bias voltage, the electron current I nm from metal to n base flows into the base terminal [22] reducing the total base current. As a result, the current gain of the SCBT is larger than that of the PNP transistor as shown in Fig. 2.6. The simulated I V characteristics of lateral SCBT and lateral PNP transistors are shown in Fig. 2.7. As can be seen, the current voltage characteristics of the SCBT structure are superior to those of the PNP transistor in terms of reduced collector resistance. The V CE off set voltage ( 0.2V) is typical of any Schottky collector transistor [9] and should be taken into account while designing the digital logic circuits. This offset voltage arises because at lower collector voltages the metal collector base junction is forward biased resulting in a substantial injection of electrons from n base into the metal collector. The electron current, therefore flows opposite to the hole current injected from the emitter reducing the collector current to zero. However, as the reverse collector voltage increases, the forward bias on the base metal junction decreases causing an increase in the net collector current. 16

Collector and base current, I C,I B [A] 10 3 P + NM P + NP 10 5 10 7 10 9 10 11 10 13 10 15 10 17 V CB = 1V 0 0.2 0.4 0.6 0.8 1.0 1.2 Emitter base voltage, V EB [V] Fig. 2.5. Gummel plots of lateral SCBT and lateral PNP structures. 17

20 Current gain, β 16 12 8 4 P + NM P + NP 0 10 14 10 12 10 10 10 8 10 6 10 4 Collector current, I C [A] Fig. 2.6. Beta versus collector current of lateral SCBT and lateral PNP structures. 18

Collector current, I C [µa] 80 60 40 20 0 P + NM P + NP I B = 2.5µA 1.5µA 1.0µA 2.0µA I B = 0.5µA I B =0A 0 1 2 3 4 Collector voltage, V C [V] Fig. 2.7. Simulated I V characteristics of lateral SCBT and lateral PNP structures. 19

2.6 Dynamic Analysis Transient simulations are carried out to estimate the base charge storage time of the conventional PNP and PNM SCBT transistor. For the conventional PNP BJT, the excess stored charge is large due to (i) increased effective base width at high collector current densities, (ii) injection of carriers from the collector region into the base and (iii) a significant minority carrier lifetime in the collector region. Fig. 2.8 illustrates the base current, in response to a large signal applied at the base terminal. For the PNP transistor, there is a finite base charge storage time because of the above mentioned reasons. Hence the total turn off time is given by [22, 41] τ off = τ s + τ f (2.3) where τ s = storage time in s and τ f = fall time in s. However, in the case of PNM SCBT the storage time (τ s ) is approximately zero. This is due to two reasons: (i) suppressed base width widening and (ii) short minority carrier lifetime in the metal collector. Therefore, in the case of PNM SCBT the total turn off time is negligible as shown in Fig. 2.8. 20

Base current, I B [µa] 40 30 20 10 0 10 20 P + NM P + NM P + NP P + NP 0 1 2 3 4 5 6 7 8 9 Transient time, T [ x10 9 s] Fig. 2.8. Switching performance of lateral SCBT and lateral PNP structures. 21

Fig. 2.9 shows the dependence of the cut off frequency on collector current for both PNP and PNM SCBT. The behaviour of both the transistors can be understood by analyzing the expression for cut off frequency f T [23]. 1 KT + τ 2πf = C dbc (r e +r c ) + (C dbe +C dbc ) (2.4) f T I C where C dbe is base emitter depletion layer capacitance in F, C dbc is base collector depletion layer capacitance in F, r e is emitter series resistance, r c is collector series resistance, and τ F is forward transit time in s and is given by τ f = t E + t B + t BE + t BC (2.5) where t E is emitter delay time in s, t B is base transit time in s, t BE is base emitter depletion layer transit time in s, and t BC is base collector depletion transit time in s. Among these, the base transit time t B is dominant at higher collector current and is expressed as W 2 B t B = 2D (2.6) pb where W B is effective base width in cm and D pb is hole diffusion coefficient in the base region in cm 2 /s. For the conventional PNP transistors, t B is dominant at very large collector currents due to the displacement of the effective base collector boundary into the collector region caused by the Kirk effect. As a result, there 22

Cutoff frequency, f T [Ghz] 2.0 1.6 1.2 0.8 0.4 V CB = 1V P + NM P + NP 0 10 12 10 10 10 8 10 6 10 4 Collector current, I C [A] Fig. 2.9. Cutoff frequency versus collector current of lateral SCBT and lateral PNP structures. 23

is a rapid fall in the cut off frequency at large collector currents. However, in the case of PNM SCBT, the absence of base widening permits cut off frequency to be high even at high collector currents. At I C =10 4 A, the cut off frequency of the SCBT is 2 GH Z, while the comparable lateral PNP transistor has a negligible cut off frequency at this current. 2.8 Conclusions The concept of the lateral SCBT structure on SOI has been successfully demonstrated using two dimensional simulation. The proposed SCBT is shown to be superior to that of the conventional lateral PNP transistor on SOI in terms of improved current gain, suppressed base widening and fast switching response. A simple fabrication procedure is also discussed. If this structure is implemented in the design of bipolar logic circuits, a significant performance leverage can be expected. However, it may be pointed out that the current gain of the proposed structure is less than 20 and is not suitable for most applications. In the following chapter, we examine the use of SiGe base to enhance the current gain of PNM transistors. 24

Chapter 3 Ge implanted SiGe Base Lateral PNM SCBT on SOI for High frequency and Low voltage VLSI Applications 3.1 Introduction SiGe HBTs are playing a vital role in many applications, which require stringent demand on device performance parameters (β, g m, and f T ) compared to silicon BJT. They satisfy the requirements of RF circuits (LNAs, PAs, mixers, modulators, VCOs, etc), mixed signal circuits (fractional N synthesizers and analog to digital converters) and in the precision analog circuits (Op Amps, band gap references, temperature bias control and current mirrors) by offering high speed (f T, f max ), high current gain, better linearity and most importantly minimum noise figure [11 13]. Further, band gap engineering of SiGe facilitates in reducing forward voltage drop of the emitter base junction by uniform grading at the emitter base junction without affecting the other parameters [14] which makes it a best candidate for low voltage applications in wireless phones and other low power battery operated products. In addition to allowing very complex custom designs, high speed and high breakdown voltage SiGe heterojunction bipolar transistors (HBTs) can be merged with high density CMOS using a mixed signal ASIC 25

methodology or other CMOS macros such as micro controllers and embedded SRAM. The primary motivation for a SiGe based HBT technology is the ability to merge the high performance SiGe HBT with standard CMOS technology giving rise to a high performance SiGe BiCMOS process without compromising the performance of either the HBT or the CMOS device. The combination of SiGe HBTs with scaled BiCMOS to form SiGe HBT BiCMOS technology presents an exciting possibility for system on chip (SoC) solutions. Further, the use of SiGe devices allows many new functions to be added onto the silicon chip thus potentially reducing cost and power and increasing speed and yield. Ge ion implantation into silicon has been successfully demonstrated to form SiGe [24 25]. But, it is difficult to obtain shallow junctions with sharp impurity profiles in vertical structures. However, recently it has been shown that this technique can be attractive for lateral SOI HBT [26]. The main requirement for the analog and mixed signal circuit designer is to have high speed and high current driving PNP bipolar transistor comparable to that of NPN transistor in applications such as complementary (npn/pnp) bipolar technology and particularly in push pull amplifier designs. The PNP transistor limits the maximum performance of the circuit since PNP transistors have poor current gain and high collector resistance due to the low hole mobility. 26

3.2 Previous Efforts To improve the performance of the PNP transistors few techniques have been suggested in the literature such as, Schottky collector (PNM) transistors [9] and SiGe base PNP heterojunction bipolar transistors (HBTs). But these are vertical structures and require complex processing for integrating with CMOS technology. Further, in the case of SiGe base PNP HBT, a careful optimization of Ge profile at the collector base junction is essential to reduce the valance band offset for the holes [14]. A lateral PNM Schottky collector transistor as explained in chapter 2 exhibits a better performance compared to that of the lateral PNP BJT. However, the application of SiGe to the base region of a lateral PNM Schottky collector transistor has not been reported in literature so far. The main objective of this chapter is therefore to explore the performance of a SiGe base lateral PNM Schottky collector transistor on SOI technology. We demonstrate using two dimensional simulation [18] that a lateral PNM HBT using SiGe base exhibits excellent characteristics over the conventional equivalent lateral PNP HBT in terms of high current gain, complete elimination of Kirk effect, approximately zero storage time, high cut off frequency, and better transfer characteristics. Finally a possible fabrication methodology compatible to BiCMOS technology is discussed in this chapter. 27

3.3 Basic Theory The Fig. 3.1 shows the energy band diagram of lateral PNM transistor with and without SiGe base. It indicates that the inclusion of uniform Ge in the base region gives rise to two effects. First, it reduces the potential barrier for the holes at the emitter base junction. The reduced potential barrier gives rise to a higher injection of carriers from emitter to base, which produces an exponentially enhanced collector current for a constant emitter base voltage drop. Hence, SiGe base heterojunction bipolar transistor has a higher current gain compared to that of a conventional PNM transistor. Second, it decreases the forward voltage drop of the emitter base junction, which makes the device more attractive for low voltage applications. 3.4 Device Structure and Fabrication Steps The top and cross sectional views of the lateral SiGe base PNM transistor implemented in the two dimensional device simulator ATLAS [18] are shown in Fig. 3.2. The fabrication steps for the lateral SiGe base PNM transistors on SOI are shown in Fig. 3.3 using a similar procedure as described in chapter 2 for the lateral PNM BJT on SOI. We start with an SOI wafer having a 0.2 µm n 28

Table 2. Simulation parameters used for the PNP and PNM HBT devices. Parameters Value SOI thickness t si 0.20 µm Buried oxide thickness t box 0.38 µm Field oxide thickness t ox 0.18 µm Emitter length 3.80 µm Base length 0.40 µm Emitter region doping concentration 5x10 19 cm 3 Base region doping concentration 5x10 17 cm 3 Minority carrier lifetime (in emitter region) 2.44x10 9 s Minority carrier lifetime (in base region) 1.0x10 7 s Barrier height lowering coefficient 2.0x10 7 cm SRH concentration parameter for electrons and 1x10 22 cm 3 holes NSRHN and NSRHP E C q V n q Φ B n E V q V p S ig e B a s e S i B a s e F ig. 3. 1. C o m p a r i s o n o f e n e r g y b a n d d ia g r a m o f a l a t e r a l P N M t r a n s i s to r w it h a n d w it h o u t S i G e b a s e. 29

type epitaxial layer with N D =5 x 10 17 cm 3 on a 0.38 µm buried oxide. After mesa isolation, a thick CVD oxide is deposited and patterned as shown in Fig. 3.3(a). Following this, a nitride film is deposited [Fig. 3.3(b)] and an unmasked RIE etch is performed retaining the nitride spacer at the vertical edge of thick CVD oxide [Fig. 3.3(c)] [6]. Next, the p + emitter (N A =5 x 10 19 cm 3 ) is formed by implanting boron at a wafer tilt angle of 15 o with an implantation energy of 30 KeV at a dose of 7 x 10 14 cm 2. As verified by the process simulator ATHENA [19], the above tilt angle will ensure that there is no short between the p + emitter region and the n + poly base contact [6]. Next, a thick CVD oxide is deposited [Fig. 3.3(d)], surface planarization is done using CMP and the nitride spacer is etched to create a window in the oxide as shown in Fig. 3.3(e). Germanium can now be implanted through this window to convert the silicon in the base region to SiGe. While SiGe regions in BiCMOS technology can be formed by epitaxy, Ge ion implantation into silicon has also been successfully demonstrated to form SiGe layers [24 25, 27 28]. It has been reported [24] that this implantation can be performed at an energy of 130 KeV and fluences of 1, 2, or 3 x 10 16 cm 2. To re crystallize the implanted SiGe layer, rapid thermal annealing (RTA) is performed at 1000 o C for 10 s. This process will ensure complete re crystallization of SiGe amorphous layer [24]. We have assumed the Ge composition in the silicon base to be 20% which is the maximum limit in most practical applications [ 29 30]. 30

Base Emitter Collector 1µm (a) E B C 0.20µm 0.38µm P + P + 3.8µm Oxide N N 0.4µm N substrate (b) Fig. 3.2. The top and cross sectional views of the lateral PNM SiGe base transistor. 31

After depositing in situ n + poly into the implanted window, the wafer is once again planarized using CMP leaving n + poly in the place where the nitride film was present [Fig. 3.3(f)]. The base contact is obtained using this n + poly. A contact window is now opened, by etching the oxide and the silicon, for the Schottky metal collector as shown in Fig. 3.3(g). Using another mask, the p + emitter contact window is opened by etching the field oxide. Following this, platinum silicide is deposited and patterned to form the Schottky collector contact and ohmic contacts on the emitter and n + poly base region. The final structure is as shown in Fig. 3.2(b). The barrier height for platinum silicide and n SiGe base junction is taken to be Φ Bn =0.82 V based on experimental results reported in literature [31]. The platinum silicide is chosen because of the better process selectivity and low resistivity. The lateral SiGe base PNP HBT, which has been used for the comparison purpose, has exactly the same dimensions and impurity concentrations as that of the proposed structure except that the collector doping of lateral SiGe base PNP HBT is chosen to be 9 x 10 17 cm 3 so that both the devices have approximately identical collector breakdown voltage BV CEO for zero base current. 32

N Substrate Si 3 N 4 N Substrate (a) (b) P + P + N Substrate N Substrate N+ poly (e) (f) P + N Substrate (c) P + N Substrate (g) LTO P + N Substrate (d) P + N Substrate (h) Fig. 3.3. Fabrication steps for the SiGe base lateral PNM transistor on SOI. 33

3.5 Simulation Results and Discussion To understand the DC and transient characteristics of the proposed lateral SiGe base PNM HBT, we have used the two dimensional simulator ATLAS [18]. Drift diffusion calculations are carried out using appropriate physical models. The concentration dependent mobility, field dependent mobility, and Klassens mobility models are used and the band gap narrowing effect is taken into account. Carrier statistics are performed by defining Fermi Dirac distribution and minority carrier lifetime including the effect of Shockley Read Hall and Auger recombination mechanisms. To account for the Schottky junction property, the standard thermionic emission model is used incorporating the effect of image force barrier lowering phenomenon [18]. 3.5.1 DC Analysis The output current voltage characteristics of the lateral SiGe base PNM transistor are compared in Fig. 3.4 with that of the lateral SiGe base PNP HBT. It can clearly be seen from Fig. 3.4 that current driving capability, output conductance, and transconductance of the proposed structure are significantly larger compared to that of the lateral SiGe PNP transistor. It may be pointed out that the PNM structure exhibits a finite off set voltage of V CE = 0.2 V which is common to any Schottky collector transistor [9] and should be considered while designing the digital logic circuits. 34

Fig. 3.5 shows the Gummel plot of both the lateral SiGe base PNM and lateral SiGe base PNP HBT for a fixed collector base voltage (V CB = 1V). We observe that the SiGe base PNM structure exhibits a lower base current than that of the PNP HBT due to a finite electron current caused by the electron flow from metal into the n base when the Schottky collector junction is reverse biased. It is also seen that the collector current of the PNM HBT is more than that of the PNP HBT even at high level injection of carriers clearly proving the absence of Kirk effect [20]. However, in the case of PNP HBT, the rapid increase in the base current at forward voltage V EB > 0.8 V indicates the presence of strong base widening. At high level injection, the base current rises to maintain charge neutrality in the widened base region. This forces the base terminal to supply additional electrons leading to an increase in base current. Since the series collector resistance is governed by the doping concentration and carrier mobility in the drift region, the PNM structure has a low resistivity since its collector is a metal as compared to the p type drift collector region of the PNP HBT. This makes the Schottky collector structure immune to the base widening even at high collector currents. Fig. 3.6 shows the current gain as a function of collector current for lateral SiGe base PNM transistor and lateral PNP transistor with SiGe base. It is important to note that the current gain of the lateral SiGe base PNM HBT is significantly large compared to any lateral PNM or PNP transistor reported so far in literature. 35

Collector current, I C [µa] 16 14 12 10 8 6 4 2 0 P + NM HBT P + NP HBT I B = 5 na Step I B =0 A 0 0.5 1.0 1.5 2.0 2.5 Collector voltage, V C [V] Fig. 3.4. Output characteristics of lateral SiGe base PNM transistor compared with that of the lateral SiGe Base PNP transistor. 36

Collector and base current, I C, I B [A] 10 3 10 5 10 7 10 9 10 11 10 13 10 15 0 V CB = 1V P + NM HBT P + NP HBT 0.2 0.4 0.6 0.8 1.0 1.2 Emitter base voltage, V EB [V] Fig. 3.5. Gummel plots of lateral SiGe base PNM transistor compared with that of the lateral SiGe base PNP transistor. 37

600 V CB = 1V Current gain, β 500 400 300 200 P + NM HBT 100 0 P + NP HBT 10 13 10 11 10 9 10 7 10 5 10 3 Collector current, I C [A] Fig. 3.6. Current gain of lateral SiGe base PNM transistor compared with that of the lateral SiGe base PNP transistor. 38

3.5.2 AC Analysis The simulated unity current gain cut off frequency f T vs collector current for both the lateral SiGe base PNM transistor and lateral SiGe base PNP HBT is presented in Fig. 3.7. The lateral SiGe base PNM HBT exhibits a higher cut off frequency, since it offers least collector resistance and also has higher transconductance g m compared to the lateral SiGe base PNP HBT. At a collector current of 0.2 ma, the f T is observed to be 4.5 GHz for the proposed structure while for the comparable lateral SiGe base PNP HBT, f T decreases sharply at this current due to the decrease in transconductance and also increased base charge storage time at high level injection [17]. The transient behaviour for lateral PNM transistor with SiGe base and lateral PNP transistor with and without SiGe base is shown in Fig. 3.8 and it is clear that the lateral SiGe base PNM transistor has approximately zero base charge storage time because of the absence of base widening and a negligible minority carrier lifetime in the metal collector region. However, the lateral PNP HBT has a higher base charge storage time not only due to the presence of the above effects but also due to the pile up of electrons at the collector base junction hetero interface at high level injection [17]. Such a carrier pile up does not seem to be present either in the case of lateral SiGe base PNM structure or the lateral PNP transistor without the SiGe base. Fig. 3.9 shows the simulated voltage transfer characteristics of the inverter using the lateral SiGe base PNM transistor and the lateral SiGe base 39

4 V CB = 1V Cutoff frequency, f T [GHz] 3 2 1 P + NM HBT P + NP HBT 0 10 9 10 8 10 7 10 6 10 5 10 4 10 3 Collector current, I C [A] Fig. 3.7. Unity gain cutoff frequency of lateral SiGe base PNM transistor compared with that of the lateral SiGe base PNP transistor. 40

Base current, I B [µa] 40 30 20 10 0 P + NM HBT P + NP HBT P + NP BJT 10 0 2 4 6 8 10 12 14 Transient time, T [x10 9 s] Fig. 3.8. Transient characteristics of lateral SiGe base PNM transistor compared with that of the lateral PNP transistor with and without SiGe base. 41

PNP HBT. As the input voltage increases from 0 to 2 V, the output voltage remains constant at 1.9 V until the input voltage reaches 0.7 V. Subsequently, the output voltage decreases rapidly until the input voltage is 0.8 V. After this point, the output voltage remains constant at 0.2 V. As can be seen the performance of the inverter formed using the lateral SiGe base PNM transistor is much superior since the transition region has a sharper transition and the ON voltage is also small compared to the inverter formed using the lateral SiGe base PNP HBT. 3.6 Conclusions In this work, for the first time, we have reported a lateral SiGe base PNM bipolar transistor on SOI suitable for non saturating VLSI logic design. A comprehensive comparison of the steady state and transient behaviour of lateral SiGe base PNM and PNP hetero junction bipolar transistors has been explored successfully using two dimensional simulation. Based on our simulation results, we demonstrate that the proposed lateral SiGe base PNM HBT exhibits excellent characteristics in terms of enhanced current gain, higher cut off frequency and fast switching response. Further a simple fabrication procedure compatible with BiCMOS process is also discussed with minimum number of masks. The proposed structure may be attractive for low power and high frequency BiCMOS VLSI applications because of the least 42

Output voltage, V O [V] 2.0 1.5 1.0 0.5 P + NM HBT P + NP HBT 0 0 0.50 1.0 1.5 2.0 Input voltage, V I [V] Fig. 3.9. Voltage transfer characteristics of the inverter using the lateral SiGe base PNM transistor and the lateral SiGe base PNP HBT. 43

reverse recovery time which results in not only a faster response but also negligible power dissipation during switching transitions thus minimizing the power delay product. While the work described in this chapter attempts to enhance the performance of PNP transistors by utilizing the SiGe base and Schottky collector, it may well be pointed out that even the NPN transistors are not free from high current effects and base storage problems. In the next chapter, we examine if the performance of NPN transistors can be enhanced using a SiC emitter and a Schottky collector junction. 44

Chapter 4 Design and Analysis of SiC Emitter Lateral NPM SCBT on SOI for High frequency and High temperature VLSI Applications 4.1 Introduction Silicon Carbide (SiC) has become a very important material in the recent past because of its high thermal conductivity, high saturated electron drift velocity, high cut off frequency, and ability to operate in hostile and high temperature environments [32 34]. Moreover, the fabrication compatibility with silicon not only reduces the cost but also increases the yield. These inherent properties of SiC make the device attractive for military applications, in intelligent control systems and in satellite applications, where silicon based device ceases to operate due to dramatic changes in electrical characteristics. The above advantages of SiC coupled with the advent of high quality local epitaxy and lateral epitaxial overgrowth of SiC [35 38], opened up new opportunities for the device designers to use the SiC as emitter of the BJT to improve the device performance through bandgap engineering mechanism. The SiC emitter HBTs [15 16], which have been reported in the literature are vertical in structure and are based on the bulk technology. Hence, they did not 45

gain much popularity for VLSI applications. To take the full advantages related to SOI technology and lateral Schottky collector transistor along with the bandgap engineering mechanism of the SiC emitter, for the first time, we propose a new SiC emitter lateral NPM Schottky collector bipolar transistor to obtain improved electrical characteristics without sacrificing the lithographic limits. The main objective of this chapter is to propose a SiC emitter lateral Schottky collector bipolar transistor on SOI technology, using a two dimensional device simulator ATLAS [18]. Based on the simulation results, we demonstrate that the performance of a SiC emitter lateral NPM HBT exhibits better electrical characteristics in terms of high current gain, high cut off frequency, complete elimination of Kirk effect, and approximately zero base storage time, over its equivalent SiC emitter lateral NPN HBT and lateral NPN BJT. In the following sections, the steady state, dynamic and transfer characteristics and a possible fabrication process compatible with BiCMOS technology are presented. 4.2 Device Structure and Parameters Fig. 4.1 shows the top and cross sectional view of the wide bandgap SiC emitter lateral NPM Schottky collector bipolar transistor, which has been implemented in the two dimensional device simulator ATLAS. The emitter length is 3.8 µm with doping equal to 5 x 10 19 cm 3 and the base length is 0.4 46

Base Emitter Collector 1µm (a) E B C 0.20µm 0.38µm N P + 3.8µm PN Oxide 0.4µm N substrate (b) Fig. 4.1 SiC Emitter Lateral NPM HBT implemented in this investigation. (a) Top layout and (b) its cross sectional view. 47

µm with p type doping equal to 5 x 10 17 cm 3. The SOI thickness is chosen to be 0.2 µm and buried oxide thickness is 0.38 µm. These parameters are exactly same as that of the SOI lateral NPN BJT device structure as reported in [6], except the inclusion of SiC emitter region. The emitter region is a wide bandgap SiC n type material that can be formed by well established deposition processes [35 38]. The base contact is obtained using the P + poly deposited on the p type silicon base region. The Schottky contact is taken at the right edge of the base that acts as a metal collector. Aluminum is chosen as the metal collector since it gives a barrier height of 0.91 ev as reported in literature [39] based on experimental results. Aluminum also offers a high conductivity and better process selectivity. The SiC emitter lateral NPN HBT and lateral NPN BJT, which have been used for comparison, have exactly the same dimensions and impurity concentrations as that of the SiC emitter lateral NPM HBT except that the collector doping of lateral NPN HBT and lateral NPN BJT is chosen to be 3 x 10 17 cm 3 so that all the devices have identical collector breakdown voltage BV CEO for zero base current. 4.3 Energy Band diagram Fig. 4.2 shows the simulated energy band diagram of SiC emitter lateral NPM Schottky collector bipolar transistor. It is clear from the figure that, due to the application of wide bandgap emitter material, there is a large potential barrier for the minority carriers (holes) from the base to emitter and 48

small potential barrier for the electrons from emitter to base. Hence, an enhanced current gain is expected for wide bandgap emitter NPM Schottky collector transistor compared to that of conventional lateral NPN BJT. E C qv n E g =1.1 ev qφ ΒP E g = 3.2 ev qv p E V Fig. 4.2 Energy band diagram of a SiC emitter NPM HBT at thermal equilibrium condition. 49

4.4 Fabrication of SiC Emitter Lateral NPM HBT The fabrication process of a SiC emitter lateral NPM HBT is similar to the fabrication of SOI lateral PNM SCBT as explained in chapter 2, with a little modification. The modification involves epitaxial growth of the SiC emitter region. This process can be implemented at the initial stage of the SOI PNM BJT fabrication as follows. We can begin with an SOI wafer having an epitaxial layer of thickness 0.2 µm and doping of 5 x 10 17 cm 3. After mesa isolation, a thick CVD oxide is deposited and patterned as shown in Fig. 4.3(a). We then deposit the in situ n + SiC on the vertical edge (at point X in Fig. 4.3(b)) of the silicon surface which acts as a seed and the SiC grows laterally [35 38] as shown in Fig. 4.3(b). After performing the CMP, we deposit a thick CVD oxide and pattern it as shown in Fig. 4.3(c). Following this, a nitride film is deposited [Fig. 4.3(d)] and an unmasked RIE etch is performed until the planar silicon nitride is etched retaining the nitride spacer at the vertical edge of thick CVD oxide [Fig. 4.3(e)]. Following this, a thick CVD oxide is deposited [Fig. 4.3(f)] and CMP process is carried out to planarize the surface. Selective etching is used to remove the nitride spacer, which will create a window in the oxide as shown in Fig. 4.3(g). After depositing in situ p + poly into the opened window, the wafer is once again planarized using CMP leaving p + poly in the place where the nitride film was present [Fig. 4.3(h)]. Now a mask is used for etching both the field oxide and the silicon film to open a contact window for the Schottky metal collector 50

LTO P Substrate (a) N P Substrate (f) SiC X P Substrate (b) N P Substrate (g) N + poly N P Substrate (c) N P Substrate (h) Si 3 N 4 N P Substrate (d) N P Substrate (i) N P Substrate (e) N P Substrate (j) Fig. 4.3. Process flow for a lateral SiC emitter NPM HBT. 51

as shown in Fig. 4.3(i). Using another mask, the n + emitter contact window is opened by etching the field oxide [Fig. 4.3(j)]. Following this, aluminum is deposited and patterned to form the Schottky collector contact and ohmic contacts on the emitter and p + poly base region. The final structure is as shown in Fig. 4.1(b). 4.5 Simulation Results and Discussion To investigate and predict the theoretical performance of SiC emitter lateral NPM transistor, a physically based numerical device simulator ATLAS [18] is employed. It calculates the electrical characteristics, which are associated with specified physical structures and bias conditions. It provides the internal device mechanism or device behaviour by solving the well established drift diffusion transport equations. To perform this, we used the appropriate physical models such as concentration dependent mobility, field dependent mobility, and Klassens mobility models and the bandgap narrowing effect is also taken into account. The Fermi Dirac distribution is defined to calculate the carrier statistics and Shockley Read Hall and Auger recombination mechanisms are also invoked in the simulation. The incomplete ionisation model is included to consider the deep donor (E D ) and deep acceptor (E A ) levels in SiC emitter [40]. To account for the Schottky junction property, the standard thermionic emission model is specified integrating the effect of image force barrier lowering phenomenon [18]. The SiC material 52