K.Diwakar et al. / Iteratioal Joural of Egieerig ad echology (IJE Delta- Sigma Mulator based Discrete Data Multiplier with Digital Output K.Diwakar #,.ioth Kumar *2, B.Aitha #3, K.Kalaiarasa #4 # Departmet of Electroics ad ommuicatio Egieerig * Departmet of Electroics ad Istrumetatio Egieerig el ech Dr.RR & Dr.SR echical Uiversity heai, Idia drdiwakar@veltechuiv.edu.i 2 viothkumarv@veltechuiv.edu.i 3 aitha.a.b@gmail.com 4 kalaiarasak9@gmail.com Abstract I the proposed multiplier cofiguratio, a ew techique is proposed for multiplicatio of two sampled aalog sigals ad the put is i digital form. Oe aalog sigal is fed to the iput of first delta-sigma mulator (DSM after samplig. he sampled put of the sec aalog sigal is egated or ot egated depedig o the bit state at the put of DSM ad is fed to the iput of sec DSM(DSM2.he resultig bit stream at the put of DSM2 is the digital represetatio of the pruct of the sampled data of the two aalog sigals. I. INRODUION he sec order, sigle stage, discrete, sigle bit quatizer ad uity feedback gai Delta-Sigma Mulator (DSM [],[2] is show i Fig. (, ad is a typical DSM where x aalog is the aalog iput sigal. he Sample ad Hold (S/H circuit over samples the iput sigal at a samplig peri (update peri U. he DSM circuit is operated by the clock with peri ( << U. x(i is the sampled aalog iput sigal to the DSM circuit durig the i th samplig peri. x(i,j, x2(i,j, z(i,j ad e(i,j represets the first itegrator put, sec itegrator put, quatizer put ad quatizer error sigal i i th samplig peri ad durig j th clock peri. he average values of the puts of the first itegrator, sec itegrator, quatizer ad error sigal durig i th update peri are deoted as x(i, x2(i, z(i ad e(i respectively. he block D is the delay uit of oe clock peri. he ormalized iput sigal durig the i th update peri, xor(i, is the ratio of x(i to the feedback gai. Fig.. Schematic diagram of typical sec order DSM. For a typical DSM with uity feedback gai, z(i is equal to x(idurig the i th update peri. he subscript i is dropped i the figures ad i further discussio. If the quatizer put is + S the the rage of x aalog is 0.7 S < x aalog < +0.7 S. Iput sigal depedat feedback gai ad iput sigal depedat operatig peri is used i DSM, to make the DSM more stable for exteded rage of iput ad suitable for idustrial applicatios [3]. I the patets [4] ad [5] ad i the papers [6] ad [9], the accuracy of, aalog multipliers which use differet techiques, is limited by the tolerace of the aalog compoets. I [4] a aalog multiplier which comprises a pair of differetial cells, each cell comprisig a pair of bipolar trasistors with coupled emitters is preseted for very low supply voltage with less distortio at the put of multiplier. I [5] is discussed a aalog multiplier which has MOS iput stage which provides go liearity rage for the multiplier. I [6] is proposed a four quadrat MOS multiplier i which the put voltage swigs with liearity of less tha %. he dyamic rages of the two iput sigals are 72% ad 48% of supply voltage, + 2.5. I [7] are compared eight categories of trascuctace multipliers. he best liearity of the eight categories of multipliers is ab 0.5%. he low cost precisio multiplier which is supplied by Aalog Devices has maximum four quadrat accuracy of 2% of full scale [8]. ISSN : 0975-4024 ol 7 No Feb-Mar 205 7
K.Diwakar et al. / Iteratioal Joural of Egieerig ad echology (IJE he aalog multiplier which is proposed i [9] is used for power ad eergy measuremet ad the power is measured with a accuracy of ±0.25%. I [0] is proposed cmos four quadrat aalog multiplier which gives better badwidth ad less power dissipatio but accuracy is ot improved. I [] is proposed aalog multiplier usig operatioal amplifiers ad the liearity error i the multiplier is 0.09%. Zhagcai Huag et. al. proposed a four quadrat MOS multiplier i which the put voltage swigs with liearity less tha %. he dyamic rages of the two iput sigals are 72% ad 48% of supply voltage [2]. Dei M. et. al. proposed Gilbert like MOS multiplier based o liear curret divider i which the distortio is less tha % [3]. Ha G. et. al. proposed eight categories of tras-cuctace multipliers ad compared. he best liearity of the eight categories of multipliers is ab 0.5% [4]. I the case of proposed DSM based multiplier, two DSMs workig with same clock frequecy multiply the two aalog iput sigals ad the result is i digital form. he tolerace requiremets of aalog compoets i the DSMs are relaxed. he cost paid for high accuracy is faster operatio ad is feasible as o-chip LSI implemetatio techology advaces. he proposed multiplier is DSM based four-quadrat multiplier with ew techique. It has maximum accuracy of ±0.0344% of FS for low frequecy sigals whe the samplig peri of aalog sigals is 0.0sec ad the DSMs operatig clock peri is 0.μsec. he maximum value of the iput sigal ca be icreased to ±70% of feedback gai. he proposed multiplier has better accuracy ad wider iput rage compared to the covetioal MOS multipliers. he major advatage is that it multiplies two low frequecy aalog sigals ad provides digital put directly which is useful for power electroics applicatios like motor cotrol usig Ss. I this paper, the proposed low cost four quadrat multiplier uses a ew techique usig basically two typical DSMs, a switch ad a NO circuit. he stadard available MOS operatioal amplifiers specificatio with D gai (A 00/m, badwidth 0MHz, iput offset voltage 20μ ad supply voltage + 2.5 is cosidered for op-amps i this proposal. With cosidered specificatio of the MOS op-amp., the proposed multiplier has maximum overall accuracy of + 0.46% of FS (full scale of supply voltage for low frequecy sigals. he maximum value of the iput voltages ca be + 70% of the supply voltage because oly dc sigals are fed to DSMs. he iput voltages of DSMs are restricted to 70% due to stability reasos. If + 2.5 is the supply voltage of the operatioal amplifiers used i the circuit the the iput sigals ca rage from -.75 to +.75 with feedback gai costat equal to 2.5. he proposed multiplier has better accuracy ad wider iput rage compared to the covetioal MOS multipliers. II. PROPOSED MULIPLIER ONFIGURAION he details of proposed multiplier icludig the block diagram, relatio betwee iputs ad put, accuracy of ivertig amplifier, implemetatio of o-ity factors ad the advatages are preseted i this sectio iverter circuit ad the specificatio of op-amp which is used i the circuits. A. Block Diagram of Proposed Multiplier I this multiplier cofiguratio a ew techique is proposed for multiplicatio of two sampled discrete aalog sigals ad the put is i digital form. Oe aalog sigal is fed to the iput of first DSM (DSM after samplig. he sampled put of the sec aalog sigal is egated or ot egated depedig o the bit state at the put of DSM ad is fed to the iput of sec DSM (DSM2. he resultig bit stream at the put of sec DSM is the digital represetatio of the pruct of the two aalog sigals. he block diagram of the proposed multiplier is show i Fig.2. he sample ad hold circuit S/H samples the iput sigal x aalog at a samplig peri U. he sampled aalog iput sigal x is fed to the iput of DSM. he DSMcircuit is operatig with the clock of peri ( U >>. he SR flip-flop is reset (phase Ф off durig each positive trasitio of the clock sigal. he put of the sigle bit quatizer, Q is i state or i 0 state. Whe the quatizer put is i state, SR flip-flop is set (phase Φ o. he S/H2 circuit samples the iput sigal y aalog at a samplig peri U. he DSM2 circuit is also operatig with the clock of peri. he sampled aalog iput sigal y is fed to the iput of DSM2 durig phase Φ o. he variable y is egated ad fed to DSM2 durig phase Ф off. ISSN : 0975-4024 ol 7 No Feb-Mar 205 8
K.Diwakar et al. / Iteratioal Joural of Egieerig ad echology (IJE Fig. 2. Proposed Multiplier of ofiguratio Durig each samplig peri, the bit stream at the put of quatizer Q 2, gives the digital represetatio of the pruct of sampled iput sigals. he average value of the bit stream at the put durig each samplig x y peri (z gives the aalog value of the pruct of ormalized samples of iput sigals. herefore, the xy ormalized value of z (z is equal to the ormalized pruct of iput sigals. he resolutio of DSM put Δz is give by, Δ z U. However, Δz is limited by the realizatio of iverter circuit ad the specificatio of op-amp which is used i the circuits. B. Relatio betwee Iputs ad Output Let x,y be the samples fed to DSM ad DSM2 respectively i i th samplig peri. If b, b 2.b are the stream of puts of DSM durig i th samplig peri, the the average aalog iput to DSM2 durig U is give by y ( b + b2 +... + b where ( b + b2 +... + b is the ormalized value of the iput of U U DSM ad is equal to x/. herefore, y( b + b2 +... + b U x y ( he average value of bit stream at the put of DSM2, z is equal to the ormalized value of iput. herefore, x z y From equatio (2, it ca be stated that the average value of the digital put of the multiplier is equal to the pruct of the ormalized samples of iput sigals.. Accuracy of Ivertig Amplifier he closed loop gai of the covetioal ivertig amplifier is give by, A i R R f i + A R + R f i where R i ad R f are the iput resistor ad feedback resistor respectively. A is the ope loop differetial voltage gai of the operatioal amplifier. For uity gai ivertig amplifier R f ad R i should be equal. Substitutig R f R i i equatio (3, the closed loop gai of the uity gai ivertig amplifier is give by, (2 (3 ISSN : 0975-4024 ol 7 No Feb-Mar 205 9
K.Diwakar et al. / Iteratioal Joural of Egieerig ad echology (IJE A i 2 + A If i (, the represets the mulus of actual value obtaied from the circuit. he equatio (4 ca be rewritte as ( (5 2 + A he accuracy, γ is give by, ( ( ( 2 + A γ..(6 Usig equatios (5 ad (6 2 % A γ 00 2 + A If A 00/m, the the accuracy of iverter circuit is approximately 0.002%. D. Implemetatio of No-Ideality Factors i Simulatio o be more practical, A is cosidered to be 70 db ad the offset voltage is cosidered to be 5m. With A 70dB, the accuracy of iverter circuit is 0.6m. osiderig the resolutio as 5m, if U 0.0sec ad 0 the from equatio Δ, ca take a miimum value of 5μsec By selectig the resolutio more z U tha the specified iput offset voltage there will ot be ay error due to the offset voltage i the iverter circuit. Substitutig A 360 (70dB i equatio (8, 0.99937 (..(8 herefore, the error due to the fiite gai of the op-amp, which is used i the ivertig amplifier, is icluded i the MALAB mel by isertig a gai elemet k of value 0.99937 after iverter block. he error due to the fiite gai of operatioal amplifiers used i S/H ad S/H2 ad also the error due to the gai mismatch are cosidered. Nowadays, the best accuracy of S/H is ab 4 bits. If the gai of S/H is +a the the gai of S/H2 is -a where a is the accuracy error ad is equal to. 2 4 herefore, x + 4 x aa log.00006xaa log (9 2 y y 2 4 aa log 0.999939 yaa log (0 he error due to the fiite gai of the op-amp, which is used i S/H ad S/H2 circuits, is icluded i the MALAB mel by isertig, gai elemet k2 of value.00006 after S/H block ad gai elemet k3 of value 0.999939 after S/H2 block. he accuracy requiremets of aalog compoets used i DSM are relaxed due to faster operatio ad correctio through feedback. III. SIMULAION RESULS OF PROPOSED MUL2 he proposed DSM based multiplier is simulated with U 0.0 sec ad 0.μsec with citios (with icludig o-ity factors. I Fig.3, the first waveform shows the sie sigal of peak amplitude 7 ad frequecy Hz (x which is the multiplicad sigal. he sec waveform of Fig.3 shows the (4 (7 ISSN : 0975-4024 ol 7 No Feb-Mar 205 20
K.Diwakar et al. / Iteratioal Joural of Egieerig ad echology (IJE sie sigal of peak amplitude 7 ad frequecy 0. Hz (y which is the multiplier sigal. he pruct (ormalized to FS of the two aalog sigals ad the average value (ormalized to FS of the bit stream at the put of the proposed multiplier i each samplig peri are show i the waveforms (c ad (d. It ca be see from (d that the ormalized aalog sigal at the put of the proposed multiplier closely follows the ormalized pruct value. he waveform (c shows the ormalized pruct value after a delay of U. he error sigal ((c-(d is show i the waveform (e. he absolute maximum value of the error sigal is 0.344m (0.0344%. Fig. 3. Ideal Fuctioig of Proposed MUL2. (Horizotal axis-ime i sec, ertical axis- oltage i olts, U 0.0 sec, 0.μsec ad 0 Fig. 4. Ideal Fuctioig of Proposed MUL2. (Horizotal axis-ime i sec, ertical axis- oltage i olts, U 0.0 sec, 0.μsec ad 0 ISSN : 0975-4024 ol 7 No Feb-Mar 205 2
K.Diwakar et al. / Iteratioal Joural of Egieerig ad echology (IJE he proposed DSM based multiplier is simulated with U 0.0 sec ad 5μsec with o-ity parameters which are detailed i sectio.2.4. ad the puts are show i Fig.4. he absolute maximum value of the error sigal is 5m (0.05% as show i the waveform (e. he accuracy takig ito accout the o-ity factors is better tha the existig multipliers. I. ONLUSION wo sec order DSMs are used for multiplicatio of two sampled aalog sigals ad the result is i digital form. For cosidered two low frequecy aalog sigals, the maximum overall accuracy is ±0.03% of FS. he dyamic rage of both iput sigals are 90% of supply voltage. he proposed multiplier has better accuracy ad dyamic rage compared to covetioal MOS multipliers ad additioally it multiplies two aalog sigals ad provides directly digital put useful for idustrial electroics applicatios like motor cotrol usig switchig coverter REFERENES [] Norsworthy S. R., Schreier R. ad emes G.. (997 Delta-Sigma Data overters, heory, Desig ad Simulatio New York, IEEE Press. [2] Schreier R., emes G..(2005 Uderstadig Delta-Sigma Data overters IEEE Press. [3] Diwakar K, Sethilpari, Ajay KS. Highly stable delta-sigma mulator for idustrial applicatios. IEIE Electro Express 2008; 5(5: 530-536. [4] Pisati,., azzaiga, M., eca, A.: US2006706300 (2006. [5] Doig, G., Schmal J.: US2004680240 (2004. [6] Zhagcai H, Yasuaki I, Hog Y, et al. A wide dyamic rage fourquadrat MOS aalog multiplier usig active feedback. IEEE Asia Pacific of ircuits ad Syst 2006; 708-7. [7] Ha G, Siecio ES. MOS trascuctace multiplier: A tutorial. IEEE ra ircuits Sys II 998; 45(2: 550-563. [8] isit http://www.aalog.com/e/other/aalog-multipliersdividers/ad633/pructs/pruct.html [9] Embedded Power ad Eergy Measuremet System Based o a Aalog Multiplier IEEE rasactios o Istrumetatio as measuremet, ol.62, No.8, August 203 [0] achai Riewruja ad Apiai Rerkrat Aalog Multiplier usig operatioal amplifiers Idia Joural of pure ad Applied Physics ol.48, Jauary 200, pp. 67-70. [] Zhagcai Huag, Yasuaki Ioue, Hog Yu ad Qua Zhag A Wide Dyamic Rage Four-Quadrat MOS aalog Multiplier Usig Active Feedback, IEEE Asia Pacific oferece o ircuits ad Systems, APAS, pp. 708-7,2006 [2] Zhagcai Huag, Yasuaki Ioue, Hog Yu ad Qua Zhag A Wide Dyamic Rage Four-Quadrat MOS aalog Multiplier Usig Active Feedback, IEEE Asia Pacific oferece o ircuits ad Systems, APAS, pp. 708-7,2006. [3] Dei M, Nizza N, Lazzerii G.M. ad Bruschi P. A four quadrat aalog multiplier based o a oval MOS liear curret divider Research i Microelectroics ad Electroics, pp.28-3,2009. [4] Ha G ad Siecio E.S. MOS trascuctace multiplier: a tutorial IEEE ra. o circuits ad systems-ii, ol. 45, No. 2, pp. 550-563,998. ISSN : 0975-4024 ol 7 No Feb-Mar 205 22