Coupled symbolic-numerical model reduction using the hierarchical structure of nonlinear electrical circuits

Similar documents
Structure-exploiting symbolic-numerical model reduction of nonlinear electrical circuits

PV-PPV: Parameter Variability Aware, Automatically Extracted, Nonlinear Time-Shifted Oscillator Macromodels

INF4420 Switched capacitor circuits Outline

INF4420. Switched capacitor circuits. Spring Jørgen Andreas Michaelsen

EE 330 Laboratory 8 Discrete Semiconductor Amplifiers

EE 330 Laboratory 8 Discrete Semiconductor Amplifiers

Assoc. Prof. Dr. Burak Kelleci

Fundamentals of RF Design RF Back to Basics 2015

DAV Institute of Engineering & Technology Department of ECE. Course Outcomes

CHAPTER 3 CUK CONVERTER BASED MPPT SYSTEM USING ADAPTIVE PAO ALGORITHM

Homework Assignment 03

A Matlab / Simulink Based Tool for Power Electronic Circuits

55:041 Electronic Circuits The University of Iowa Fall Exam 3. Question 1 Unless stated otherwise, each question below is 1 point.

A SIGNAL DRIVEN LARGE MOS-CAPACITOR CIRCUIT SIMULATOR

Behavioral Simulator of Analog-to-Digital Converters

EE301 Electronics I , Fall

Computer Controlled Curve Tracer

Homework Assignment 06

Operational Amplifier as A Black Box

Tuesday, March 29th, 9:15 11:30

Hot Topics and Cool Ideas in Scaled CMOS Analog Design

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

The Evolution of Waveform Relaxation for Circuit and Electromagnetic Solvers

EE 230 Lab Lab 9. Prior to Lab

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

444 Index. F Fermi potential, 146 FGMOS transistor, 20 23, 57, 83, 84, 98, 205, 208, 213, 215, 216, 241, 242, 251, 280, 311, 318, 332, 354, 407

Op-Amp Simulation Part II

Electronic Devices. Floyd. Chapter 9. Ninth Edition. Electronic Devices, 9th edition Thomas L. Floyd

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

! Review: MOS IV Curves and Switch Model. ! MOS Device Layout. ! Inverter Layout. ! Gate Layout and Stick Diagrams. ! Design Rules. !

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

SCHMITT TRIGGER. Typical ``real world'' signals consist of a superposition of a ``noise'' signal and a

Analysis and Design of Autonomous Microwave Circuits

An Oscillator is a circuit which produces a periodic waveform at its output with only the dc supply voltage at the input. The output voltage can be

CHAPTER 7 HARDWARE IMPLEMENTATION

Lecture 300 Low Voltage Op Amps (3/28/10) Page 300-1

Appendix. RF Transient Simulator. Page 1

Chapter 9: Operational Amplifiers

Reduction of Multiple Subsystems

Wire Layer Geometry Optimization using Stochastic Wire Sampling

Nonlinear dynamics for signal identification T. L. Carroll Naval Research Lab

Jack Keil Wolf Lecture. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. MOSFET N-Type, P-Type.

Introduction (concepts and definitions)

On Chip Active Decoupling Capacitors for Supply Noise Reduction for Power Gating and Dynamic Dual Vdd Circuits in Digital VLSI

Control of Power Converters for Distributed Generation

Other Effects in PLLs. Behzad Razavi Electrical Engineering Department University of California, Los Angeles

12-Bit Successive-Approximation Integrated Circuit ADC ADADC80

CMOS analog amplier design problem: choose transistor dimensions, bias currents, component values critical part of mixed-mode (digital-analog) ICs for

Tuesday, February 1st, 9:15 12:00. Snorre Aunet Nanoelectronics group Department of Informatics University of Oslo

Basic Operational Amplifier Circuits

Homework Assignment 07

High Accuracy 8-Pin Instrumentation Amplifier AMP02

Analog and Telecommunication Electronics

Analog Synthesizer: Functional Description

Noise Constraint Driven Placement for Mixed Signal Designs. William Kao and Wenkung Chu October 20, 2003 CAS IEEE SCV Meeting

Integrated Circuit Design for High-Speed Frequency Synthesis

An Analog Phase-Locked Loop

Experiment 9. PID Controller

International Journal of Modern Engineering and Research Technology

P a g e 1. Introduction

Spurious and Stability Analysis under Large-Signal Conditions using your Vector Network Analyser

SHF Communication Technologies AG

CHAPTER 6 INPUT VOLATGE REGULATION AND EXPERIMENTAL INVESTIGATION OF NON-LINEAR DYNAMICS IN PV SYSTEM

Chapter 4: Differential Amplifiers

INF4420. Outline. Switched capacitor circuits. Switched capacitor introduction. MOSFET as an analog switch 1 / 26 2 / 26.

Design and Implementation of Current-Mode Multiplier/Divider Circuits in Analog Processing

Time Domain Reflectometer Example

1.3 Mixed-Signal Systems: The 555 Timer

DISCRETE DIFFERENTIAL AMPLIFIER

ECEN620: Network Theory Broadband Circuit Design Fall 2012

PROCESS-VOLTAGE-TEMPERATURE (PVT) VARIATIONS AND STATIC TIMING ANALYSIS

Interface Electronic Circuits

Four-Channel Sample-and-Hold Amplifier AD684

INTEGRATED CIRCUITS. AN145 NE5517/A transconductance amplifier applications Dec

Lecture 6. Angle Modulation and Demodulation

Operational Amplifiers

CHAPTER 5 CONTROL SYSTEM DESIGN FOR UPFC

ETIN25 Analogue IC Design. Laboratory Manual Lab 2

Matched Monolithic Quad Transistor MAT04

12-Bit Successive-Approximation Integrated Circuit A/D Converter AD ADC80

CHAPTER 1 INTRODUCTION

Intelligent Systems Group Department of Electronics. An Evolvable, Field-Programmable Full Custom Analogue Transistor Array (FPTA)

Common Reference Example

Adaptive Flux-Weakening Controller for IPMSM Drives

Amplification. Objective. Equipment List. Introduction. The objective of this lab is to demonstrate the basic characteristics an Op amplifier.

Phase Locked Loops, Report Writing, Layout Tuesday, April 5th, 9:15 11:00

BANGLADESH UNIVERSITY OF ENGINEERING & TECHNOLOGY

High-level synthesis of analog sensor interface front-ends

CMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits

UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE Department of Electrical and Computer Engineering

Radivoje Đurić, 2015, Analogna Integrisana Kola 1

Design of a Folded Cascode Operational Amplifier in a 1.2 Micron Silicon-Carbide CMOS Process

Agilent Technologies Gli analizzatori di reti della serie-x

Basic Electronics Learning by doing Prof. T.S. Natarajan Department of Physics Indian Institute of Technology, Madras

EECS 427 Lecture 21: Design for Test (DFT) Reminders

LM13600 Dual Operational Transconductance Amplifiers with Linearizing Diodes and Buffers

Chapter 13: Comparators

Kent Bertilsson Muhammad Amir Yousaf

WHITE PAPER CIRCUIT LEVEL AGING SIMULATIONS PREDICT THE LONG-TERM BEHAVIOR OF ICS

CHAPTER 4 MIXED-SIGNAL DESIGN OF NEUROHARDWARE

Transcription:

Coupled symbolic-numerical model reduction using the hierarchical structure of nonlinear electrical circuits Model Reduction for Complex Dynamical Systems (ModRed ( 2010) TU Berlin, Berlin, Germany, December 2-4, 2010 Oliver Schmidt Patrick Lang Slide 1

Outline Introduction Hierarchical Modelling and Model Reduction Implementations and Applications Slide 2

Outline Introduction and Foundations Analysis and Reduction Methods Symbolic Techniques Hierarchical Modelling and Model Reduction Implementations and Applications Slide 3

Analysis and Reduction Methods numerical techniques parameters given as numerical values applicable to very large systems no qualitative insights symbolic techniques symbolic parameters not for too large circuits (complexity) analytical description of functional relations and dependences (qualitative insights) helpful in early stages of design process Slide 4

Symbolic Techniques original DAE reference solution reduced DAE original reduced error functione error bound ε numerical analysisa DAE F R R 1 R 2 R k DAE G y F = A( F, u ) E( y, y ) < ε F G y G = A( G, u ) Slide 5

Symbolic Techniques algebraic manipulations x = f ( y) 0= g( x, y) term cancellations F j : N i= 1 t ( x) = 0 i ( f ( y y) 0= g ), N Gj : t ( x ɶ ) = 0 i k i= 1 original reduced Slide 6

Outline Introduction and Foundations Hierarchical Modelling and Model Reduction Hierarchical Modelling Hierarchical Model Reduction Algorithm Subsystem Reduction Subsystem Sensitivities Subsystem Ranking Implementations and Applications Slide 7

SyreNe Subproject 5 original DAE reduced DAE original reduced numerical efficiency applicability to large systems analytical insights parameterized behavioral models coupling Slide 8

Hierarchical Structure system level f i Phase comparator Loop filter F(s) A=1 VCO block level f o IN + - VDD VSS OUT transistor level level of components hierarchical layout Drain SiO 2 Gate Metal Source different subsystems, coupled by an interconnecting structure P N Bulk P Slide 9

Hierarchical Reduction idea: exploitation of hierarchy reduce subsystems separately replace subsystems by reduced models advantages faster processing of smaller problems coupling of different techniques recursive approach possible level concept larger nonlinear circuits processable entire system 1 1 1 1 2 2 2 2 f ( x, y, z ) = 0 f ( x, y, z ) = 0 f 3 f ( x 0 3 ( x, y 3 1, z, y 3 1, x 2, y 2, x, y, x ) = 0 f 3 3 4, y 4 ( x 4 4 ) = 0 subsystem 1 subsystem 2 subsystem 3 subsystem 4 netlist based DAE PDE, y 4, z 4 ) = 0 Slide 10

Hierarchical Reduction Algorithm summary choose reduction methods for separated subsystems compute several reduced models for each subsystem compute subsystem sensitivities hierarchical reduction by means of subsystem ranking and suitable replacements guaranteed accuracy by checking the accumulated error after each replacement Slide 11

Subsystem Reduction Workflow simulate subsystem in test bench (a), record voltage potentials at subsystem terminals connect subsystem terminals to voltage sources (b) d sub- system a setup of describing system of equations and reduction (c) sub- system test bench removal of sources yields reduced subsystem (d) c sub- system b Slide 12

Subsystem Sensitivities relation between errors of subsystem and entire system not available determine degree of reduction of subsystems by influence on entire system simulate original system replace Ti by reduced system Ti,k simulate perturbed entire system compute error on output of entire system T3... T3,1 T3,m entire system T1 T2 T3 T4 entire system T1 T2 T3,k T4 Slide 13

Subsystem Sensitivities Definition Definition Subsystem Sensitivity electrical circuit entire system T1 T2 T3 T4 reduction information, e.g. or =r3k(t (T3) T3,k 3,k=r =r3k error function sensitivity of : entire system T1 T2 T3,k T4 Slide 14

Subsystem Ranking for each subsystem order the entries of the sensitivity vector increasingly w.r.t. the error in each step of the hierarchical reduction take the minimum of all first entries in the ordered sensitivity vectors replace the respective subsystem by the corresponding model check the accumulated error Slide 15

Subsystem Ranking entire system T1 T2 T3 T4 Slide 16

Subsystem Ranking entire system T1 T2 T3 T4 Slide 17

Subsystem Ranking entire system T1 T2 T3 T4 Slide 18

Subsystem Ranking entire system T1 T2 T3 T4 Slide 19

Subsystem Ranking entire system T1 T2 T3 T4 Slide 20

Subsystem Ranking entire system T1 T2 T3 T4 Slide 21

Subsystem Ranking entire system T1 T2 T3 T4 Slide 22

Subsystem Ranking entire system T1 T2 T3 T4 Slide 23

Subsystem Ranking entire system T1 T2 T3 T4 Slide 24

Subsystem Ranking entire system T1 T2 T3 T4 Slide 25

Subsystem Ranking entire system T1 T2 T3 T4 Slide 26

Subsystem Ranking entire system T1 T2 T3 T4 Slide 27

Subsystem Ranking entire system T1 T2 T3 T4 Slide 28

Subsystem Ranking entire system T1 T2 T3 T4 Slide 29

Subsystem Ranking entire system T1 T2 T3 T4 Slide 30

Subsystem Ranking entire system T1 T2 T3 T4 Slide 31

Subsystem Ranking entire system T1 T2 T3 T4 etc. Slide 32

Outline Introduction and Foundations Hierarchical Modelling and Model Reduction Implementations and Applications Implementations Hierarchical Reduction of a Differential Amplifier Hierarchical Reduction of an Operationial Amplifier Slide 33

Implementations hierarchical reduction algorithm has been implemented in ReduceSubcircuits computation of reduced subsystem models yields entire system with all reduced subsystem models appended (advantage: possibility for easy switching among different reduced models) SensitivityAnalysis computes sensitivities of each subsystem returns sensitivity vectors with entries ordered increasingly w.r.t. the error HierarchicalReduction computes ranking in accordance with the subsystem sensitivities and performs subsystem replacements in the corresponding order yields hierarchically reduced entire system with all reduced subsystem models appended Slide 34

Example Differential Amplifier differential amplifier specification discretized PDE transmission line models (20 line segments each) sine wave excitation: 2 V, 100 khz full system: 167 eq., 645 terms non-hierarchical symbolic reduction (2h 11min) 3% error: 124 eq., 416 terms 12 V -12 V Slide 35

Example Differential Amplifier differential amplifier specification discretized PDE transmission line models (20 line segments each) sine wave excitation: 2 V, 100 khz full system: 167 eq., 645 terms non-hierarchical symbolic reduction (2h 11min) 3% error: 124 eq., 416 terms 10% error: 44 eq., 284 terms 12 V -12 V Slide 36

Example Differential Amplifier differential amplifier specification discretized PDE transmission line models (20 line segments each) sine wave excitation: 2 V, 100 khz full system: 167 eq., 645 terms non-hierarchical symbolic reduction (2h 11min) 3% error: 124 eq., 416 terms 10% error: 44 eq., 284 terms 12 V -12 V L8 L1 L9 DUT2 DUT Slide 37

Example Differential Amplifier differential amplifier specification discretized PDE transmission line models (20 line segments each) sine wave excitation: 2 V, 100 khz full system: 167 eq., 645 terms non-hierarchical symbolic reduction (2h 11min) 3% error: 124 eq., 416 terms 10% error: 44 eq., 284 terms hierarchical coupled symbolicnumerical reduction (4min 50sec) 3% error: 62 eq., 315 terms 12 V -12 V L8 L1 L9 DUT2 DUT Slide 38

Example Differential Amplifier differential amplifier specification discretized PDE transmission line models (20 line segments each) sine wave excitation: 2 V, 100 khz full system: 167 eq., 645 terms non-hierarchical symbolic reduction (2h 11min) 3% error: 124 eq., 416 terms 10% error: 44 eq., 284 terms hierarchical coupled symbolicnumerical reduction (4min 50sec) 3% error: 62 eq., 315 terms 10% error: 60 eq., 249 terms 12 V -12 V L8 L1 L9 DUT2 DUT Slide 39

Example Differential Amplifier differential amplifier 12 V specification L8 discretized PDE transmission line models (20 line segments each) sine wave excitation: 2 V, 100 khz L1 DUT2 cooperation with SyreNe-SP3, TU Berlin (T. Stykel, A. Steinbrecher) reduction of L1 using PABTEC (BT), reduction of L8, L9 using Arnoldi, symbolic reduction of DUT, DUT2-12 V L9 DUT full system: 191 eq., 695 terms hierarchically reduced system: time cost: 8min 20sec 3% error: 96 eq., 2114 terms Slide 40

Example Differential Amplifier differential amplifier 12 V specification L8 discretized PDE transmission line models (20 line segments each) sine wave excitation: 2 V, 100 khz L1 DUT2 cooperation with SyreNe-SP3, TU Berlin (T. Stykel, A. Steinbrecher) reduction of L1 using PABTEC (BT), reduction of L8, L9 using Arnoldi, symbolic reduction of DUT, DUT2-12 V L9 DUT full system: 191 eq., 695 terms hierarchically reduced system: time cost: 8min 20sec 3% error: 96 eq., 2114 terms 10% error: 84 eq., 1190 terms Slide 41

Example Operational Amplifier operational amplifier op741 specification 7 subsystems symbolic reductions error bounds [%] {2,10,20,30,50,70,90,100} 10% error (entire system) transient analysis L² error function input: sine wave excitation, 0.8 V amplitude, 1 khz frequency, T=[0 s, 0.002 s] Slide 42

Example Operational Amplifier operational amplifier op741 full system: 215 eq., 1050 terms non-hierarchical symbolic reduction 10% permitted error 97 eq., 593 terms time cost: ~10,5h Slide 43

Example Operational Amplifier operational amplifier op741 full system: 215 eq., 1050 terms non-hierarchical symbolic reduction 10% permitted error 97 eq., 593 terms time cost: ~10,5h hierarchical reduction 10% permitted error 153 eq., 464 terms time cost: 2h 22min Slide 44

Earlier Results compared to non-hierarchical approach significant savings in time for both system reduction and system simulation models with similar or better quality w.r.t. number of equations and terms error Slide 45

Earlier Results further excitations (operational amplifier) pulse sum of three sine waves sine wave Slide 46

Earlier Results further excitations (differential amplifier) pulse sum of sine waves sum of pulses Slide 47

Thank you for your attention. Slide 48