527, 5273 Dual 256 position I 2 ompatible Digital Potentiometers (POs) he 527 and 5273 are dual 256-position digital programmable linear taper potentiometers ideally suited for replacing mechanical potentiometers and variable resistors. he wiper settings are controlled through an I 2 -compatible digital interface. Upon power-up, the wiper assumes a midscale position and may be repositioned anytime after the power is stable. he devices can be programmed to go to a shutdown state during operation. he 527 and 5273 operate from 2.7 V to 5.5 V, while consuming less than 2. his low operating current, combined with a small package footprint, makes them ideal for battery-powered portable applications. he 527 and 5273, designed as pin for pin replacements for the D5243 and D5248, are offered in the -lead MOP package and operate over the 4 to +85 industrial temperature range. Features Dual 256-position End-to-End Resistance: 5 k, k I 2 ompatible Interface* Power-on Preset to Midscale ingle upply 2.7 V to 5.5 V Low emperature oefficient ppm/ Low Power, I DD 2 max Wide Operating emperature 4 to +85 MOP Package (3 mm 4.9 mm) hese Devices are Pb-Free, Halogen Free/BFR Free and are RoH ompliant N YMR MOP Z UFFIX E 846E MRING DIGRM NE YMR N = 572 5 k NE = 572 k P = 5273 5 k * Y = Production Year (Last Digit) M = Production Month ( 9, O, N, D) R = Revision L = ssembly Location XX = Last wo Digits of ssembly Lot Number PIN ONNEION PYM LXX *ontact factory for availability of 5273 k ypical pplications Potentiometer Replacement ransducer djustment of Pressure, emperature, Position, hemical, and Optical ensors RF mplifier Biasing Gain ontrol and Offset djustment B W2 V DD B 527 W B2 2 D L W *wo address decode pins (5273 only) allowing multiple devices on the same bus D W2 5273 B2 D D V DD L (op Views) ORDERING INFORMION ee detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. emiconductor omponents Industries, LL, 23 July, 23 Rev. 3 Publication Order Number: 527/D
527, 5273 V Wiper ontrol Register W V Wiper ontrol Register W L D I 2 Interface Wiper ontrol Register 2 B 2 W2 L D I 2 Interface Wiper ontrol Register 2 B W2 B2 ontrol Logic B2 Figure. 527 Functional Block Diagram D D Figure 2. 5273 Functional Block Diagram able. PIN FUNION DERIPION 527 5273 Pin No. Pin Name Description Pin Name Description B B erminal B B erminal 2 erminal D Device ddress Bit 3 W2 W2 erminal W2 W2 erminal 4 Digital Ground Digital Ground 5 VDD Positive Power upply VDD Positive Power upply 6 L erial lock Input L erial lock Input 7 D erial Data Input / Output D erial Data Input / Output 8 2 2 erminal D Device ddress Bit 9 B2 B2 erminal B2 B2 erminal W W erminal W W erminal able 2. BOLUE MXIMUM RING (Note ) Rating Value Unit V DD to.3 to 6.5 V, B, W, 2, B2, W2 Voltage to V DD I MX 2 m Digital Inputs and Output Voltage to to 6.5 V Operating emperature Range 4 to +85 Maximum Junction emperature ( JMX ) 5 torage emperature 65 to +5 Lead emperature (oldering, sec) 3 tresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating onditions is not implied. Extended exposure to stresses above the Recommended Operating onditions may affect device reliability.. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the, B, and W terminals at a given resistance. 2
527, 5273 able 3. ELERIL HRERII: 5 k and k Versions V DD = 2.7 V to 5.5 V; V = V DD ; V B = V; 4 < < +85 ; unless otherwise noted. (Note 2) Parameter est onditions ymbol Min yp (Note 3) Max Unit D HRERII RHEO MODE Resistor Differential Nonlinearity (Note 4) R WB, V = no connection (527) R DNL. + LB Resistor Integral Nonlinearity (Note 4) R WB, V = no connection (527) R INL 2.4 +2 LB Nominal Resistor olerance (Note 5) = 25 R B 2 +2 % Resistance emperature oefficient V B = V DD, Wiper = no connection R B / ppm/ Wiper Resistance V DD = 5 V, I W = 3 m R W 5 2 V DD = 3 V, I W = 3 m 25 D HRERII POENIOMEER DIVIDER MODE Resolution N 8 Bits Differential Nonlinearity (Note 6) DNL. + LB Integral Nonlinearity (Note 6) INL.4 + LB Voltage Divider emperature oefficient ode = x8 V W / ppm/ Full-scale Error ode = xff V WFE 3 LB Zero-scale Error ode = x V WZE 3 LB REIOR ERMINL Voltage Range (Note 7) V,B,W V DD V apacitance (Note 8), B f = MHz, measured to, ode = x 8,B 45 pf apacitance (Note 8) W f = MHz, measured to, ode = x 8 W 6 pf ommon-mode Leakage (Note 8) V = V B = V DD /2 I M n DIGIL INPU Input Logic High V DD = 5 V V IH.7 x V DD V Input Logic Low V DD = 5 V V IL.3V DD V Input Logic High V DD = 3 V V IH.7 x V DD V Input Logic Low V DD = 3 V V IL.3V DD V Input urrent V IN = V or 5 V I IL POWER UPPLIE Power upply Range V DD RNGE 2.7 5.5 V upply urrent V IH = 5 V or V IL = V I DD.3 2 Power Dissipation (Note 8) V IH = 5 V or V IL = V, V DD = 5 V P DI.2 mw Power upply ensitivity V DD = +5 V %, ode = Midscale P.5 %/% DYNMI HRERII (Notes 8 and ) Bandwidth 3 db R B = 5 k / k, ode = x8 BW /4 khz otal Harmonic Distortion V = V rms, V B = V, f = khz, R B = k HD W.5 % V W ettling ime (5 k / k ) V = 5 V, V B = V, LB error band t 2 s 2. V applies to both and 2, V B applies to both B and B2. 3. ypical specifications represent average readings at +25 and V DD = 5 V. 4. Resistor position nonlinearity error R INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 5. 527: V B = V DD, Wiper (V W ) = no connect. 5273: V WB = V DD. 6. INL and DNL are measured at VW with the digital potentiometer configured as a potentiometer divider similar to a voltage output D/ converter. V = V DD and V B = V. DNL specification limits of LB maximum are guaranteed monotonic operating conditions. 7. Resistor terminals, B, W have no limitations on polarity with respect to each other. 8. Guaranteed by design and not subject to production test. 9. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the, B, and W terminals at a given resistance..ll dynamic characteristics use V DD = 5 V. 3
527, 5273 able 4. PINE = 25, f =. MHz, V DD = 5 V ymbol est onditions Max Units I/O (Note ) Input/Output apacitance (D, L) V I/O = V 8 pf able 5. POWER UP IMING (Notes and 2) ymbol Parameter Max Units t PUR Power-up to Read Operation ms t PUW Power-up to Write Operation ms. his parameter is tested initially and after a design or process change that affects the parameter. 2.t PUR and t PUW are delays required from the time V is stable until the specified operation can be initiated. able 6. DIGIL POENIOMEER IMING ymbol Parameter Min Max Units t WRPO Wiper Response ime fter Power upply table 5 s t WR Wiper Response ime: L falling edge after last bit of wiper position data byte to wiper change 2 s able 7... HRERII V DD = +2.7 V to +5.5 V, 4 to +85 unless otherwise specified. ymbol Parameter Min yp Max Units f L lock Frequency 4 khz t HIGH lock High Period 6 ns t LOW lock Low Period 3 ns t U: tart ondition etup ime (for a Repeated tart ondition) 6 ns t HD: tart ondition Hold ime 6 ns t U:D Data in etup ime ns t HD:D Data in Hold ime ns t U:O top ondition etup ime 6 ns t BUF ime the bus must be free before a new transmission can start 3 ns t R D and L Rise ime 3 ns t F D and L Fall ime 3 ns t DH Data Out Hold ime ns I Noise uppression ime onstant at L, D Inputs 5 ns t L Low to D Data Out and Out s 4
527, 5273 YPIL HRERII.3. ERROR (LB).2...2.3.4 DNL ERROR (LB)..2.3.4 INL.5 32 64 96 28 6 92 224 256.5 32 64 96 28 6 92 224 256 P P Figure 3. Potentiometer Divider Differential Non-linearity, V DD = 5.6 V Figure 4. Potentiometer Divider Integral Non-linearity, V DD = 5.6 V ERROR (LB)..8.6.4.2.2.4 32 64 96 28 P 6 Figure 5. Rheostat Differential Non-linearity, V DD = 5.6 V ERROR (LB).6.4.2..8.6.4.2.2.4 92 224 256 32 64 96 28 6 92 224 256 P Figure 6. Rheostat Integral Non-linearity, V DD = 5.6 V 2 8 V DD = 2.6 V 6 5 4 5.6 V 5. V Rw ( ) 6 4 3.3 V Vw (V) 3 2 4. V 3.3 V V DD = 2.6 V 2 4. V 5.6 V 5 5 2 25 52 4 56 28 26 P P Figure 7. Wiper Resistance at Room emperature Figure 8. Wiper Voltage 5
527, 5273 YPIL HRERII 4 IB (n) 35 3 25 2 = 9 = 45 = 25 5 2 3 4 5 V DD (V) Figure 9. tandby urrent 6.4 2.5 (%).2 R (k ) 2. 2.5 2..95.9.85.8.2 5 2 4 7.75 5 2 4 7 EMPERURE ( ) EMPERURE ( ) Figure. hange in End-to-End Resistance Figure. End-to-End Resistance vs. emperature 3 6 V DD = 5 V 25 (db) 2 8 24 V DD = 3 V PRR (db) 2 5 V DD = 5 V V DD = 3 V 3 5 36 f (Hz) f (Hz) Figure 2. Gain vs. Bandwidth (ap x8) Figure 3. PRR 6
527, 5273 BI OPERION he 527 and 5273 are dual 256-position digitally controlled potentiometers. When power is first applied, the wipers assume a mid-scale position. Once the power supply is stable, the wipers may be repositioned via the I 2 compatible interface. PROGRMMING: VRIBLE REIOR Rheostat Mode (he following section refers to 527. he behavior of 5273 is identical, but for this device terminal of the resistor is not accessible.) he resistance between terminals and B, R B, has a nominal value of 5 k or k and has 256 contact points accessed by the wiper terminal, plus the B terminal contact. Data in the 8-bit Wiper register is decoded to select one of these 256 possible settings. he wiper s first connection is at the B terminal, corresponding to control position x. Ideally this would present a between the Wiper and B, but just as with a mechanical rheostat there is a small amount of contact resistance to be considered, there is a wiper resistance comprised of the R ON of the FE switch connecting the wiper output with its respective contact point. In 527/ 5273 this contact resistance is typically 5. hus a connection setting of x yields a minimum resistance of 5 between terminals W and B. For a k device, the second connection, or the first tap point, corresponds to 44 (R WB = R B /256 + R W = 39.6 + 5 ) for data x. he third connection is the next tap point, is 83 (2 x 39.6 + 5 ) for data x2, and so on. Figure 4 shows a simplified equivalent circuit where the last resistor string will not be accessed; therefore, there is LB less of the nominal resistance at full scale in addition to the wiper resistance. Wiper Register and Decoder R R R R W B he equation for determining the digitally programmed output resistance between W and B is R WB D 256 R B R W (eq. ) where D is the decimal equivalent of the binary code loaded in the 8-bit Wiper register, R B is the end-to-end resistance, and R W is the wiper resistance contributed by the on resistance of the internal switch. In summary, if R B = k and the terminal is open circuited, the following output resistance R WB will be set for the indicated Wiper register codes: able 8. ODE ND ORREPONDING R WB REINE FOR R B = k, V DD = 5 V D (Dec.) R WB ( ) Output tate 255 99,559 Full cale (R B LB + R W ) 28 5,5 Midscale 44 LB 5 Zero cale (Wiper ontact Resistance) Be aware that in the zero-scale position, the wiper resistance of 5 is still present. urrent flow between W and B in this condition should be limited to a maximum pulsed current of no more than 2 m. Failure to heed this restriction can cause degradation or possible destruction of the internal switch contact. imilar to the mechanical potentiometer, the resistance of the digital PO between the wiper W and terminal also produces a digitally controlled complementary resistance R W. When these terminals are used, the B terminal can be opened. etting the resistance value for R W starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. he general equation for this operation is R W (D) 256 D R 256 B R W (eq. 2) For R B = k and the B terminal open circuited, the following output resistance R W will be set for the indicated Wiper register codes. Figure 4. 527 Equivalent Digital PO ircuit 7
527, 5273 able 9. ODE ND ORREPONDING R W REINE FOR R B = k, V DD = 5 V D (Dec.) R W ( ) Output tate 255 44 Full cale 28 5,5 Midscale 99,659 LB,5 Zero cale V DD W,, B LOGI 527 ypical device to device resistance matching is lot dependent and may vary by up to 2%. ED Protection Digital Input W,, B LOGI Potentiometer Figure 5. ED Protection Networks erminal Voltage Operating Range he 527/5273 V DD and power supply define the limits for proper 3-terminal digital potentiometer operation. ignals or potentials applied to terminals, B or the wiper must remain inside the span of V DD and. ignals which attempt to go outside these boundaries will be clamped by the internal forward biased diodes. Figure 6. Power-up equence Because ED protection diodes limit the voltage compliance at terminals, B, and W (see Figure 5), it is recommended that V DD / be powered before applying any voltage to terminals, B, and W. he ideal power-up sequence is:, V DD, digital inputs, and then V /B/W. he order of powering V, V B, V W, and the digital inputs is not important as long as they are powered after V DD /. Power upply Bypassing Good design practice employs compact, minimum lead length layout design. Leads should be as direct as possible. It is also recommended to bypass the power supplies with quality low ER eramic chip capacitors of. F to. F. Low ER F to F tantalum or electrolytic capacitors can also be applied at the supplies to suppress transient disturbances and low frequency ripple. s a further precaution digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. V DD 3 + F. F V DD 527 Figure 7. Power upply Bypassing 8
527, 5273 I 2 BU PROOOL he following defines the features of the I 2 bus protocol:. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. ny changes in the data line while the clock is high will be interpreted as a R or OP condition. he device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. he master will always initiate data transfers and provide the clock for both transmit and receive operations. herefore, 527/5273 will be considered a slave device in all applications. R ondition he R condition precedes all commands to the device, and is defined as a high to low transition of D when L is high. he 527/5273 monitors the D and L lines and will not respond until this condition is met. OP ondition low to high transition of D when L is high determines the OP condition. ll operations must end with a OP condition. DEVIE DDREING he bus Master begins a transmission by sending a R condition. he Master then sends the address of the particular slave device it is requesting. he seven most significant bits of the 8-bit slave address are fixed as for the 527. For 5273 the first five bits are fixed as, and the next two bits are pin-programmable device address bits (D and D). he next bit (R/W) selects between the type of the instruction Read or Write. If the bit is logic high, then a Read instruction is performed. If the bit is logic low, then the Write command is executed. fter the Master sends a R condition and the slave address byte, the 527/5273 monitors the bus and responds with an acknowledge (on the D line) when its address matches the transmitted slave address. cknowledge fter a successful data transfer, each receiving device is required to generate an acknowledge. he cknowledging device pulls down the D line during the ninth clock cycle, signaling that it received the 8 bits of data. he 527/5273 responds with an acknowledge after receiving a R condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the 527/5273 is in a RED mode it transmits 8 bits of data, releases the D line, and monitors the line for an acknowledge. Once it receives this acknowledge, the 527/5273 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a OP condition. WRIE OPERION In the Write mode, the Master device sends the R condition and the slave address information to the lave device. fter the lave generates an acknowledge, the Master sends the instruction byte. fter receiving another acknowledge from the lave, the Master device transmits the data to be written into the wiper register. he 527/ 5273 acknowledges once more and the Master generates the OP condition. 9
527, 5273 t F t HIGH t R t LOW t LOW L t U: t HD: t HD:D t U:D t U:O D IN t t DH t BUF D OU Figure 8. Bus iming Diagram D L R ONDIION OP ONDIION Figure 9. tart/top ondition L FROM MER 8 9 D OUPU FROM RNMIER D OUPU FROM REEIVER R NOWLEDGE Figure 2. cknowledge ondition
527, 5273 INRUION ND REGIER DERIPION lave ddress Byte he first byte sent to the 527 from the master/processor is called the lave ddress Byte. he most significant seven bits of the slave address are a device type identifier. For the 527, these bits are fixed at. For 5273, the first five bits are fixed as, and the next two bits of the device identifier are determined by the logic levels on the D and D pins. he following bit (R/W) selects between a Read or a Write operation. If the bit is logic high, then a Read instruction is performed. If the bit is low, then the Write command is executed. Instruction Byte Write and Read instructions are respectively three and two bytes in length. he basic sequence of the two instructions is illustrated in able and. Write Operation In the write instruction, the second byte first bit () selects between the potentiometer and 2: a logic low is for the potentiometer, and a logic high is for potentiometer 2. he following bit (D) is the shutdown bit. logic high causes an open circuit at terminal while shorting the wiper terminal W to terminal B. he shutdown operation does not change the contents of the wiper register. When the shutdown bit, D, goes back to a logic low, the previous wiper position is restored. lso during shutdown, new settings can be programmed. s soon as the device is returned from shutdown, the wiper position is set according to the wiper register value. he remainder of the bits in the instruction byte are don t care bits. Read Operation In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences. here is no potentiometer channel selection bit in the Read command. he addressed channel is the one that is previously selected in the write mode. If it desired to read the potentiometer wiper register values of both channels, the first potentiometer must be addressed in write mode and then change to read mode to read the first channel value. fter that, the user must return the device to write mode with the second potentiometer selected and read the second potentiometer wiper register value in read mode. It is not necessary for users to issue the third data byte in write mode for subsequent read operation. Wiper ontrol he 527/5273 contains two 8-bit Wiper ontrol Register (WR). he Wiper ontrol Register output is decoded to select one of 256 switches along its resistor array. he contents of the WR may be written by the host via Write instruction. he Wiper ontrol Registers are a volatile register that loses its contents when the 527/5273 is powered-down. Upon power-up, the wiper is set to midscale and may be repositioned anytime after the power has become stable. able. 527 Write D R W D X X X X X X D7 D6 D5 D4 D3 D2 D D P lave ddress Byte Instruction Byte Data Byte R/W D X X X X X X D7 D6 D5 D4 D3 D2 D D lave ddress Byte Instruction Byte Data Byte able. 527 RED R D7 D6 D5 D4 D3 D2 D D P lave ddress Byte Data Byte O P D R Legend = P = = D = R = W = lave ddress Byte R/W D7 tart top cknowledge Data bit Read (bit is for Read instruction) Write (bit is for Write instruction) D6 D5 D4 D3 D2 D D X = Data Byte = D = N O P Potentiometer hannel ( or 2) elect Bit hut Down: : normal operation : wiper is parked at B terminal and terminal is open circuit. Don t are
527, 5273 able 2. 5273 Write D D W D X X X X X X D7 D6 D5 D4 D3 D2 D D P lave ddress Byte Instruction Byte Data Byte D R D D R/W D X X X X X X D7 D6 D5 D4 D3 D2 D D lave ddress Byte Instruction Byte Data Byte O P able 3. 5273 RED D D R D7 D6 D5 D4 D3 D2 D D P lave ddress Byte Data Byte D R Legend = P = = D = R = W = = D D R/W lave ddress Byte D7 tart top cknowledge Data bit Read (bit is for Read instruction) Write (bit is for Write instruction) Potentiometer hannel ( or 2) elect Bit D6 D5 D4 D3 D2 D D D = Data Byte X = D, D = N O P hut Down: : normal operation : wiper is parked at B terminal and terminal is open circuit. Don t are Bits that must match the logic levels on pins D and D able 4. ORDERING PR NUMBER Part Number Resistance Package Lead Finish hipping 527ZI 5 G3 5 k 3 / ape & Reel 527ZI G3 k MOP NiPdu 3 / ape & Reel 5273ZI 5 G3 5 k MOP NiPdu 3 / ape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our ape and Reel Packaging pecifications Brochure, BRD8/D. 3. For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON emiconductor Device Nomenclature document, ND3/D, available at www.onsemi.com. 4. ll packages are RoH-compliant (Lead-free, Halogen-free). 2
527, 5273 PGE DIMENION MOP, 3x3 E 846E IUE O YMBOL MIN NOM MX...5.5 2.75.85.95 b.7.27 c.3.23 E E D E 2.9 4.75 3. 4.9 3. 5.5 E 2.9 3. 3. e.5 B L.4.6.8 L.95 REF L2 θ.25 B º 8º DEIL OP VIEW D 2 c END VIEW e b IDE VIEW L2 Notes: () ll dimensions are in millimeters. ngles in degrees. (2) omplies with JEDE MO-87. DEIL L L ON emiconductor and are registered trademarks of emiconductor omponents Industries, LL (ILL). ILL owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. listing of ILL s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent Marking.pdf. ILL reserves the right to make changes without further notice to any products herein. ILL makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ILL assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ypical parameters which may be provided in ILL data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. ll operating parameters, including ypicals must be validated for each customer application by customer s technical experts. ILL does not convey any license under its patent rights nor the rights of others. ILL products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ILL product could create a situation where personal injury or death may occur. hould Buyer purchase or use ILL products for any such unintended or unauthorized application, Buyer shall indemnify and hold ILL and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ILL was negligent regarding the design or manufacture of the part. ILL is an Equal Opportunity/ffirmative ction Employer. his literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLIION ORDERING INFORMION LIERURE FULFILLMEN: Literature Distribution enter for ON emiconductor P.O. Box 563, Denver, olorado 827 U Phone: 33 675 275 or 8 344 386 oll Free U/anada Fax: 33 675 276 or 8 344 3867 oll Free U/anada Email: orderlit@onsemi.com N. merican echnical upport: 8 282 9855 oll Free U/anada Europe, Middle East and frica echnical upport: Phone: 42 33 79 29 Japan ustomer Focus enter Phone: 8 3 587 5 3 ON emiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local ales Representative 527/D