Dual, 6-Bit nanodac+ with 4 ppm/ C Reference, SPI Interface FEATURES High relative accuracy (INL): ±4 LSB maximum at 6 bits Low drift.5 V reference: 4 ppm/ C typical Tiny package: 3 mm 3 mm, 6-lead LFCSP Total unadjusted error (TUE): ±.% of FSR maximum Offset error: ±.5 mv maximum Gain error: ±.% of FSR maximum High drive capability: 5 ma,.5 V from supply rails User-selectable gain of or (GAIN pin) Reset to zero scale or midscale (RSTSEL pin).8 V logic compatibility 5 MHz SPI with readback or daisy chain Low glitch:.5 nv-sec Low power: 3.3 mw at 3 V.7 V to 5.5 V power supply ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC) Temperature range: 55 C to +5 C Controlled manufacturing baseline assembly/test site fabrication site Enhanced product change notification Qualification data available on request APPLICATIONS Optical transceivers Base station power amplifiers Process control (PLC input/output cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The, a member of the nanodac+ family, is a low power, dual, 6-bit buffered voltage output digital-to-analog converter (DAC). The device includes a.5 V, 4 ppm/ C internal reference (enabled by default) and a gain select pin giving a full-scale output of.5 V (gain = ) or 5 V (gain = ). The device operates from a single.7 V to 5.5 V supply, is guaranteed monotonic by design, and exhibits less than.% FSR gain error and.5 mv offset error performance. The also incorporates a power-on reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remains there until a valid write occurs. The device contains a per channel power-down feature that reduces the current consumption of the device to 4 μa at 3 V while in power-down mode. Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. V LOGIC SCLK SYNC SDIN SDO FUNCTIONAL BLOCK DIAGRAM V DD INTERFACE LOGIC LDAC RESET INPUT REGISTER INPUT REGISTER GND DAC REGISTER DAC REGISTER POWER-ON RESET RSTSEL Figure. STRING DAC A STRING DAC B BUFFER BUFFER V OUT A V OUT B One Technology Way, P.O. Box 96, Norwood, MA 6-96, U.S.A. Tel: 78.39.47 5 6 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com V REF GAIN = / GAIN.5V REFERENCE POWER- DOWN LOGIC The uses a versatile serial peripheral interface (SPI) that operates at clock rates up to 5 MHz, and contains a VLOGIC pin that is intended for.8 V/3 V/5 V logic. Additional application and technical information can be found in the AD5689R/AD5687R data sheet. PRODUCT HIGHLIGHTS. High Relative Accuracy (INL). ±4 LSB maximum. Low Drift.5 V On-Chip Reference. 4 ppm/ C typical temperature coefficient 3 ppm/ C maximum temperature coefficient 346-
TABLE OF CONTENTS Features... Enhanced Product Features... Applications... Functional Block Diagram... General Description... Product Highlights... Revision History... Specifications... 3 AC Characteristics... 5 Enhanced Product Timing Characteristics...6 Daisy-Chain and Readback Timing Characteristics...7 Absolute Maximum Ratings...9 ESD Caution...9 Pin Configuration and Function Descriptions... Typical Performance Characteristics... Outline Dimensions... 7 Ordering Guide... 7 REVISION HISTORY /6 Rev. to Rev. A Changed.8 V VLOGIC 5.5 V to.6 V VLOGIC 5.5 V... Throughout Changes to Features Section... Changes to VLOGIC Parameter, Table... 4 Changes to Table 3... 6 Changes to Table 4 and Figure 4... 7 Changes to Figure 5... 8 Changes to Table 5... 9 Changes to Figure... Changes to Figure 6, Figure 7, and Figure 8... Changes to Figure 9 to Figure 4... 3 Changes to Figure 6, Figure 7, and Figure 3... 4 Changes to Figure 33 and Figure 34... 5 8/5 Revision : Initial Version Rev. A Page of 7
SPECIFICATIONS VDD =.7 V to 5.5 V,.6 V VLOGIC 5.5 V, RL = kω, CL = pf, and all specifications TMIN to TMAX, unless otherwise noted. Table. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE Resolution 6 Bits Relative Accuracy ± ±4 LSB Gain = ± ±5 LSB Gain = Differential Nonlinearity (DNL) ± LSB Guaranteed monotonic by design Zero-Code Error.4.5 mv All zeros loaded to DAC register Offset Error +. ±.5 mv Full-Scale Error +. ±. % of FSR All ones loaded to DAC register Gain Error ±. ±. % of FSR Gain = ±. ±.5 % of FSR Gain = Total Unadjusted Error ±. ±. % of FSR External reference; gain = ±. % of FSR Internal reference; gain = Offset Error Drift ± µv/ C Gain Temperature Coefficient (TC) ± ppm Of FSR/ C DC Power Supply Rejection Ratio.5 mv/v DAC code = midscale, VDD = 5 V ± % DC Crosstalk ± µv Due to single channel, full-scale output change ±3 µv/ma Due to load current change ± µv Due to powering down (per channel) OUTPUT CHARACTERISTICS Output Voltage Range VREF V Gain = VREF V Gain =, see Figure 8 Capacitive Load Stability nf RL = nf RL = kω Resistive Load 3 kω Load Regulation 8 µv/ma 5 V ± %, DAC code = midscale; 3 ma IOUT +3 ma 8 µv/ma 3 V ± %, DAC code = midscale; ma IOUT + ma Short-Circuit Current 4 4 ma Load Impedance at Rails 5 5 Ω See Figure 8 Power-Up Time.5 µs Coming out of power-down mode; VDD = 5 V REFERENCE OUTPUT Output Voltage 6.4975.55 V At ambient Reference TC 7, 8 4 3 ppm/ C Output Impedance.4 Ω Output Voltage Noise µv p-p. Hz to Hz Output Voltage Noise Density 4 nv/ Hz At ambient; f = khz, CL = nf Load Regulation Sourcing µv/ma At ambient Load Regulation Sinking 4 µv/ma At ambient Output Current Load Capability ±5 ma VDD 3 V Line Regulation µv/v At ambient Thermal Hysteresis 5 ppm First cycle 5 ppm Additional cycles LOGIC INPUTS Input Current ± µa Per pin Input Voltage Low (VINL).3 VLOGIC V High (VINH).7 VLOGIC V Pin Capacitance pf Rev. A Page 3 of 7
Enhanced Product Parameter Min Typ Max Unit Test Conditions/Comments LOGIC OUTPUTS (SDO) Output Voltage Low (VOL).4 V ISINK = μa High (VOH) VLOGIC.4 V ISOURCE = μa Floating State Output Capacitance 4 pf POWER REQUIREMENTS VLOGIC.6 5.5 V ILOGIC 3 µa VDD.7 5.5 V Gain = VDD VREF +.5 5.5 V Gain = IDD VIH = VDD, VIL = GND, VDD =.7 V to 5.5 V Normal Mode 9.59.7 ma Internal reference off..3 ma Internal reference on at full scale All Power-Down Modes 4 µa 4 C to +85 C 6 µa 55 C to +5 C DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = mv and exists only when VREF = VDD with gain = or when VREF/ = VDD with gain =. Linearity is calculated using a reduced code range of 56 to 65,8. Guaranteed by design and characterization; not production tested. 3 Channel A can have an output current of up to 5 ma. Similarly, Channel B can have an output current of up to 5 ma, up to a junction temperature of 35 C. 4 VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature may be exceeded during current limit, but operation above the specified maximum operation junction temperature can impair device reliability. 5 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 5 Ω typical channel resistance of the output device. For example, when sinking ma, the minimum output voltage = 5 Ω ma = 5 mv (see Figure 8). 6 Initial accuracy presolder reflow is ±75 µv; output voltage includes the effects of preconditioning drift. See the AD5689R/AD5687R data sheet for more information. 7 Reference is trimmed and tested at two temperatures and is characterized from 55 C to +5 C. 8 Reference temperature coefficient is calculated as per the box method. See the AD5689R/AD5687R data sheet for more information. 9 Interface inactive. Both DACs active. DAC outputs unloaded. Both DACs powered down. Rev. A Page 4 of 7
AC CHARACTERISTICS VDD =.7 V to 5.5 V, RL = kω to GND, CL = pf to GND,.6 V VLOGIC 5.5 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization; not production tested. Table. Parameter Min Typ Max Unit Test Conditions/Comments Output Voltage Settling Time 5 8 µs ¼ to ¾ scale settling to ± LSB Slew Rate.8 V/µs Digital-to-Analog Glitch Impulse.5 nv-sec LSB change around major carry Digital Feedthrough.3 nv-sec Digital Crosstalk. nv-sec Analog Crosstalk. nv-sec DAC-to-DAC Crosstalk.3 nv-sec Total Harmonic Distortion (THD) 3 8 db At ambient, BW = khz, VDD = 5 V, fout = khz Output Noise Spectral Density (NSD) 3 nv/ Hz DAC code = midscale, khz; gain = Output Noise 6 µv p-p. Hz to Hz Signal-to-Noise Ratio (SNR) 9 db At ambient, BW = khz, VDD = 5 V, fout = khz Spurious Free Dynamic Range (SFDR) 83 db At ambient, BW = khz, VDD = 5 V, fout = khz Signal-to-Noise-and-Distortion Ratio (SINAD) 8 db At ambient, BW = khz, VDD = 5 V, fout = khz See the AD5689R/AD5687R data sheet. Temperature range is 55 C to +5 C, typical at 5 C. 3 Digitally generated sine wave at khz. Rev. A Page 5 of 7
Enhanced Product TIMING CHARACTERISTICS All input signals are specified with tr = tf = ns/v (% to 9% of VDD) and timed from a voltage level of (VIL + VIH)/. See Figure. VDD =.7 V to 5.5 V,.6 V VLOGIC 5.5 V, and VREF =.5 V. All specifications TMIN to TMAX, unless otherwise noted. Table 3..6 V VLOGIC <.7 V.7 V VLOGIC 5.5 V Parameter Symbol Min Max Min Max Unit SCLK Cycle Time t ns SCLK High Time t ns SCLK Low Time t3 ns SYNC to SCLK Falling Edge Setup Time t4 5 ns Data Setup Time t5 5 5 ns Data Hold Time t6 5 5 ns SCLK Falling Edge to SYNC Rising Edge t7 ns Minimum SYNC High Time t8 ns SYNC Rising Edge to SYNC Rising Edge (DAC Register Update/s) t9 87 83 ns SYNC Falling Edge to SCLK Fall Ignore t 6 ns LDAC Pulse Width Low t 5 5 ns SYNC Rising Edge to LDAC Rising Edge t ns SYNC Rising Edge to LDAC Falling Edge t3 3 3 ns LDAC Falling Edge to SYNC Rising Edge t4 84 8 ns Minimum Pulse Width Low t5 3 3 ns Pulse Activation Time t6 3 3 ns Power-Up Time 4.5 4.5 μs Guaranteed by design and characterization; not production tested. Time to exit power-down to normal mode of operation, 3 nd clock edge to 9% of DAC midscale value, with output unloaded. t t SCLK t 8 t 4 t 3 t t 7 t 4 SYNC t 9 t 5 t 6 SDIN DB3 DB t 3 t LDAC t LDAC RESET t 5 VOUT t 6 ASYNCHRONOUS LDAC UPDATE MODE. SYNCHRONOUS LDAC UPDATE MODE. Figure. Serial Write Operation 346-3 Rev. A Page 6 of 7
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS All input signals are specified with tr = tf = ns/v (% to 9% of VDD) and timed from a voltage level of (VIL + VIH)/. See Figure 4 and Figure 5. VDD =.7 V to 5.5 V,.6 V VLOGIC 5.5 V, and VREF =.5 V. All specifications TMIN to TMAX, unless otherwise noted. VDD =.7 V to 5.5 V. E Table 4..6 V VLOGIC <.7 V.7 V VLOGIC 5.5 V Parameter Symbol Min Max Min Max Unit SCLK Cycle Time t 66 4 ns SCLK High Time t 33 ns SCLK Low Time t3 33 ns SYNC to SCLK Falling Edge t4 33 ns E Data Setup Time t5 5 5 ns Data Hold Time t6 5 5 ns SCLK Falling Edge to SYNC Rising Edge t7 5 ns E E Minimum SYNC High Time t8 6 3 ns SDO Data Valid from SCLK Rising Edge t9 45 3 ns SYNC Rising Edge to SCLK Rising Edge t 5 ns E SYNC Rising Edge to SDO Disable t 6 6 ns Guaranteed by design and characterization; not production tested. Circuit and Timing Diagrams µa I OL TO OUTPUT PIN C L pf V OH (MIN) µa I OH Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications 346-4 t SCLK 4 48 t 8 t t 3 t 7 t t 4 SYNC t 5 t 6 SDIN DB3 DB DB3 DB INPUT WORD FOR DAC N t 9 INPUT WORD FOR DAC N + SDO DB3 DB UNDEFINED INPUT WORD FOR DAC N Figure 4. Daisy-Chain Timing Diagram 346-5 Rev. A Page 7 of 7
Enhanced Product t SCLK 4 4 t 8 t 3 t 4 t t 7 t 8 t SYNC t 6 t 5 SDIN DB3 DB DB3 DB INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION t 9 t SDO DB3 DB HI-Z SELECTED REGISTER DATA CLOCKED OUT 346-6 Figure 5. Readback Timing Diagram Rev. A Page 8 of 7
ABSOLUTE MAXIMUM RATINGS TA = 5 C, unless otherwise noted. Table 5. Parameter Rating VDD to GND.3 V to +7 V VLOGIC to GND.3 V to +7 V VOUT to GND.3 V to VDD +.3 V VREF to GND.3 V to VDD +.3 V Digital Input Voltage to GND.3 V to VLOGIC +.3 V Operating Temperature Range 55 C to +5 C Storage Temperature Range 65 C to +5 C Junction Temperature 35 C 6-Lead LFCSP, θja Thermal Impedance, 7 C/W JA Airflow (4-Layer Board) Reflow Soldering Peak Temperature, 6 C Pb Free (J-STD-) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION Rev. A Page 9 of 7
Enhanced Product PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 5 V REF 3 RESET SDO LDAC GAIN 5 6 7 8 6 NC 4 RSTSEL V OUT A GND V DD 3 NC 4 SDIN SYNC SCLK 9 V LOGIC V OUT B TOP VIEW (Not to Scale) NOTES. THE EXPOSED PAD MUST BE TIED TO GND.. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 6. Pin Configuration Table 6. Pin Function Descriptions Pin No Mnemonic Description VOUTA Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. GND Ground Reference Point for All Circuitry on the. 3 VDD Power Supply Input. The can be operated from.7 V to 5.5 V. Decouple the supply with a μf capacitor in parallel with a. μf capacitor to GND. 4 NC No Connect. Do not connect to this pin. 5 VOUTB Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 6 SDO Serial Data Output. SDO can be used to daisy-chain a number of devices together, or it can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling edge of the clock. 7 LDAC LDAC can be operated in two modes: asynchronously and synchronously. Pulsing this pin low allows either or both DAC registers to be updated if the input registers have new data; both DAC outputs can be updated simultaneously. This pin can also be tied permanently low. 8 GAIN Gain Select. When this pin is tied to GND, both DACs output a span from V to VREF. If this pin is tied to VLOGIC, both DACs output a span of V to VREF. 9 VLOGIC Digital Power Supply. Voltage ranges from.6 V VLOGIC 5.5 V. SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at rates of up to 5 MHz. SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, data is transferred in on the falling edges of the next 4 clocks. SDIN Serial Data Input. This device has a 4-bit input shift register. Data is clocked into the register on the falling edge of the serial clock input. 3 RESET Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending on the state of the RSTSEL pin. If this pin is forced low at power-up, the power-on reset (POR) circuit does not initialize the device correctly until this pin is released. 4 RSTSEL Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to VLOGIC powers up both DACs to midscale. 5 VREF Reference Voltage. The has a common reference pin. When using the internal reference, this is the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is as a reference output. 6 NC No Connect. Do not connect to this pin. 7 EPAD Exposed Pad. The exposed pad must be tied to GND. 346-7 Rev. A Page of 7
TYPICAL PERFORMANCE CHARACTERISTICS.5.55.5 DEVICE DEVICE DEVICE 3 DEVICE 4 DEVICE 5 6 4 V REF (V).55.5.4995 NSD (nv/ Hz) 8 6.499 4.4985.498 4 4 6 8 TEMPERATURE ( C) Figure 7. Internal Reference Voltage (VREF) vs. Temperature 346-9 k k k M FREQUENCY (MHz) Figure. Internal Reference Noise Spectral Density (NSD) vs. Frequency 346-3.5.55.5 DEVICE DEVICE DEVICE 3 DEVICE 4 DEVICE 5 T.55 V REF (V).5.4995.499.4985.498 4 4 6 8 TEMPERATURE ( C) 346- CH µv M.s A CH 6mV 346-4 Figure 8. VREF vs. Temperature Figure. Internal Reference Noise,. Hz to Hz 9 8.5.4999 7 NUMBER OF UNITS 6 5 4 3 V REF (V).4998.4997.4996.4995.4994.5..5..5 3. 3.5 4. 4.5 5. TEMPERATURE DRIFT (ppm/ C) Figure 9. Reference Output Temperature Drift Histogram 346-.4993.5.3...3.5 I LOAD (A) Figure. VREF vs. Load Current (ILOAD) 346-5 Rev. A Page of 7
Enhanced Product 8 8 6 6 4 4 INL (LSB) ERROR (LSB) INL DNL 4 4 6 6 8 REFERENCE =.5V 3 4 5 6 CODE Figure 3. Integral Nonlinearity (INL) vs. Code 346-7 8 4 6 TEMPERATURE ( C) Figure 6. INL Error and DNL Error vs. Temperature 346-..8 8.6 6.4 4 DNL (LSB).. ERROR (LSB) INL DNL.4.6.8. REFERENCE =.5V 3 4 5 6 CODE Figure 4. Differential Nonlinearity (DNL) vs. Code 346-9 4 6 8.5..5..5 3. 3.5 4. 4.5 5. V REF (V) Figure 7. INL Error and DNL Error vs. VREF 346-.5.5 D 8 6 V REF (V).4998.4996.4994 D3 ERROR (LSB) 4 4 INL DNL.499.499.5 3. 3.5 4. 4.5 5. 5.5 D V DD (V) 346-6 6 8.7 3. 3.7 4. 4.7 5. SUPPLY VOLTAGE (V) 346-3 Figure 5. VREF vs. Supply Voltage (VDD) Figure 8. INL Error and DNL Error vs. Supply Voltage Rev. A Page of 7
..5.8.6. ERROR (% of FSR).4...4 FULL-SCALE ERROR GAIN ERROR ERROR (mv).5.5 ZERO-CODE ERROR OFFSET ERROR.6.8. 4 4 6 8 TEMPERATURE ( C) 346-4..5.7 3. 3.7 4. 4.7 5. SUPPLY VOLTAGE (V) 346-7 Figure 9. Gain Error and Full-Scale Error vs. Temperature Figure. Zero-Code Error and Offset Error vs. Supply Voltage ERROR (mv).4...8.6.4. ZERO-CODE ERROR OFFSET ERROR TOTAL UNADJUSTED ERROR (% of FSR)..9.8.7.6.5.4.3.. 4 4 6 8 TEMPERATURE ( C) 346-5 4 4 6 8 TEMPERATURE ( C) 346-8 Figure. Zero-Code Error and Offset Error vs. Temperature Figure 3. Total Unadjusted Error (TUE) vs. Temperature.. ERROR (% of FSR).8.6.4...4.6.8..7 3. 3.7 4. 4.7 5. SUPPLY VOLTAGE (V) GAIN ERROR FULL-SCALE ERROR 346-6 TOTAL UNADJUSTED ERROR (% of FSR).8.6.4...4.6.8..7 3. 3.7 4. 4.7 5. SUPPLY VOLTAGE (V) 346-9 Figure. Gain Error and Full-Scale Error vs. Supply Voltage Figure 4. Total Unadjusted Error (TUE) vs. Supply Voltage, Gain = Rev. A Page 3 of 7
Enhanced Product TOTAL UNADJUSTED ERROR (% of FSR)...3.4.5.6.7.8.9 V DD =5V T A =5 C. 3 4 5 6 65535 CODE Figure 5. Total Unadjusted Error (TUE) vs. Code 346-3 V OUT (V)..8.6.4 SINKING.7V. SINKING 5V..4 SOURCING 5V.6 SOURCING.7V.8. 5 5 5 3 LOAD CURRENT (ma) Figure 8. Headroom/Footroom vs. Load Current 346-33 5 EXTERNAL REFERENCE =.5V 7 6 5 GAIN = REFERENCE =.5V FULL SCALE 4 THREE-QUARTER SCALE HITS 5 V OUT (V) 3 MIDSCALE ONE-QUARTER SCALE 5 ZERO SCALE 54 56 58 6 6 64 I DD (µa) Figure 6. IDD Histogram with External Reference, VDD = 5 V 346-3.6.4...4.6 LOAD CURRENT (A) Figure 9. Source and Sink Capability at 5 V, Gain = 346-34 HITS 3 5 5 INTERNAL REFERENCE =.5V V OUT (V) 5 4 3 V DD = 3V GAIN = EXTERNAL REFERENCE =.5V xffff xc x8 x4 x 5 4 6 8 4 I DD (µa) 346-3 6 4 4 6 I OUT (ma) 346-35 Figure 7. IDD Histogram with Internal Reference, VREF =.5 V, Gain = Figure 3. Source and Sink Capability at 3 V, Gain = Rev. A Page 4 of 7
.4 T SUPPLY CURRENT (ma)...8.6 FULL SCALE ZERO CODE EXTERNAL REFERENCE, FULL SCALE.4. 4 6 TEMPERATURE ( C) Figure 3. Supply Current vs. Temperature 346-36 EXTERNAL REFERENCE =.5V CH µv M.s A CH 8mV Figure 33.. Hz to Hz Output Noise Plot,.5 V External Reference 346-38.58 T.53 V OUT (V).4998 CHANNEL B.4993 V DD = 5.5V INTERNAL REFERENCE POSITIVE MAJOR CODE TRANSITION ENERGY =.76nV-sec.4988 4 6 8 TIME (µs) Figure 3. Digital-to-Analog Glitch Impulse 346-37 CH µv M.s A CH 8mV Figure 34.. Hz to Hz Output Noise Plot,.5 V Internal Reference 346-39 Rev. A Page 5 of 7
Enhanced Product 6 4 V DD =5V T A =5 C FULL SCALE MIDSCALE ZERO SCALE NSD (nv/ Hz) 8 6 BANDWIDTH (db) 3 4 4 k k k M FREQUENCY (Hz) 346-4 5 REFERENCE =.5V, ±.V p-p 6 k k FREQUENCY (Hz) M M 346-4 Figure 35. Noise Spectral Density (NSD) vs. Frequency Figure 37. Multiplying Bandwidth, External Reference =.5 V, ±. V p-p, khz to MHz REFERENCE =.5V 4 THD (dbv) 6 8 4 6 8 4 6 8 4 6 8 FREQUENCY (Hz) Figure 36. Total Harmonic Distortion at khz vs. Frequency 346-4 Rev. A Page 6 of 7
OUTLINE DIMENSIONS PIN INDICATOR 3. 3. SQ.9.5 BSC.3.3.8 3 6 PIN INDICATOR EXPOSED PAD.75.6 SQ.45.8.75.7 SEATING PLANE TOP VIEW.5.4.3.5 MAX. NOM COPLANARITY.8. REF 9 4 8 5 BOTTOM VIEW COMPLIANT TO JEDEC STANDARDS MO--WEED-6..5 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 38. 6-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 3 mm 3 mm Body, Very Very Thin Quad (CP-6-) Dimensions shown in millimeters 8-6--E ORDERING GUIDE Model Resolution Temperature Range Package Description Package Option AD5689RTCPZ-EP-RL7 6 Bits 55 C to +5 C 6-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-6- Z = RoHS Compliant Part. 5 6 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D346--/6(A) Rev. A Page 7 of 7