A Successive Approximation ADC based on a new Segmented DAC

A Successive Approximation ADC based on a new Segmented DAC

segmented current-mode DAC successive approximation ADC bi-direction segmented current-mode DAC DAC INL 0.47 LSB DNL 0.154 LSB DAC 3V 8 2MS/s successive approximation ADC TSMC 1P4M 0.35 m CMOS INL 0.82 LSB DNL 0.31 LSB ENOB 7 2.6mW I

A Successive Approximation ADC based on a new Segmented DAC ABSTRACT A successive approximation analog-to-digital converter (ADC) based on a new segmented digital-to-analog converter (DAC) architecture is presented. A more efficient method which is the bi-direction segmented current-mode approach is proposed to implement the high-resolution and high speed DAC. This DAC has the maximum integral nonlinearity (INL) error of 0.47 LSB, and the maximum differential nonlinearity (DNL) error of 0.154 LSB. Based on this new DAC, a 3-V, 8-bit, 2-MS/s ADC is realized. The whole circuit is implemented by the TSMC 1P4M 0.35 m CMOS process. The experimental results show that the INL of ADC is less than 0.82 LSB. Meanwhile, the DNL is less than 0.31 LSB. The power consumption is only 2.6mW with the effective number of bits of 7. II

III

...I ABSTRACT... II... III...IV...VI...VII Chapter 1 INTRODUCTION... 1 1.1 Motivation... 1 1.2 Organization of the Dissertation... 2 1.3 SAR ADC versus other ADCs... 2 1.3.1 Pipelined Converter... 2 1.3.2 Flash Converter... 3 1.3.3 Sigma-Delta Converter... 4 1.4 Circuit Characteristic... 4 Chapter 2 BASIC CONCEPTS... 5 2.1 Successive Approximation ADC Architecture... 5 2.2 Algorithm... 6 2.3 SAR ADC Techniques... 8 2.3.1 R-2R-Based Converter... 8 2.3.2 Charge-Redistribution Converter... 9 2.3.3 Resistor-Capacitor Hybrid Converter... 10 2.3.4 Current-Mode Converter... 10 Chapter 3 CIRCUIT DESIGN OF SAR ADC... 12 3.1 Sample / Hold (S/H) Amplifier Architecture... 12 3.1.1 Clock Divider... 13 3.1.2 Simulation results of the S/H... 14 3.2 Comparator... 17 3.2.1 Comparator Circuit... 17 3.2.2 Clock of the Comparator... 20 3.3 Segmented Current-Mode DAC... 21 3.3.1 3-way switch controller... 27 3.3.2 I-V Converter... 30 3.3.2.1 Operational Amplifier... 30 3.3.3 Simulation results of the DAC... 33 3.4 SAR Controller... 34 IV

Chapter 4 EXPERIMENTAL RESULTS... 38 4.1 ADC Test... 38 4.2 Layout Arrangement... 40 Chapter 5 CONCLUSIONS & FUTURE WORKS... 43 5.1 Conclusions... 43 5.2 Future Works... 43 REFERENCES... 45... 47 V

1 Size of the comparator... 18 2 3 8 binary-to-thermometer decoder... 28 3 P-channel (B 7 =0)... 28 4 N-channel (B 7 =1)... 29 5 OPA... 32 6 8 SAR... 36 7 Effective number of bits... 40 8 Experimental results of the proposed ADC... 42 9 successive approximation ADC... 43 VI

1. 1 General Pipelined ADC architecture... 3 1. 2 N-bit Flash ADC... 3 2. 1 Successive approximation ADC... 5 2. 2 Various values of the DAC output voltage... 6 2. 3 N-bit successive approximation approach... 7 2. 4 4-bit successive approximation ADC conversion... 8 2. 5 DAC... 9 2. 6 Charge-redistribution converter... 9 2. 7 Resistor-Capacitor Hybrid converter... 10 2. 8 Binary-weighted current-mode converter... 11 3. 1 Double sampling S/H architecture... 12 3. 2 Execution period of the double sampling.... 13 3. 3 Transmission Gate circuit... 13 3. 4 clock divider circuit... 14 3. 5 clock... 14 3. 6 Simulation result of the S/H circuit.... 15 3. 7 Output power spectrum density of the S/H... 16 3. 8 Comparator... 17 3. 9 Circuit design of the comparator... 18 3. 10 Auto-zeroing circuit.... 19 3. 11 Clock circuit of the comparator... 20 3. 12 Simple RC model... 20 3. 13 Clock simulation of the comparator... 21 3. 14 Basic N-bit segmented D/A converter... 22 3. 15 Non-monotonic behavior of the DAC.... 23 3. 16 Monotonic N-bit segmented D/A converter... 23 3. 17 Monotonic behavior of the DAC... 23 3. 18 Segmented N-bit inherently monotonic current DAC... 24 3. 19 N-bit bi-direction segmented DAC... 25 3. 20 DAC P... 26 3. 21 MOS... 27 3. 22 2-way switches circuit... 29 3. 23 Two-stage OPA... 31 3. 24 Two-stage OPA... 31 3. 25 Simulation result of the DAC... 33 VII

3. 26 DAC INL... 34 3. 27 DAC DNL... 34 3. 28 N-bit SAR... 35 3. 29 N-bit SAR controller based on the non-redundant structure... 35 3. 30 N th... 36 3. 31 D-latch... 37 4. 1 ADC INL... 38 4. 2 ADC DNL... 39 4. 3 Output power spectrum density of the ADC... 39 4. 4 ENOB versus input frequency... 40 4. 5 Layout arrangement... 41 4. 6 I/O PAD arrangement... 41 4. 7 Layout view... 42 VIII

Chapter 1 INTRODUCTION 1.1 Motivation Analog-to-Digital Converter ADC Digital-to-Analog Converter DAC (Bluetooth) ADC DAC ADC ADC successive approximation register (SAR) ADC 5MS/s (8~16 bits) ADC successive approximation ADC ADC DAC successive approximation ADC successive approximation ADC DAC current-steering with resistance ladder [1] charge-redistribution with capacitance array [2] successive approximation ADC 1

current-mode successive approximation ADC DAC segmented current-mode [3] 1.2 Organization of the Dissertation successive approximation ADC successive approximation ADC ADC 1.3 SAR ADC versus other ADCs ADC ADC SAR ADC ADC SAR 1.3.1 Pipelined Converter Pipelined ADC 1. 1 parallel (stage) (conversion rate) (Latency) Latency ADC ADC Pipelined ADC clock Latency successive approximation ADC clock Latency Pipelined ADC successive approximation ADC stage 2

OPA S/H 1. 1 General Pipelined ADC architecture 1.3.2 Flash Converter Flash ADC 1. 2 wideband low-gain preamp(s) latch Flash ADC ADC 2 n Flash 10 12 ADC successive approximation ADC Flash ADC 1. 2 N-bit Flash ADC 3

1.3.3 Sigma-Delta Converter Sigma-Delta ( oversampling) Sigma-Delta modulators ( ) (multi-bit) Sigma-Delta modulators ( 16 ) digital decimation filter 1.4 Circuit Characteristic successive approximation ADC 1. 2. 3. 4

Chapter 2 BASIC CONCEPTS 2.1 Successive Approximation ADC Architecture Successive approximation ADC 2. 1 (S/H) (Comparator) Successive Approximation Register (SAR) N N Successive approximation ADC N 2. 1 Successive approximation ADC N successive approximation ADC (V in ) Sample/Hold (S/H) comparator N DAC SAR (binary search) DAC comparator (MSB) (LSB) N register (D-latch) successive approximation ADC 5

comparator DAC successive approximation ADC comparator V in V DAC DAC ADC 1/2 LSB comparator DAC 2.2 Algorithm Successive approximation ADC ( ) N successive approximation ADC DAC V FS (V FS DAC full-scale voltage) V in V D/A (DAC ) 1 0 DAC V FS /2 ( ) V D/A V in (V in ) N N (N cycles) (LSB) 4 successive approximation ADC DAC 2. 2 2. 2 Various values of the DAC output voltage 6

2. 3 i N 2. 3 N-bit successive approximation approach 4 Y DAC X 4 successive approximation ADC 2. DAC 1000 2 V in > V DAC B 3 1 DAC 1100 2 V in < V DAC B 2 0 DAC 1010 2 V in > V DAC B 1 1 DAC 1011 2 7

V in < V DAC B 0 0 1010 2 N successive approximation ADC N 4 successive approximation ADC 2. 4 4-bit successive approximation ADC conversion 2.3 SAR ADC Techniques successive approximation ADC DAC 2.3.1 R-2R-Based Converter DAC [1][4] 2. 5 binary-weighted ( ) DAC MSBs thermometer (Glitch) ( ) (Layout area) 8

2. 5 DAC 2.3.2 Charge-Redistribution Converter [2] 2. 6 ( binary-weighted) DAC SAR ADC S/H [5] [6] 2. 6 Charge-redistribution converter 9

2.3.3 Resistor-Capacitor Hybrid Converter binary-weighted [7][8] 2. 7 DAC DAC binary-weighted 2. 7 Resistor-Capacitor Hybrid converter 2.3.4 Current-Mode Converter ( binary-weighted) [9] 2. 8 10

DAC segmented current-mode [3] segmented current-mode 2. 8 Binary-weighted current-mode converter 11

Chapter 3 CIRCUIT DESIGN OF SAR ADC approximation ADC 3-V 8 16MHz data rate 2 MS/s 1V~2V successive successive approximation ADC 3.1 Sample / Hold (S/H) Amplifier Architecture Clock Double sampling operational amplifiers (OPAs) Buffer 3. 1 S/H 3. 2 Clock (Sample) (Hold) Clock (Hold) (Sample) Double sampling 3. 1 Double sampling S/H architecture. 12

3. 2 Execution period of the double sampling. Sample-and-Hold circuit Charge Injection Clock Feedthrough Transmission Gate ( 3. 3 ) MOS Charge Injection PMOS NMOS CLK CLK PMOS NMOS channel channel q 1 q 2 MOS gate-source overlap capacitance Charge Injection OPAs Offset Error Sample-and-Hold circuit OPAs Offset 3. 3 Transmission Gate circuit 3.1.1 Clock Divider S/H D D 2 16MHz 16 13

4 D 1MHz 3. 4 3. 5 D 3. 4 clock divider circuit 3. 5 clock 3.1.2 Simulation results of the S/H 3. 6 S/H 1-V PP 62.5KHz S/H 1MHz S/H tracking 14

3. 6 Simulation result of the S/H circuit. 8 S/H 1MHz 1-V PP 62.5KHz 32 1024 (FFT) 3. 7 500fF Signal-to-(Noise + distortion) Ratio(SNDR) 59.35dB S/H 8-bit 15

20 40 60 80 100 120 3. 7 Output power spectrum density of the S/H. 49.76dB (8-bit ) (3.1)[10] K T C (3.1) 2 Vn(rms) V n(rms) 1/4 V LSB (=1mV) K Boltzmanns constant ( 1.38 10-23 JK -1 ) T 300 K 4.14fF 500fF S/H 16

3.2 Comparator successive approximation ADC 16MHz 1/2 LSB Latch Latch Latch ( 0V~3V) -1mV +1mV 63.5dB Latch Latch 3. 8 Comparator 3. 8 Differential preamplifier Latch preamplifier 3.2.1 Comparator Circuit 3. 9 ph2 high M1 M2 M3 M4 M7 Differential Preamplifier ph2 low M3 M4 M5 M6 M7 Bistable Multivibrator [11] 17

3. 9 Circuit design of the comparator. ph1 ph2 ph3 high preamplifier C1 C2 VIN Vc VIN VD ph1 low C1 C2 node C D ph3 low C1 C2 V in- V in+ node A B ph2 low Multivibrator latch VA VB VIN VIN 0 V OUT high 1 Size of the comparator (W/L) M1 (1.1/1) M2 (1.1/1) M3 (7.5/1)*2 M4 (7.5/1)*2 M5 0.9/0.35 M6 0.9/0.35 M7 (7.6/1)*2 S1 0.9/0.35 S2 0.9/0.35 18

50 A (3.2) (3.3)[12] Channel-Length modulation Latch 1 multiple fingers 1 2 W L 2 I D ncox ( VGS VTH) (3.2) 1 2 W L 2 I D pcox ( VGS VTH) (3.3) LSB) (Offset) 208 W 2mV ( 1/2 Auto-zeroing 3. 10 node A B 3. 10 Auto-zeroing circuit. 19

3.2.2 Clock of the Comparator clock delay 3. 11 3. 11 Clock circuit of the comparator. RC 3. 12 R p R n PMOS NMOS C L C gs C gd (3.4) (3.5) L RC L i t d (3.6) 3. 12 Simple RC model. 20

R 1 p W pcox ( VGS VTH) L (3.4) R 1 n W ncox ( VGS VTH) L (3.5) t d RiCi (3.6) i 3. 13 CLK 16MHz ph1 ph3 3.2ns ph2 ph3 12.5ns CLK ph1 ph2 ph3 3. 13 Clock simulation of the comparator. 3.3 Segmented Current-Mode DAC successive approximation ADC DAC ADC DAC successive approximation ADC DAC segmented 21

current-mode [3][13][14] DAC Current Switching Matrix [11] 3. 14 N-bit segmented D/A converter m coarse current source (I u ) (coarse current source) (I m ) current divider (fine currents) I out 3. 14 Basic N-bit segmented D/A converter. DAC ( MSBs ) thermometer (monotonicity) thermometer ( MSBs ) current divider ( LSBs ) V LSB DAC (monotonic) 3. 15 DAC ( V LSB ) (Non-monotonic) 3. 16 (three-way switch) 22

3. 15 Non-monotonic behavior of the DAC. 3. 16 Monotonic N-bit segmented D/A converter 3. 17 Monotonic behavior of the DAC 23

I 1 ~ I m-1 I m fine current divider 3. 17 DAC I m (segment current) I seg 3. 18 N C MSBs F LSBs 3. 18 Segmented N-bit inherently monotonic current DAC MSBs Binary-to-Thermometer thermometer LSBs 8 MSBs 4 LSBs 4 2 4 current divider 2 4 I out (=I out(coarse) +I out(fine) ) (I-V converter) V ref 24

V ref V ref OPA V DS 3. 19 P-channel N-channel R out 3. 19 N-bit bi-direction segmented DAC 8 3V 1V~2V 8 1 (sign bit) 3 (coarse) 4 (fine) 3 ( MSBs) 3 8 binary-to-thermometer 4 ( LSBs) (2-way) 25

P-channel + ( I out(coarse) I + out(fine) ) 1~V ref N-channel - ( I out(coarse) I - out(fine) ) V ref ~2V V ref V DD /2( ) 8 ( ) P-channel N-channel 3 MSBs thermometer m-1 I out(coarse) ( I out(coarse) MSBs ) m binary-weighted current divider (I seg ) binary-weighted current divider binary-weighted LSBs binary-weighted I out(fine) DAC I out I out(coarse) I out(fine) (I dump ) V ref 3. 20 3. 20 DAC P 26

M a1 ~M a8 P-channel M b1 ~M b24 M c1 ~M c16 M d1 ~M d5 current divider DAC N P-channel N-channel P-channel N-channel Integral nonlinearity (INL) error (current mirror) 3. 21 MOS V DS V GS DAC 3. 21 MOS 3.3.1 3-way switch controller segmented DAC MSBs binary-to-thermometer thermometer 2 N -1 2 N N 2 N N 3 2 27

2 3 8 binary-to-thermometer decoder Binary Code Thermometer Code B3 B2 B1 T7 T6 T5 T4 T3 T2 T1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 thermometer 1. Differential nonlinearity (DNL) error 2. (monotonicity) 3. Glitch 4 16 binary -to- thermometer 3 4 P-channel PMOS N-channel NMOS 3 P-channel (B 7 =0) B 6 B 5 B 4 Sw8 Sw7 Sw2 Sw1 0 0 0 1 1 0 1 0 1 1 0 1 1 0 1 0 0 1 0 1 1 1 1 0 1 0 1 1 0 1 0 1 0 0 1 1 0 1 1 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 0 0 1 1 0 1 1 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 0 28

4 N-channel (B 7 =1) B 6 B 5 B 4 Sw16 Sw15 Sw10 Sw9 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 1 1 1 0 0 1 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 0 0 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 0 0 1 0 I dump I out I seg 2 N *3(N ) 48 Binary-weighted current divider LSBs 3. 22 I seg V DS Binary-weighted current divider 3. 22 2-way switches circuit 29

3.3.2 I-V Converter DAC OPA OPA ( ) V ref 1.5V (3.7) R out Output_ range N 2 I unit I (3.7) Output_range I unit I N DAC I unit I HSPICE ( N, Output_range, I unit, I ) = ( 8, 1V, 1 A, 23nA ) R out 3.83k 3.3.2.1 Operational Amplifier OPA OPA OPA two - stage 3. 23 30

3. 23 Two-stage OPA OPA DAC S/H DAC (Bandwidth) slew rate (DC gain) Phase Margin ( ) (3.8) t V out( t) Vstep(1 e ) (3.8) V step V out (t) V step 1V 0.999V( 1/4 LSB) DAC (16MHz) 7 OPA 112 MHz 60dB Phase Margin 65 slew rate 3. 24 3. 24 Two-stage OPA 31

Flicker PMOS Slew Rate Unity-gain frequency (3.9)[10] ( W ( W / L) / L) 7 4 ( W 2 ( W / L) / L) 6 5 (3.9) OPA 200MHz DC gain 65.2dB Phase Margin 61.3 2mV ADC OPA OPA DAC DAC OPA S/H Buffer 705 W 5 5 OPA M1 8.1/1 M2 8.1/1 M3 4.2/1 M4 4.2/1 M5 (10/1)*2 M6 (10/1)*6 M7 (4.2/1)*6 M8 0.9/1 32

3.3.3 Simulation results of the DAC 3. 25 Simulation result of the DAC 3. 25 DAC 8 00000000 2 ~ 11111111 2 1V~2V 1 A 16 A ADC INL 3. 26 0.47 LSB DNL 3. 27 0.154 LSB 33

3. 26 DAC INL 3. 27 DAC DNL 3.4 SAR Controller N SAR [15] 3. 28 (memory register) (shift register) non - redundant successive approximation register [16] 3. 29 N 2N Flip-Flop(FF) N FF FF finite state machine (FSM) 34

3. 28 N-bit SAR 3. 29 N-bit SAR controller based on the non-redundant structure SAR start low MSB 1 0 DAC 1.5V(1/2 full scale) low MSB 0 high MSB 1 high comparator high low 8 8 6 35

1 MSB 8 LSB 6 8 SAR Conversion step D/A converter input Comparator output 0 1 0 0 0 0 0 0 0 B 7 1 B 7 1 0 0 0 0 0 0 B 6 2 B 7 B 6 1 0 0 0 0 0 B 5 3 B 7 B 6 B 5 1 0 0 0 0 B 4 4 B 7 B 6 B 5 B 4 1 0 0 0 B 3 5 B 7 B 6 B 5 B 4 B 3 1 0 0 B 2 6 B 7 B 6 B 5 B 4 B 3 B 2 1 0 B 1 7 B 7 B 6 B 5 B 4 B 3 B 2 B 1 1 B 0 Result B 7 B 6 B 5 B 4 B 3 B 2 B 1 B 0-8 non-redundant structure SAR 8 (CU) 3. 30 D-FF shift register load data hold data (3.10) BitN next) ( Hold BitN Shift Hold BitN Load Hold BitN (3.10) 3. 30 N th 36

1. ( ) 2. 3. ( OR 1 ) 3. 29 D-latch D-latch D-latch 3. 31 6 clk high V in V out clk low V out 3. 31 D-latch 37

Chapter 4 EXPERIMENTAL RESULTS TSMC 1P4M 0.35 m CMOS 3V 2.6mW 2MS/s 4.1 ADC Test Static test ADC ADC 1V~2V ramp 1. Integral Nonlinearity Error (INL) 0.82 LSB best-fit line INL 4. 1 INL 4. 1 ADC INL 2. Differential Nonlinearity Error (DNL) DNL 0.5 LSB ADC monotonic 38

DNL 0.31 LSB 4. 2 4. 2 ADC DNL Dynamic test ADC ADC 1V pp 62.5kHz 32 32 1024 MATLAB 1024 Fast Fourier transform (FFT) 4. 3 signal-to-(noise and distortion) ratio (SNDR) 43.4dB 10 20 30 40 50 60 70 80 90 100 4. 3 Output power spectrum density of the ADC 39

Effective number of bits (ENOB) 7 ENOB 4. 4 post layout simulation 7 Effective number of bits SNDR ENOB 31.25kHz 44.01dB 7 62.5kHz 43.4dB 6.9 125kHz 42.82dB 6.8 250kHz 42.9dB 6.8 4. 4 ENOB versus input frequency 4.2 Layout Arrangement poly Guard ring 40

(Poly-Metal1-Metal2) Guard ring 4. 5 4. 5 Layout arrangement I/O PAD 4. 6 4. 6 I/O PAD arrangement Layout view ( I/O PAD) 4. 7 41

350 *430 I/O PAD 4. 7 Layout view 8-bit successive approximation ADC 8 8 Experimental results of the proposed ADC Supply voltage 3V Total power dissipation < 2.6mW Technology 0.35 m CMOS Sampling rate 2MS/s Resolution 8 bits Input swing 1V INL < 0.82 LSB DNL < 0.31 LSB SNDR@ f in = 62.5KHz 43.4 db ENOB@ f in = 62.5KHz 6.9 bits Active area < 0.15mm 2 42

Chapter 5 CONCLUSIONS & FUTURE WORKS 5.1 Conclusions segmented current-mode DAC segmented current-mode DAC 3V 8-bit 2MS/s successive approximation ADC 2.6mW offset 2mV ENOB 7-bit ADC ADC successive approximation ADC 9 9 successive approximation ADC Process Resolution Sampling rate Supply voltage Power consumption Active area 1.2um[1] 8-bit 50kS/s 1V 0.34mW 3.24mm 2 3um [8] 8-bit 1.3MS/s 5V 70mW 3750mil 2 3um [9] 8-bit 5MS/s N/A 50mW 0.903mm 2 *0.35um 8-bit 2MS/s 3V 2.6mW 0.15mm 2 * ADC 5.2 Future Works 1. Low voltage design ( VDD 1 V ) 43

2. 3. BIST (Built-In Self-Test) 4. Programmable resolution 44

REFERENCES 1. S. Mortezapour, E.K.F. Lee, A 1-V, 8-bit successive approximation ADC in standard CMOS process, IEEE Journal of Solid-State Circuits, vol.35 Issue.4, pp.642-646, April 2000. 2. H. Neubauer, T. Desel, H. Hauer, A successive approximation A/D converter with 16 bit 200 ks/s in 0.6 m CMOS using self calibration and low power techniques, The 8th IEEE International Conference on Electronics Circuits and Systems, vol. 2 pp.859-862, 2001. 3. H. J. Schouwenaers, D. W. J. Greeneveld, and H. A. H. Tremeer, A low-power stereo 16-bit CMOS D/A converter for Digital Audio, IEEE Journal of Solid-State Circuits, vol.23, no.6, pp.1290-1297, December 1988. 4. C. J. B. Fayomi, G. W. Roberts, and M. Sawan, A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 m CMOS technology, The 2001 IEEE International Symposium on Circuits and Systems, vol. 1, pp.460-463, 2001. 5. S. Ogawa, K. Watanabe, A switched-capacitor successive-approximation A/D converter, IEEE Transactions on Instrumentation and Measurement, Vol.42, Issue: 4, pp.847-853, Aug. 1993. 6. Z. Zheng, U. Moon, J. Steensgaard, B. Wang, G. C. Temes, Capacitor mismatch error cancellation technique for a successive approximation A/D converter, IEEE International Symposium on Circuits and Systems, vol.2, pp.326-329, 1999. 7. KH. Hadidi, V. S. Tso, and G. C. Temes, Fast successive-approximation A/D converters, IEEE 1990 Custom Integrated Circuits Conference, pp.6.1/1-6.1/4, 1990. 8. KH. Hadidi, V. S. Tso, An 8-b 1.3-MHz successive-approximation A/D converter, IEEE Journal of Solid-State Circuits, vol. 25, Issue: 3, pp.880-885, June 1990. 45

9. K. Chen, C. Svensson, and J. Yuan, A CMOS implementation of a video-rate successive approximation A/D converter, IEEE International Symposium on Circuits and Systems, vol. 3, pp.2577-2580, 1988. 10. David A. Johns, Ken Martin, Analog integrated circuit design, John Wiley & Sons, Inc., 1997. 11. Roubik Gregorian, Introduction to CMOS OP-AMPs and comparators, Wiley-Interscience Publication, 1999. 12. Behzad Razavi, Design of analog CMOS integrated circuit, The McGraw-Hill Companies, Inc., 2000. 13. John A. Schoeff, An inherently monotonic 12 bit DAC, IEEE Journal of Solid-State Circuits, vol.sc-14, no.6, pp.904-911, December 1979. 14. D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, A self-calibration technique for monolithic high-resolution D/A converter, IEEE Journal of Solid-State Circuits, vol.24, no.6, pp.1517-1522, December 1989. 15. David F. Hoeschele, Jr., Analog-to-digital and digital-to-analog conversion techniques, Wiley-Interscience Publication, 1994. 16. A. Rossi and G. Fucili, Nonredundant successive approximation register for A/D converters, IEE of Electronics Letters, vol.32, Issue.12, pp.1055-10576, June 1996. 46

1978 3 6 ( ) ( ) 2002 VLSI Design/CAD symposium accepted, A Successive Approximation ADC based on a new segmented DAC, June, 2002. 47