Fully-Integrated Low Phase Noise Bipolar Differential VCOs at 2.9 and 4.4 GHz Ali M. Niknejad Robert G. Meyer Electronics Research Laboratory University of California at Berkeley Joo Leong Tham 1 Conexant Systems 2 Newport Beach, CA 1 The author is now with Maxim Integrated Products 2 Formerly known as Rockwell Semiconductor Systems
Outline of Presentation Project motivation Modeling on-chip inductors above 3 GHz Center-tapped inductors / differential Q Varactors above 3 GHz / MIM caps Circuit topology for low phase noise design Overall chip design & layout Summary of measured performance
3-10 GHz VCOs Project Motivation VCO key building block in RF transceivers Specs: Tuning Range, Power, and Phase Noise Power and Phase Noise directly impacted by inductor Q Fully integrated VCOs very difficult to implement Main constraint: Lack of high Q inductor Solution Realize high Q small footprint inductors > 3 GHz f T ~ 25 GHz Scaling area curtails substrate losses MIM caps smaller > 3 GHz Design low phase noise VCO w/high Q tank Divide down to convenient frequency range
High-Frequency Effects Over Si Substrate radiation proximity effects due to presence of nearby segment segments couple magnetically and electrically through oxide/air current crowding at edge due to skin effect substrate injection substrate currents: ohmic, eddy, and displacement current substrate tap nearby causes lateral currents
Summary of Loss Mechanisms Conductor losses: Series ohmic loss due to conductor resistivity Eddy current losses: Skin and proximity effects Substrate losses: Electrically induced substrate currents Magnetically induced substrate currents (bulk eddy currents) Dielectric losses Radiation losses: Radiation into air Surface waves and radiation into the substrate
Bulk Eddy Current Losses Are bulk eddy current losses significant? Negligible if ρ > 1 Ω-cm (quasi-tem) Dominant if ρ <.01 Ω-cm (skin-effect mode) Mechanism: Magnetic field penetrates bulk substrate and generates electric fields which produce currents Eddy current mechanism different from electrical substrate losses At h.f. the inductance drops significantly due to image currents 6 Spiral Series Resistance 10 Spiral Quality Factor.01 ohm-cm.001 ohm-cm 9 3.0001 ohm-cm.00001 ohm-cm 8 7 6 5 0 1 4 7 10 (GHz) 4 1 4 7 10 (GHz)
ASITIC Software http://www.eecs.berkeley.edu/~niknejad Analysis and Simulation of Inductors and Transformers for ICs A software tool for design and analysis of passive devices on Si ASITIC checked against meas. up to 14 GHz (conductive substrate) 12 inductance Q factor 8 4 0 Lmeas Lsim Qmeas Qsim -4-8 0 2 4 6 8 10 12 14 GHz Q max > 5 in absence of eddy currents!
Inductors at 2 GHz versus 10 GHz 25 20 15 10 5 0 0 2 4 6 8 10 Freq (GHz) 1 nh: R= 75µ W= 5.2µ S=2.1µ N=2 10 nh: R=150µ W=12.3µ S=2.1µ N=7.5 1 nh at 10 GHz: L=1.0n R=1.6 C s =28 R s =500 Q = 11.4, 14.9, 20.3 10 nh at 2 GHz: L=8.7n R=5.3 C s =258 R s =350 Q = 4.4, 5.1, 10.2
Inductor/Transformer Layout Geometry circular spiral inductor symmetric center-tapped balun transformer
center R=100µ w =12µ s = 3µ Center-Tapped Inductors L=2nH C=200fF R=2Ω Single-Ended & Differential Q-Factor Benefits: Windings share area so better self-resonance Don t need to worry about parasitic coupling btwn two ind Differential Q at h.f. depends heavily on substrate! Problems: Each turn accumulates additional resistance due to vias Forced to keep N < 4 18 15 12 9 6 3 0 single-ended differential circular square 0 2 4 GHz 6 8 10
Compact Circuit Model Model includes two coupled windings k C b C b r x r x C s L C s2 L C s R s R s2 R s 2.9 GHz circular design: Radius = 125µ, W=14.5µ, S=3µ, N=3, L 2 =23µ L=.9nH, r x =1.2Ω, k=.5, C b =70fF C x =28fF, R x =380 Ω, C x2 =235fF, R x2 =310 Ω Peak Differential Q = 22 at 5 GHz, 14 at 3 GHz
Varactor Q Above 3 GHz C MIM Q 1 Q 2 1V 0.5n L choke 0.5n 2V Peak Q about 18 at 5.7 GHz (C MIM =0) This is comparable to inductor Q
Differential Circuit Topology Differential operation provides better immunity from package and substrate Differential Q higher (if substrate losses dominate) Differential dividers easier to build above 3 GHz Doubles area of actives but substantially reduces area of passives (due to mutual coupling & higher Q) De-couples circuit blocks on same substrate
Oscillator Design Equations ω φ d d Steady-state conditions: RF large signal transconductance Phase delay of transconductor, transformer, and tank must add to zero Phase delay in transconductor and transformer causes oscillator frequency to differ from peak 0 1 ) ( 3 2 1 0 = + = φ φ φ ω n j Z G T ml ) ( 0 3 2 1 ω φ φ φ j Z e n v v v e G i T j o x x j ml x = = = ) ( ω j Z T 1 : n i x x v o v
Oscillator Design Procedure dφ Find highest Q inductor (optimize ) dω Split cap between transformer, load, and varactor to provide sufficient tuning range Find smallest I bias so that circuit oscillates with reasonable amplitude over process variation Optimize device size for phase noise Optimize n for best phase noise (noise match) Minimize noise from bias circuit Degen. bias current mirrors; degen. of osc. core does not help Minimize flicker noise up-conversion from bias
VCO Layout: f T =25 GHz Bipolar Process MIM caps 3 GHz Buffer Passive Coupler 1.5 GHz Buffer VCO Core Divide by 2 Feedback Inductor Bypass Caps
VCO Core Circuit V cc V tune D 1 D 2 R E11 R E12 L t variable LC tank negative R ckt C 1 C t C 2 R B1 Q 11 Q 12 constant base bias R B2 Q 1 -Q 4 current bias V bias C 4 C 3 R B4 Q 6 Q 7 Q 9 Q 5 Q 10 Q 8 R E5 R B3 R E7 R E10
VCO Core Layout 0.4µ 7µ 4 BJT 3.5-4 ma bias current 5 ma with bias current pnp mirrors varactors differential quad
Capacitor Loads and Feedback C x1 C top plate bottom plate R x C x2 r sub shield Capacitive Feedback Network: Differential Load: V o+ V o V i port 1 port 2 V i+ shield Bottom plate (shield)
Down-Conversion, Mode Locking and Division LO v LO = B cos( ω t + φ 2 LO n ) VCO Filter v VCO = C cos[( ω ± ω 2 + ω ) t + φ 1 + φ 2 ] 1 n n v VCO = A cos[( ω + ω ) t + φ 1] 1 n VCO LO VCO FF divider v Injection locked LO or PLL LO = ω VCO B cos( t + φ n1) n Note: VCO inject more power than intrinsic noise of LO v LO = B cos( ω VCO t + φ n n1 )
Vcc Divider FF Circuit 400Ω Qbar Q D Clk DBar ClkBar 1kΩ Bias 200Ω Resistor CM improves headroom 260µA total current (works up to 8 GHz with 200Ω load)
Design Summary and Predicted Performance 2.9 GHz Tank: 3nH, 500fF (varac), 450fF (MIM) 4.4 GHz Tank: 2nH, 500fF (varac), 130fF (MIM) Best predicted phase noise: -110 dbc/hz at 100 khz offset (based on 6 GHz design!) Power dissipation: 10mW (Vcc=2.4, I~4mA) Tuning Range: 7% Core swing: ~1.7V differential Base swing: ~400mV
VCO Measurement Setup VCO 4 Buff π-match Phase Noise network Analyzer 4.4 GHz LO VCO Buff π-match Phase Noise network Analyzer 2.9 GHz Phase Noise Analyzer RDL model NTS-1000B 4.4 GHz: Measured phase noise at 4 (internal FF divider) 2.9 GHz: Down-convert to 1 GHz, assume phase noise of LO is negligible
Phase Noise Measurement Results -40-50 -60-70 -80-90 -100-110 -120 offset (khz) dbc/hz1 10 100 1000 2.9 GHz: Measured phase noise of -95.2 dbc/hz at 2.9 GHz Effective: -104 dbc/hz @ 100 khz offset (1 GHz carrier) 4.4 GHz: Measured phase noise of -100.2 dbc/hz at 4 Effective: -101 dbc/hz @ 100 khz offset (1 GHz carrier)
Summary and Conclusion Center Freq. 2.9 GHz VCO 4.4 GHz Technology 25 GHz bipolar 25 GHz bipolar Substrate 10 :-cm 10 :-cm Core current 3.5 ma 4 ma Tuning Range 250 MHz (10%) 260 MHz (6%) SSB Phase Noise @100 khz offset -95.2 dbc/hz @ 2.9 GHz -100.2 dbc/hz @ 1.1 GHz Inductors above 3 GHz feasible and desirable Accurate and efficient analysis of inductors possible Differential operation beneficial over single-ended SpectreRF phase noise simulation used for optimization Measurement results close to expectations
Acknowledgements Conexant Systems, Newport Beach, CA Frank Intveld (layout) Ron Hlavac (test board) U.S. Army Research Office (Grant DAAG55-97-1-0340)