Multiple-Valued Signed-Digit Adder Using Negative Differential-Resistance Devices

IEEE TRANSACTIONS ON COMPUTERS, OL. 47, NO. 9, SEPTEMBER 1998 947 Multile-alued Signed-Digit Adder Uing Negatie Differential-Reitance Deice Alejandro F. González, Student Member, IEEE, and Pinaki Mazumder, Senior Member, IEEE Abtract Thi aer decribe a new igned-digit full adder (SDFA) circuit coniting of reonant-tunneling diode (RTD) and metal-oxide emiconductor field effect tranitor (MOSFET). The deign i rimarily baed on a multile-alued logic literal circuit that utilize the folded-back I- (alo known a negatie differential-reitance, NDR) characteritic of RTD to comactly imlement it gated tranfer function. MOS tranitor are configured in current-mode logic, where addition of two or more digit i achieed by uerimoing the ignal of indiidual wire being hyically connected at the umming node. The rooed SDFA deign ue redundant arithmetic rereentation and, therefore, the circuit can erform addition of two arbitrary ize binary number in contant time without the need for either carry roagation or carry look-ahead. The SDFA cell deign ha been erified through imulation by an augmented SPICE imulator that include new homotoy-baed conergence routine to tackle the nonlinear deice characteritic of quantum deice. From the imulation reult, the SDFA cell ha been found to erform addition oeration in 3.5 nanoecond, which i omewhat uerior to other multialued redundant arithmetic circuit reorted in the literature. The SDFA cell require only 13 MOS tranitor and one RTD, a ooed to the tate-of-the-art CMOS redundant binary adder requiring 56 tranitor, and to the conentional multialued current-mode adder coniting of 34 MOS tranitor. In order to erify the imulation reult, a rototye SDFA cell ha been fabricated uing MOSIS 2-micron CMOS roce and GaA-baed RTD connected externally to the MOSFET circuit. Index Term Signed-digit arithmetic, multile-alued logic, quantum electronic reonant-tunneling circuit.xxx F 1 INTRODUCTION I N a conentional rile-carry adder, the inut carry bit may roagate through the bank of full adder, anning from the leat ignificant digit to the mot ignificant digit. Therefore, the wort-cae roagation delay in a rile-carry adder i roortional to n, the ize of the adder. Other aroache, uch a carry look-ahead, can reduce the roagation delay to log n time at the exene of additional circuit that not only introduce irregularity in chi layout but alo render the adder circuit le amenable to comrehenie teting. The igneddigit number ytem, originally rooed in 1961 by Aizieni [1], can be ued in adder circuit to retrict carry roagation only to adjoining cell by eliminating the deendency of the carry outut function on the carry inut ignal. To retrict carry roagation, igned-digit number ytem emloy redundant rereentation, in which a number different from zero can be exreed in more than one unique way. In igneddigit adder, it i oible to erform addition of two arbitrary ize number in contant time, and redundant algorithm can, therefore, hel to ignificantly imroe the erformance of arithmetic circuit in alication with large oerand ize. Signed-digit ytem hae been adoted by many reearcher and deigner in the deeloment of high-erformance arithmetic circuit [2], [3], [4], [5], but comact and efficient imlementation of the igned-digit adder till remain omewhat eluie with the conentional deice technologie. ²²²²²²²²²²²²²²²² The author are with the Deartment of Electrical Engineering and Comuter Science, Unierity of Michigan, Ann Arbor, MI 48109. E-mail: mazum@eec.umich.edu. Manucrit receied 9 June 1997; reied 25 No. 1997. For information on obtaining rerint of thi article, leae end e-mail to: tc@comuter.org, and reference IEEECS Log Number 105233. A MOS technology i raidly adancing to it hyical limit of feature ize hrinking, it i of aramount imortance that deice engineer dicoer alternatie enabling technologie that may emloy radically different deice tranortation henomena, uch a quantum tunneling through multile barrier tructure, ingle-electroncontrolled charge tranfer oer the coulombian blockade, charge tranfer oer comlex molecular tructure, and DNA comuting. Among a hot of nacent technologie that eem to be extremely romiing, quantum electronic reonant-tunneling deice, uch a reonant-tunneling diode (RTD) [6], reonant-tunneling hot electron tranitor (RHET) [7], reonant-tunneling biolar tranitor (RTBT) [8], bound-tate reonant-tunneling tranitor (BSRTT) [9], etc., are the mot mature and aear to be imminently iable for commercial introduction. Thee deice can oerate at room temerature and they are comatible with conentional technologie uch a heterojunction biolar tranitor (HBT) [10], [11], and high-electron mobility tranitor (HEMT) [12], [13]. The nonlinear tunneling characteritic of thee deice can be efficiently harneed to deign multile-alued circuit requiring fewer actie deice and le amount of connecting wire between them. Interconnect will redominantly goern the circuit eed in future gargantuan multibillion tranitor monolithic integrated chi. Multile-alued logic (ML) can alleiate the interconnect delay and routing comlexitie ince multialued ignal coney more information than binary ignal, thu requiring le amount of interconnect to tranmit imilar bandwidth of information [14], [15]. In a igned-digit arithmetic ytem, multialued ignal leel are ued to erform the arithmetic 0018-9340/98/$10.00 1998 IEEE

948 IEEE TRANSACTIONS ON COMPUTERS, OL. 47, NO. 9, SEPTEMBER 1998 function much more comactly than the conentional binary arithmetic ytem. Reonant-tunneling deice are inherently bitable deice caable of retaining the outut tate after the inut ignal change their alue. Thi roerty enable the circuit deigner to deelo deely ielined (what i termed a nanoielining) circuit where each gate behae a a bitable latch. Thi noel feature allow the circuit to obtain much higher eed and throughut. In addition to nanoielining caability, reonant-tunneling deice can be tacked together ertically to deelo multitate memorie and multialued logic gate [14], [16], [17], [18], [19]. Thi aer reent a multile-alued igned-digit full adder coniting of reonant-tunneling diode (RTD) and MOS tranitor. The rooed circuit i built comactly uing only 13 MOS tranitor and one two-eak RTD, in comarion to 56 tranitor required by Makino et al. well-known CMOS redundant binary adder [3], and to 34 deice required by an efficient multialued current-mode MOS adder rooed by Kawahito et al. [20]. The igneddigit adder in thi aer imlement a radix-2 arithmetic ytem that ue ternary digit et {-1, 0, 1}. In order to obtain a good noie erformance, a three-alued logic ytem i ued. A mocku rototye of the adder circuit wa fabricated uing MOSIS 2-micron CMOS roce technology and the RTD were externally added, ince iliconized RTD are not yet ready for cointegration with the tandard CMOS technologie. The circuit ha been teted to erify it functionality and it meaured outut waeform were matched with it imulated outut reone. At reent, RTD and other quantum tunneling deice are rimarily baed on comound-emiconductor uch a gallium arenide (GaA) and indium hohide (InP). Currently, RTD cannot be integrated with MOS deice, but igorou effort are being made to monolithically integrate RTD and ilicon MOS tranitor. One of the aroache being urued conit of deeloing NDR deice made of ilicon germanium (SiGe), which i comatible with ilicon technology [21], [22]. Another aroach [23] inole lifting off RTD from GaA wafer and then bonding them onto a ilicon hot ubtrate. The ret of thi aer i organized a follow. Section 2 decribe the rincile of oeration of the rooed igneddigit adder deign. Section 3 then analyze the MOS/RTDbaed multialued literal circuit, which i the centeriece of the rooed igned-digit adder. In Section 4, imulation and exerimental reult are reented. Concluion are made in Section 5, giing a comarion of the rooed adder deign along with ome other fat adder circuit. 2 SIGNED-DIGIT FULL ADDER CIRCUIT DESIGN Thi ection decribe the oeration of the rooed igneddigit full adder (SDFA) circuit. Firt, the required tranfer characteritic for a three-alued arithmetic (radix-2) will be decribed. The circuit imlementation of the identified tranfer function will then be reented. It wa found that RTD, in conjunction with CMOS deice, offer imortant benefit in term of circuit comactne in two way. Firt, CMOS deice are ery ueful in a current-mode logic with Fig. 1. Block digram of the imlemented totally-arallel addition aroach. wired-ummation of digit that ae circuit area. Second, the folded I- characteritic of the RTD can be utilized to build high functionality literal gate which can be ut together to form multile-alued logic adder, enabling the enuing RTD-baed adder deign to be een more comact. 2.1 Tranfer Characteritic Fig. 1 deict a block diagram of the igned-digit addition aroach rooed in thi work. Line x i, y i, c i, w i, and i are three-alued, current-mode ignal. Addition of x i and y i i achieed by imle wired-ummation of current. The function of the SDFA block i to conert the ummation of inut ignal, z, to a two-digit rereentation of the um gien by digit c and w, that i, rc w = z where r = 2. The final um outut, i, i obtained by current-addition of the interim um outut, w i, and the incoming carry ignal, c i - 1. Thi addition aroach correond to the igned-digit addition rooed by Aizieni in [1]. According to igneddigit arithmetic theory, the radix alue hould meet the condition r > 2. In thi cae, r = 2, howeer, which lead to the imlementation of a modified igned-digit arithmetic [1]. An imortant characteritic of the modified igned-digit arithmetic i that the SDFA block require a inut both it correonding inut ignal, z, and the inut to the next leignificant adder lice, z i - 1. The ue of inut z i - 1 in the SDFA cell i exlained next. The tranfer function of the SDFA block are defined o that w and c alway rereent the arithmetic alue of x y. Fig. 2 how the tranfer function for the interim um, w, and the carry, c, ignal in the SDFA cell. All the digit in the grah are oitie becaue the circuit will ue only oitie current. In thi cae, the igned-digit 0 i rereented by a current leel 3, digit -2 i rereented by current 1, and o on. There are two air of tranfer function, and the

GONZÁLEZ AND MAZUMDER: MULTIPLE-ALUED SIGNED-DIGIT ADDER USING NEGATIE DIFFERENTIAL-RESISTANCE DEICES 949 Fig. 2. Tranfer function of the SDFA block. working air i elected by the alue of z i - 1. Thi inut ignal i ued to determine if c i - 1-1, which indicate when the SDFA cell i allowed to generate an outut w = -1 without cauing inalid current leel to be roduced. If the inut z i - 1 to the reiou digit wa not conidered, then it would be oible to generate w = -1 or w = 1 when c i - 1 = -1 or c i - 1 = 1, reectiely. In thee cae, the final um reult would be = -2 or = 2, which are inalid outut for the elected radix. Careful oberation of the SDFA tranfer characteritic how that three multile-alued literal ignal can be ued to decribe the adder function. A een in Fig. 2, literal lit1, lit2, and lit3 contain all the witching information required to define outut function w and c. Thi oberation form the bai of the rooed SDFA cell deign, whoe block diagram i deicted in Fig. 3. The inut to the ytem i the wired ummation current ignal i z. The three required literal ignal are then generated in different block of the circuit. The literal ignal are ued to control witched current ource, which, in turn, yntheize the SDFA tranfer function in the current outut generator block. Pleae note Fig. 3. Block diagram of the rooed SDFA cell. that the outut block ue inut ignal a to determine which of the two et of tranfer characteritic hould be ued. a indicate if z i - 1 < -1 and, to our adantage, it behaior i identical to literal lit2. 2.2 Literal Circuit Imlementation Let u begin the decrition of the SDFA circuit by dicuing the imlementation of ignal lit1 uing RTD. Fig. 4 how the baic circuit ued for generating the literal ignal. A een in the figure, the circuit conit of a erial connection of a reitor R and an RTD, where the RTD erform a a load element. The inut to the circuit i the oltage z, which rereent the wired ummation z = x y. In the cae of lit1, two RTD are ued in erie to obtain an equialent two-eak characteritic. The CMOS inerter i ued to ene the oltage at the node connecting the RTD and the reitor ( node ). The rooed literal circuit i imilar to the one reented in [14]; howeer, the rooed deign ue a comlete CMOS inerter intead of a aie-load inerter. The behaior of the oltage node i decribed uing the load-line method (deicted in Fig. 5a and 5b). The I- characteritic of the RTD and the reitor are lotted a the current I that flow through them with reect to the oltage node. The alue of the current I i found at the oint of interection of the I- cure. The oerating oint of the circuit change a the inut oltage z i increaed becaue the I- cure of the RTD i moed to the right a z increae. There are oint where the current I uddenly decreae with increaing z due to the folded I- characteritic of RTD. Fig. 5b, how a low-current oerating oint occurring after a tranition from a high-current oint (hown in Fig. 5a). Since the oltage node i roortional to the current I, the tranition in I are directly reflected in node. Fig. 5c dilay the ideal behaior of node obtained uing the load-line method.

950 IEEE TRANSACTIONS ON COMPUTERS, OL. 47, NO. 9, SEPTEMBER 1998 (a) Fig. 4. Comact literal circuit uing RTD and CMOS deice. The CMOS inerter i ued to ene node and, then, generate the tranfer characteritic of lit1 uing the threhold of the gate (ee Fig. 5c). The CMOS inerter can be thought of a a buffer/quantizer of the RTD-reitor oltage characteritic. The CMOS gate offer a ery imortant adantage to the literal circuit: a high inut reitance that reent the alteration of the RTD characteritic caued by draining DC current from the node node. Fig. 5c deict the formation of the literal ignal lit1 by ening node. Obere that the alue of z where the negatie tranition oint of literal lit1 take lace deend on the alue of the threhold oltage of the inerter ( T ). A een in Fig. 2, literal lit2 and lit3 are imler than literal lit1. Conequently, imlementing them i eaier than imlementing lit1 and no RTD are required. Function lit2 and lit3 correond to threhold detector whoe threhold leel hould match the witching oint of the carry outut function, c, for z i - 1-1. Fig. 7 how the imlementation of literal lit2 and lit3 by mean of two reitor connected in erie. The ratio between the alue of the two reitor for each literal determine the correonding witching threhold leel. 2.3 Outut Current Circuit The generation of the SDFA tranfer function by mean of literal ignal lit1, lit2, lit3 i now dicued. The behaior of the literal wa conceied with the uroe of achieing a imle imlementation of the current outut block. The aroach conit of uing the four controlling ignal (three literal and a ) to actiate witched current ource. Thee current ource are imlemented with MOS deice. Fig. 6 how the current outut generator circuit. Imlementing outut w require only three MOS tranitor and two control inut ignal (ee Fig. 6a). The interim um circuit owe it imlicity to the imilarity between the form of function w and literal lit1. Tranitor m1 inject a current equialent to one logic leel when lit1 i high. Thee tate correond to z = 1, 3, 5 in the tranfer function (b) (c) Fig. 5. (a), (b) Alication of the load-line method in decribing the behaior of oltage node. (c) Ideal rereentation of the ue of the CMOS inerter in the formation of lit1. hown in Fig. 2. The oerating oint for z = 2, 4 are handled by tranitor m2 and m3, which inject a current equialent to two logic leel or no current at all, deending uon the alue of a.

GONZÁLEZ AND MAZUMDER: MULTIPLE-ALUED SIGNED-DIGIT ADDER USING NEGATIE DIFFERENTIAL-RESISTANCE DEICES 951 (a) (b) Fig. 6. Circuit for generating the (a) interim um and the (b) carry outut function. Fig. 7. Comlete SDFA cell circuit. The circuit for imlementing function c i hown in Fig. 6b. In thi circuit, tranitor m1 and m2 roduce the baic tairway form of the carry function for the cae z i - 1-1 (a deicted in Fig. 2). Tranitor m3 and m4 are ued to generate the correct carry outut current z i - 1 > -1 by injecting one logic leel of current at the oerating oint where the two cae of the outut function c are different (z = 2, 4). Pleae note that lit1 control thee oerating oint becaue they coincide with the zero-leel oint of thi literal ignal. Alo note that the current outut function generated by the decribed circuit are not identical to the ideal tranfer function hown in Fig. 2. The difference lie in the current outut leel. While the ideal tranfer function wee current leel 2, 3, and 4, the gien outut circuit generate ignal that wee leel 0, 1, and 2. Thi rereent no roblem at all. Since only oitie current ignal are ued, it i alway neceary to erform a hift correction after eery wired-addition, and the amount of thi correction i maller if the lowet current leel oible are ued. Fig. 7 how a diagram of the SDFA circuit. 3 TRANSIENT ANALYSIS OF MULTIALUED LITERAL CIRCUIT In thi ection, we analyze the roagation delay of the RTD-baed literal circuit. A exected, the roagation delay i a function of the erie reitance, R, and the RTD characteritic. The analyi yield the bet alue of the reitance R for otimal roagation delay. A iecewie linear RTD model, hown in Fig. 8, i aumed in the analyi.

952 IEEE TRANSACTIONS ON COMPUTERS, OL. 47, NO. 9, SEPTEMBER 1998 Fig. 8. Piecewie linear current-oltage RTD characteritic ued in analyi. Obering Fig. 5b, one can ee that, in order to hae a har tranition in node, R < R n where R n i the negatie differential-reitance of the RTD. From the RTD model, R n can be written a R n = I - -, I where and are the eak and alley oltage, reectiely, and I and I are the correonding eak and alley current. In the gien reitor-rtd toology, the maximum outut oltage i gien by the roduct of the eak current of the RTD and the alue of the reitor, that i, node(max) = I R. On the other hand, we jut aw that Therefore, node R < I - - I 0 I max5 = -. I - I. (1) Auming a high eak-to-alley ratio (I I ), node(max) can be exreed a node(max) -. (2) A high alue of node(max) i needed to witch the CMOS inerter becaue node ha to be larger than the threhold of the inerter, T. Therefore, from (2), - hould be high. At the ame time, from (1), ( - ) R. Hence, R will hae to be large, too, which hel to imroe inut reitance. Howeer, large - i a limiting factor for RTD and inut oltage range. In thi articular deign, the RTD characteritic were redetermined by the roce and the roblem conited in electing R. Table 1 decribe the characteritic arameter of the RTD which were ued in the analyi. In the table, Second oltage i defined a the oltage 2 > for which the current through the RTD i exactly I. C be1 through C be3 are intrinic araitic caacitance acro the RTD in the three region of oeration of TABLE 1 RTD PARAMETERS Parameter Symbol alue Peak oltage 0.3 Peak Current I 7.0 ma alley oltage 0.6 alley Current I 0.7 ma Second oltage 2 1.0 Peak-to-alley Current Ratio PCR = I /I 10 oltage Difference = 2-0.7 Firt Poitie Reitance R 1 I 42.9 W Negatie Differential Reitance - R n = I -I -47.6 W Second Poitie Reitance R 2-2 I -I 63.5 W Caacitance in PDR1 region C be1 3 ff Caacitance in NDR region C be2 3 ff Caacitance in PDR2 region C be3 2 ff the deice. It i imortant to note that the alue of the current and caacitance arameter are determined by the ize of the RTD. Dynamic hyterei i a ery imortant factor in the election of R. Dynamic hyterei i the hifting of the RTD I- characteritic for a dynamic inut ignal due to the dilacement current flowing through the araitic caacitor C be [24]. The amount of hifting (hyterei) i larger in the NDR region than in the oitie differential-reitance (PDR) region becaue the current flowing through the RTD decreae, while the dilacement current tend to increae due to a oitie lew rate inut. The effect of dynamic hyterei can be exreed a a delay between the exected DC I- characteritic and the tranient reone for a gien oitie lew rate inut. The amount of thi delay and it relation to the alue of R can be calculated by erforming the correonding tranient analyi of the circuit. Fig. 9 deict the equialent circuit for each of the oerating region of the RTD. Pleae note that the iecewie linear model of the RTD wa ued. In the diagram, C g i the load caacitance reented by the CMOS inerter of the literal circuit. With the excetion of R n, for which the negatie ign i written exlicitly in the circuit chematic, the circuit element are aigned according to the RTD arameter reented in Table 1. In order to find the delay at node, it i neceary to obtain the time t dynamic when I R = (I - I )/2 in the NDR region of oeration (Fig. 9c). Thi oerating oint i elected becaue it gie the wort cae delay. The delay time t delay i obtained by comaring the tranient time t dynamic with the tatic time t tatic. That i, t delay = t dynamic - t tatic, where t tatic i the delay for the current to reach the ame oerating oint in the tatic equialent of the circuit (without araitic caacitance). The tranient reone analyi of the circuit i done in two art. The firt art i for the firt PDR region of oeration of the RTD, which i modeled by the circuit hown in Fig. 9b. Analyzing the firt region of oeration allow the calculation of the tranient time when the current through the RTD reache I. Thi information i ued to obtain the initial condition required in the econd art of the analyi. The

GONZÁLEZ AND MAZUMDER: MULTIPLE-ALUED SIGNED-DIGIT ADDER USING NEGATIE DIFFERENTIAL-RESISTANCE DEICES 953 (a) (b) econd art i done for the NDR region of oeration of the RTD, whoe equialent circuit i hown in Fig. 9c. In thi art, the delay time t dynamic, u to the oerating oint of interet (I R = (I I )/2), i obtained. The firt art of the analyi (PDR region) i done a follow. Pleae refer to Fig. 9b for thi dicuion. The tranient reone i analyzed by oling the node equation for node in time. The flow of current at node i written a z05 t - node05 t d C R be1 dt 4 z05 t - node05 t 9 = 1 (c) (d) Fig. 9. Circuit ued in the reitor-rtd circuit tranient analyi. (a) Original circuit. Equialent circuit in the (b) firt PDR region, (c) NDR region, and (d) econd PDR region. 05 2 057 node t C d R g dt node t. (3) A mentioned reiouly, the inut ignal z i aumed to be a ram with lew rate S R, that i, z (t) = S R t. (4) Soling the linear differential equation (3) with (4) and the initial condition node (0) = 0 yield the following exreion for node : node where RS Rt 05 t = R R 1 SR R R R C R C C R 4 g 1 be19 t - # e R R 4 - - a 1 1 9, (5) 1! R R 1 1 a 1 = R1R Cg Cbe1 4 9. To find the initial condition for the econd art of the analyi, (5) i ued to ole z (t a ) - node (t a ) =, where t a i the time at which the RTD enter the NDR region of oeration. Uing t a, the final alue, za, of the inut ignal when the oeration of the circuit leae the PDR region ( za = S R t a ) i determined. za i the initial alue for the inut ariable z in the econd art of the analyi. The econd art of the analyi i erformed in a imilar fahion. In order to make thing more imle, a new time reference i ued. Conidering thi aumtion and the reiou reult, the inut ariable i exreed a " $ #

954 IEEE TRANSACTIONS ON COMPUTERS, OL. 47, NO. 9, SEPTEMBER 1998 z (t) = S R t za. (6) The chematic diagram in Fig. 9c deict the equialent circuit for the NDR region of oeration. A negatie ign i written for the negatie differential-reitor, and the analyi i erformed accordingly. Thi i done with the uroe of making the negatie reitor more exlicit. R n in thi cae i the abolute alue of the negatie differential-reitance reented in Table 1. It i now eay to obtain the differential equation decribing the oeration of the circuit at node : d I C dt t t z t -node t - be2 2 z05- node057 05 05 = -Rn node05 t C d R g dt node05 t. (7) Thi equation i oled uing the initial condition node (0) = za -, which yield R SRt za node05 2 7 t = R - R where n R n 4 g be 9" 2 # n n! $ # a2t Rn 2 1 - e - - - R R e a t 4 9 za, (8) n R R R I R S R C SRR C C n - R n be2 R - R R - R n a 2 = RR n Cg Cbe2 4 9. Exreion (8) i ued to calculate the time t b when the current through the RTD/reitor reache the oerating oint of interet ( IR = ( I I ) 2). Thi time i obtained by oling t I I node27 b =. R 2 The dynamic time i calculated a t dynamic = t a t b. To calculate t tatic, a imilar tye of analyi in two te i done. The only difference i that the calculation i for the DC tranfer characteritic of the RTD, hence, the araitic caacitor are eliminated. The delay time i calculated a the difference between dynamic and tatic time: t delay = t dynamic - t tatic. Analyzing the dynamic hyterei i ueful in finding the bet alue for the reitor R. Since it i not oible to obtain a cloed form olution for t delay, comuter tool were ued to lot t delay for eeral alue of R. Fig. 10 how the grah obtained for the gien RTD characteritic uing the method decribed. The exeriment howed that t b i alway ery mall becaue the tranient of node in the NDR region i ery har. Therefore, the delay time i redominantly determined by the time, t a, taken to reach IR = I. The criteria for electing R i a trade-off between the delay and the inut reitance of the literal circuit. While it i neceary to minimize the delay of the configuration, it i alo neceary to maximize the inut reitance. The highet alue of R uch that the delay i not harly increaed i Fig. 10. RTD-baed literal circuit delay with reect to R. then elected (Fig. 10). Uing thi criteria and the grah, R 35 ohm i conidered a reaonable alue. Pleae note that the inut reitance of the literal circuit i gien by the um of R and the oitie reitance of the RTD. 4 RESULTS Thi ection decribe the imulation exeriment aimed at erifying and ealuating the rooed SDFA deign. It alo reent the rototye teting reult and ome of the iue related to the imlementation of the rototye. 4.1 Simulation The rooed SDFA circuit wa erified uing NDR-SPICE [25], [26], [27]. Thi circuit imulation tool include SPICE model for RTD and other NDR deice. The imulator alo make ue of ecial conergence routine that eliminate fale ocillation and other conergence roblem that arie when imulating NDR-baed circuit with conentional circuit imulator. Fig. 11a how a tranient analyi outut trace obtained from a imulation of the SDFA circuit. Thi imulation exeriment include both cae for inut a : z i - 1-1 and z i - 1 > -1. Another imortant characteritic of thi exeriment i that the inut ignal i a ram. Thi tye of inut i ueful for tudying the tranfer characteritic of the circuit, including noie margin and identification of logic leel. Performance figure uch a ower conumtion and eed are etimated by mean of a econd imulation exeriment. In the econd exeriment, the inut ignal ha fat tranient in order to aoid contribution of the inut ignal rie and fall time to the delay meaured at the outut. In the econd exeriment, the inut ignal z i teed through it different logic leel, which were determined in the firt exeriment. The imulation trace obtained in the econd exeriment are hown in Fig. 11b. Thee trace how a good matching of circuit oeration with reect to the deired SDFA function hown in Fig. 2. Table 2 ummarize the reult of the meaurement for both imulation exeriment. The noie margin wa meaured in the firt exeriment with reect to the leat wide

GONZÁLEZ AND MAZUMDER: MULTIPLE-ALUED SIGNED-DIGIT ADDER USING NEGATIE DIFFERENTIAL-RESISTANCE DEICES 955 (a) (b) Fig. 11. Circuit imulation trace for the (a) firt and the (b) econd exeriment. ule in outut ignal w (a hown in Fig. 11a). The leel i a and i b of inut ignal z at 50 ercent of each tranition of the elected ule of w are meaured. The noie margin i obtained by auming that the oerating oint i at the middle of the elected outut ule. Hence, the noie margin i half of the difference between the meaured current alue of ignal z, that i, NM = i a - i b /2. The alue of ower diiation gien in Table 2 wa obtained in the econd imulation exeriment (Fig. 11b). The frequency of oeration affect the alue of the meaured ower diiation. Finally, the delay of the circuit wa meaured a the time elaed between 50 ercent of the tranition in the inut ignal, z, and 50 ercent of the reulting tranition in the outut ignal (in the econd exeriment). Both riing and falling delay were meaured, but only the wort cae (riing) reult i gien. A good characteritic of the rooed aroach i that it will be able to take adantage of the rogre in CMOS technology. For intance, the delay alue will decreae a the circuit i imlemented with more adanced CMOS rocee. 4.2 Prototye Imlementation It wa imortant to imlement a working rototye in order to demontrate the rooed rincile of oeration.

956 IEEE TRANSACTIONS ON COMPUTERS, OL. 47, NO. 9, SEPTEMBER 1998 TABLE 2 SDFA CIRCUIT SIMULATION RESULTS Parameter Noie Margin Power Diiation Delay (um) Delay (carry) alue 0.15 ma 2.3 mw 3.5 n 2.5 n With thi uroe in mind, a mall tet circuit wa deigned uing a tandard 2-micron CMOS roce. Thi being the initial effort in the contruction of a rototye and functional teting being the main objectie, the RTD and reitor element were connected a dicrete external deice to the CMOS tet chi. It wa neceary to make modification on the rototye due to incomatibilitie in the characteritic of the CMOS deice and the aailable RTD. Baed on (2) and Table 1, the highet oltage that can be roduced at node, in Fig. 4, i 0.3 olt. Thi oltage i ery low comared to the aroximately 2.5-olt threhold of an inerter in the aailable CMOS roce, where DD = 5 olt. In the future, RTD and CMOS characteritic will be brought cloer together by CMOS caling and the ue of lower ower uly oltage. Howeer, gien the hyical limitation of MOS deice, it will alo be neceary to modify the characteritic of RTD. For the SDFA rototye, it wa neceary to modify the imlementation a follow. The modification conited of relacing the inerter of all the literal circuit by a oltage comarator, a hown in Fig. 12a. Fig. 12b how the comarator circuit ued in the SDFA rototye. Thi i not the mot comact otion for oling the roblem, but it i the mot flexible. Intead of altering the threhold oltage of the inerter by uing circuit technique, uch a relacing the PMOS tranitor of the inerter by a reitie load, the deign allow for the imlementation of an adjutable threhold oltage through an external reference, ref. Thi aroach ha the diadantage of uing more tranitor and a reference oltage. Howeer, it roide the imortant benefit of increaed flexibility. Therefore, the ue of a comarator i conidered adantageou and aroriate for the tet chi rototye. Neerthele, mature imlementation will ue the imle inerter. Another oible modification of the SDFA rototye i motiated by the need for uniformity of the deice in the current outut generator module. An imortant difference between the interim um and carry circuit hown in Fig. 6 lie in the tye of MOS deice they ue. While the carry circuit ue only one tye of tranitor, the interim um ue both NMOS and PMOS deice. Uing only one tye of tranitor gie the carry circuit two adantage. Firt, the witching time of the deice are more uniform. And, econd, there i a better control of the current outut leel becaue there are no different tranconductance alue for different tye of deice. If a w current generator uing only PMOS deice wa required, it would then be neceary to inert two inerter in the SDFA circuit to generate the comlement of literal ignal lit1 and lit2. In the tet chi, one of the SDFA cell rototye wa built uing thi aroach. The microhotograh of the chi i hown in Fig. 13b. Fig. 13a how a microhotograh of the imle SDFA (a) (b) Fig. 12. Modification for rototye imlementation. (a) Modified circuit for generating lit1. (b) Detailed comarator circuit diagram. cell which require a reduced number of tranitor by uing the interim um current generator which combine NMOS and PMOS tranitor. In both erion of the rototye, inerter were relaced by oltage comarator, a decribed in the reiou aragrah. 4.3 Exerimental Reult Since the main objectie of the rototye i to demontrate the functionality of the SDFA cell, an exeriment to how the tranfer characteritic of the circuit wa erformed. Thee tranfer characteritic were obtained by feeding the inut of the circuit with a ram ignal of ery low lew-rate. The exeriment wa done uing the econd erion of the SDFA cell (Fig. 13b). The ocillocoe trace obtained in the exeriment are hown in Fig. 14. In general, the form of the meaured outut function agree with the exected circuit behaior hown in Fig. 11. Pleae note that the exeriment i diided into two art with reect to the alue of a. The trace labeled node reflect the oeration of the RTD and correond to the exected behaior een in Fig. 5c. Alo note that the behaior of literal lit2 i indeendent of the alue of a. The lat two trace how the tranfer characteritic for the outut function, w and c, of the SDFA cell. Ob- ere how the outut characteritic are elected by a. There i a difference in the alue of the outut current leel between the meaured characteritic and their exected

GONZÁLEZ AND MAZUMDER: MULTIPLE-ALUED SIGNED-DIGIT ADDER USING NEGATIE DIFFERENTIAL-RESISTANCE DEICES 957 (a) (b) Fig. 13. Microhotograh of the fabricated tet chi. Fig. 14 Ocillocoe trace howing the oeration of the igned-digit adder tet circuit at low frequency. alue. While the exected outut current for logic leel -1, 0, and 1 are 0.0, 0.5, and 1.0 milliamere, reectiely, the meaured current leel are 0.0, 0.2, and 0.4 milliamere (Fig. 14). Thi alteration of the current leel i due, in art, to a reduction in the tranconductance of the PMOS deice from 20.563 ma/ 2 in the SPICE model ued for the imulation, to 16.129 ma/ 2 meaured for the actual CMOS run of the tet chi. Another reaon for the difference in outut leel i due to the method ued for meauring the outut current. In the exeriment, a reitie load wa connected to the outut in order to conert the current ignal into oltage ignal that could be dilayed by the ocillocoe. 5 CONCLUSIONS Thi aer reent a new multile-alued igned-digit adder circuit that combine, for the firt time, reonanttunneling diode (RTD) with MOS field-effect tranitor. RTD roide high functionality for comact multilealued logic imlementation, and MOS tranitor enable efficient arithmetic circuit deign through current-mode oeration. The rincile of oeration of the rooed circuit wa demontrated uing circuit imulation and alo through a rototye fabrication where the GaA-baed quantum tunneling deice were not cointegrated with monolithically fabricated MOSFET deice. RTD were externally added to erify the correctne of the SDFA oeration a redicted by the imulation model. The main adantage of the rooed deign when comared to other redundant adder imlementation i comactne, which i rimarily due to the nonlinear characteritic of RTD that enabled u to obtain three literal function ery efficiently. Alo, current-mode of circuit oeration, in which digit are ummed by merely connecting their wire together [28], enabled u to reduce the tranitor count. The number of deice i ued a an etimate of the ize of the circuit. Thi criterion i baed on the fact that

958 IEEE TRANSACTIONS ON COMPUTERS, OL. 47, NO. 9, SEPTEMBER 1998 TABLE 3 SDFA CELL COMPARED WITH OTHER IMPLEMENTATIONS Deign Ref Delay (n) Deice Count Redundant Binary Adder Cell [3] 0.89 56 Current-Mode Multile-alued [20] 7.0 34 Prooed SDFA 3.5 19 current technologie allow reitor with ize equialent to thoe of tranitor. Uing only 13 CMOS tranitor, fie reitor, and a two-eak RTD, the total number of actie and aie deice ued in the SDFA circuit i only 19. The binary-alued counterart of a radix-2 igned-digit adder i a redundant binary adder (RBA) cell uually imlemented with CMOS logic. The functionality of the RBA cell i ery imilar to that of the igned-digit adder. The main difference i that the multialued igned digit are rereented by air of binary ignal in the RBA cell. Many RBA deign hae been deeloed, and contant refinement are being tried out to imroe the erformance. The fatet redundant binary adder cell i decribed in [3], which alo reent a mall urey of reiou work on RBA cell deign. The comactne of the rooed igneddigit adder deign comare ery well againt Makino RBA cell that require about 56 MOS tranitor [3], a ooed to only 19 deice ued in thi aer. In term of eed, howeer, the RBA cell imlementation ha an aarent adantage. The reorted delay of the RBA cell i 0.89 nanoecond, while the rooed SDFA i etimated to hae about 3.5 nanoecond for the wort-cae delay (ee Table 2). Thi difference in eed erformance i rimarily due to the fact that our igned-digit adder wa deeloed uing a 2-micron CMOS roce, while the reult reented in [3] are baed on a 0.5-micron roce technology. Another current-mode, multile-alued logic imlementation of the radix-2 igned-digit adder cell wa reented in [20] by Kawahito et al. Their igned digit adder ue 34 MOS tranitor and ha an etimated delay of 7 nanoecond. Een though Kawahito et al. fabricated a rototye uing a 10- micron roce, the imulation-baed delay etimation wa obtained for a 2-micron roce. Table 3 reent a comarion of the rooed igned-digit adder with other fat imlementation of adder cell uing both binary and multialued logic. Finally, thi aer demontrate that emerging quantum technologie which are going to be cointegrated with redominant emiconductor technologie uch a CMOS, HBT, and HEMT will uh the frontier of high-eed arithmetic and ignal-roceing LSI circuit beyond the realm of conentional technologie. Reonant-tunneling deice, uch a RTD, RTBT, RHEMT, RHET, etc., hae eeral intrinic adantage that can be exloited to deign fater digital logic gate. Their nonlinear, folded-back characteritic will enable the circuit deigner to imlement comlex function ery comactly. RTD bitable roerty will be ueful in building nanoielined logic gate ery eaily, and it deice eed and mall caacitance will allow the deigner to ubtitute RTD for bulkier PMOS ull-u deice, thereby imroing the circuit eed by dint of trimming down the load caacitance. Multialued function are alo eay to imlement by RTD and thi aer will encourage the reearcher in the multialued logic field to deelo many other comact multialued gate by uing a combination of RTD and conentional deice. ACKNOWLEDGMENTS Thi work wa uorted by the U.S. Army Reearch Office under the MURI rogram, by DARPA, and by the U.S. National Science Foundation. REFERENCES [1] A. Aizieni, Signed-Digit Number Rereentation for Fat Parallel Arithmetic, IRE Tran. Electronic Comuter, ol. 10,. 389-400, Set. 1961. [2] S. Kawahito, M. Kameyama, T. Higuchi, and H. Yamada, A 32 32-Bit Multilier Uing Multile-alued MOS Current-Mode Circuit, IEEE J. Solid State Circuit, ol. 23,. 124-132, Feb. 1988. [3] [4] [5] [6] [7] [8] [9] H. Makino, Y. Nakae, H. Suuki, H. Morinaka, H. Shinohara, and K. Mahiko, An 8.8-n 54 54-Bit Multilier with High Seed Redundant Binary Architecture, IEEE J. Solid State Circuit, ol. 31,. 773-783, June 1996. M. Kameyama, T. Seikibe, and T. Higuchi, Highly Parallel Reidue Arithmetic Chi Baed on Multile-alued Bidirectional Current-Mode Logic, IEEE J. Solid State Circuit, ol. 24,. 1,404-1,411, Oct. 1989. M. Kameyama, M. Nomura, and T. Higuchi, Modular Deign of Multile-alued Arithmetic LSI Sytem Uing Signed-Digit Number Sytem, Proc. Int l Sym. Multile-alued Logic,. 355-362, 1990. L.L. Chang, L. Eaki, and R. Tu, Reonant Tunneling in Semiconductor Double Barrier, Alied Phyic Letter, ol. 24,. 593-595, 1974. N. Yokoyama, S. Muto, H. Ohnihi, K. Inamura, T. Mori, and T. Inata, Reonant Tunneling Hot Electron Tranitor (RHET), Phyic of Quantum Electron Deice, F. Caao, ed., chater 8,. 253-270. Sringer-erlag, 1990. A.C. Seabaugh, E.A. Beam, A.H. Taddiken, J.N. Randall, and Y.-C. Kao, Co-Integration of Reonant Tunneling and Double Heterojunction Biolar Tranitor on InP, IEEE Electron Deice Letter, ol. 14,. 472-474, Oct. 1993. G.I. Haddad, U.K. Reddy, J.P. Sun, and R.K. Main, Bound-State Reonant Tunneling Tranitor (BSRTT): Fabrication, D.C. I- Characteritic and High-Frequency Proertie, Suerlattice and Microtructure, ol. 7, no. 4,. 369-374, 1990. [10] W.P. Dumke, J.M. Woodall, and.l. Rideout, GaA-GaAlA heterojunction Tranitor for High Frquency Oeration, Solid State Electronic, ol. 15,. 1,329-1,334, Dec. 1972. [11] H. Kroemer, Heterotructure Biolar Tranitor and Integrated Circuit, Proc. IEEE, ol. 7,. 13-25, Jan. 1982. [12] R. Dingle, H.L. Störmer, A.C. Goard, and W. Wiegmann, Electron Mobilitie in Modulation-Doed Semiconduction Heterojunction Suerlattice, Alied Phyic Letter, ol. 33,. 665-667, Oct. 1978. [13] T. Mimura, S. Hiyamiza, T. Fujii, and K. Namba, A New Field- Effect Tranitor with Selectiely Doed GaA/n-Al x GA 1 - x A Heterojunction, Jaanee J. Alied Phyic, ol. 19,. L22-L227, May 1980. [14] T. Hanyu, Y. Yabe, and M. Kameyama, Multile-alued Programmable Logic Array Baed on a Reonant Tunneling Diode Model, IEICE Tran. Electronic, ol. E76-C,. 1,126-1,132, July 1993.

GONZÁLEZ AND MAZUMDER: MULTIPLE-ALUED SIGNED-DIGIT ADDER USING NEGATIE DIFFERENTIAL-RESISTANCE DEICES 959 [15] K.C. Smith, The Proect for Multialued Logic: A Technology and Alication iew, IEEE Tran. Comuter, ol. 30, no. 9,. 619-634, Set. 1981. [16] A.C. Seabaugh, Y.-C. Kao, and H.-T. Yuan, Nine-State Reonant Tunneling Diode Memory, IEEE J. Solid State Circuit, ol. 13,. 479-481, Set. 1992. [17] H.C. Lin, Reonant Tunneling Diode for Multi-alued Digital Alication, Proc. Int l Sym. Multile-alued Logic,. 188-195, 1994. [18] T. Waho, Reonant Tunneling Tranitor and It Alication to Multile-alued Logic Circuit, Proc. Int l Sym. Multile-alued Logic,. 130-138, 1995. [19] L.J. Micheel and H.L. Hartnagel, Intraband RTD with nanoelectronic HBT-LED Structure for Multile-alued Logic Comutation, Proc. Int l Sym. Multile-alued Logic,. 80-85, 1996. [20] S. Kawahito, M. Kameyama, and T. Higuchi, Multile-alued Radix-2 Signed-Digit Arithmetic Circuit for High-Performance LSI Sytem, IEEE J. Solid State Circuit, ol. 25,. 125-131, Feb. 1990. [21] U. König, M. Kuil, J.-F. Luy, and F. Schäffler, Si/SiGe Reonant Tunneling Deice Searated by Surrounding Polyilicon, Electronic Letter, ol. 25,. 1,169-1,171, 1989. [22] U. König, M. Kuil, F. Schäffler, G. Ficher, and T. Ki, Oerating CMOS After a Si-MBE Proce: A Precondition for Future Three- Dimenional Circuit, IEEE Electron Deice Letter, ol. 11,. 218-220, May 1990. [23] N. Eer, O. endier, C. Chun, M.R. Murti, J. Lakar, N.M. Jokert, T.S. Moie, and Y.-C. Kao, Thin Film Peudomorhic A1A/InGaA/InA Reonant Tunneling Diode Integrated onto Si Subtate, IEEE Electron Deice Letter, ol. 17,. 443-445, Set. 1996. [24] S.-J. Wei, H.C. Lin, R.C. Potter, and D. Shue, Dynamic Hyterei of the RTD Folding Circuit and It Limitation on the A/D Conerter, IEEE Tran. Circuit and Sytem II: Analog and Digital Signal Proceing, ol. 39,. 247-251, Ar. 1992. [25] S. Mohan, J.P. Sun, P. Mazumder, and G.I. Haddad, Deice and Circuit Simulation of Quantum Electronic Deice, IEEE Tran. Comuter-Aided Deign of Integrated Circuit and Sytem, ol. 14,. 653-662, June 1995. [26] S. Mohan, P. Mazumder, and G.I. Haddad, NDR SPICE: A Circuit Simulator for Reonant Tunneling Deice, Proc. Int l Comound Semiconductor Conf., Set. 1994. [27] S. Mohan, P. Mazumder, and G.I. Haddad, A New Circuit Simulator for Negatie Reitance Deice, Proc. Int l Electron Deice Meeting, Dec. 1994. [28] M. Kameyama and T. Higuchi, Deign of a Radix-4 Signed-Digit Arithmetic Circuit for Digital Filtering, Proc. Int l Sym. Multile- alued Logic,. 272-277, 1980. Alejandro F. González (S 96) receied the BE degree in electrical engineering (Licenciado en Ingeniería Electrónica) from the Intituto Tecnológico y de Etudio Sueriore de Occidente, Guadalajara, Mexico, in 1993, and the MSE degree in electrical engineering from the Unierity of Michigan, Ann Arbor, in 1995. He i currently uruing the PhD degree in electrical engineering at the Unierity of Michigan. Hi reearch interet include ultrafat digital circuit deign, multile-alued logic, and LSI deign automation. He i a tudent member of the IEEE. Pinaki Mazumder (S 84 M 87 SM 95) receied the BSEE degree from the Indian Intitute of Science in 1976, the MSc degree in comuter cience from the Unierity of Alberta, Canada, in 1985, and the PhD degree in electrical and comuter engineering from the Unierity of Illinoi at Urbana-Chamaign in 1987. For two year, he wa a reearch aitant with the Coordinated Science Laboratory, Unierity of Illinoi at Urbana-Chamaign. For more than ix year, he wa with Bharat Electronic Ltd. (a collaborator of RCA), India, where he deeloed analog and digital integrated circuit for conumer electronic roduct. During the ummer of 1985 and 1986, he wa a member of the technical taff in the Naerille, Illinoi, branch of AT&T Bell Laboratorie. He ent hi abbatical year a a iiting faculty member at Stanford Unierity, Unierity of California, Berkeley, and alo at Nion Telegrah and Telehone (NTT), Jaan. He i reently a rofeor in the Deartment of Electrical Engineering and Comuter Science at the Unierity of Michigan, Ann Arbor. Hi reearch interet include LSI teting, hyical deign automation, and ultrafat digital circuit deign. He ha written more than 100 aer for archial journal and international conference roceeding on thee toic. He ha coauthored two book entitled Teting and Tetable Deign of Random Acce Memorie (Kluwer, 1996) and Genetic Algorithm for LSI Layout and Tet Automation (Prentice Hall, 1998). Dr. Mazumder wa a reciient of Digital Incentie for Excellence Award, U.S. National Science Foundation Reearch Initiation Award, and Bell Northern Reearch Laboratory Faculty Award. He i an aociate editor of IEEE Tranaction on ery Large Scale Integration (LSI) Sytem. He wa a guet editor of IEEE Deign and Tet ecial iue on multimegabit memory teting, March 1993, a guet editor of Journal of Electronic Teting: Theory and Alication ecial iue on adanced technique for memory teting, Aril 1994, and a guet editor of IEEE Tranaction on LSI Sytem ecial iue on the imact of emerging technologie in LSI ytem, March 1998. He i a member of Sigma Xi, Phi Kaa Phi, the ACM Secial Interet Grou on Deign Automation, and a enior member of the IEEE.